From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Thu, 1 Nov 2018 13:09:46 +0100 Subject: [U-Boot] [PATCH 03/13] mmc: tmio: Do not set divider to 1 in DDR mode In-Reply-To: References: <20181031171606.13561-1-marek.vasut+renesas@gmail.com> <20181031171606.13561-3-marek.vasut+renesas@gmail.com> Message-ID: <2ae3c7de-f72d-4b6e-3f31-93989c4934d3@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 11/01/2018 12:39 PM, Masahiro Yamada wrote: > On Thu, Nov 1, 2018 at 2:22 AM Marek Vasut wrote: >> >> The TMIO core has a quirk where divider == 1 must not be set in DDR modes. >> Handle this by setting divider to 2, as suggested in the documentation. >> >> Signed-off-by: Marek Vasut >> Cc: Masahiro Yamada >> --- >> drivers/mmc/tmio-common.c | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c >> index 9eb2984ed3..072171d4b3 100644 >> --- a/drivers/mmc/tmio-common.c >> +++ b/drivers/mmc/tmio-common.c >> @@ -565,6 +565,10 @@ static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, >> >> divisor = DIV_ROUND_UP(mclk, mmc->clock); >> >> + /* Do not set divider to 0xff in DDR mode */ >> + if (mmc->ddr_mode && (divisor == 1)) >> + divisor = 2; >> + > > With this patch applied, my board would not boot any more. > > Please stop adding Renesas-specific quirks to tmio-common. > > By moving tmio_sd_set_clk_rate to a platform hook, > you can do anything you want to do in renesas-sdhi.c Are you sure this is renesas-specific ? My understanding is this is common to SDHI. I am happy to pull this whole thing into renesas specific part of the driver, but then you won't get all the clock fixes and there'll be duplication of code. -- Best regards, Marek Vasut