From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Mon, 25 Sep 2017 11:20:24 +0200 Subject: [U-Boot] [PATCH v2 14/19] arm: socfpga: Enable build for DDR Arria 10 In-Reply-To: <1506328815-23733-15-git-send-email-tien.fong.chee@intel.com> References: <1506328815-23733-1-git-send-email-tien.fong.chee@intel.com> <1506328815-23733-15-git-send-email-tien.fong.chee@intel.com> Message-ID: <2b0dec3a-6d53-f10f-55a5-4dbdd1659691@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote: > From: Tien Fong Chee > > This patch is for enabling the DDR support on Arria 10. > > Signed-off-by: Tien Fong Chee > --- > drivers/ddr/altera/Makefile | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile > index ac4ab85..02f8b7c 100644 > --- a/drivers/ddr/altera/Makefile > +++ b/drivers/ddr/altera/Makefile > @@ -10,4 +10,5 @@ > > ifdef CONFIG_ALTERA_SDRAM > obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o > +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o > endif > This should be part of the patch which added the sdram_arria10.c -- Best regards, Marek Vasut