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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id o16-20020ac25e30000000b00492ea54beeasm185736lfg.306.2022.09.20.01.21.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 20 Sep 2022 01:21:50 -0700 (PDT) Message-ID: <2b0e6e33-ef76-4bd4-8894-53f9a3fe68b4@linaro.org> Date: Tue, 20 Sep 2022 10:21:49 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 Subject: Re: [PATCH v2 1/2] dt-binding: pinctrl: Add NPCM8XX pinctrl and GPIO documentation Content-Language: en-US To: Tomer Maimon Cc: Rob Herring , Avi Fishman , Tali Perry , Joel Stanley , Patrick Venture , Nancy Yuen , Benjamin Fair , Linus Walleij , Krzysztof Kozlowski , =?UTF-8?Q?Jonathan_Neusch=c3=a4fer?= , zhengbin13@huawei.com, OpenBMC Maillist , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , devicetree References: <20220714122322.63663-1-tmaimon77@gmail.com> <20220714122322.63663-2-tmaimon77@gmail.com> <20220718211046.GA3547663-robh@kernel.org> <3981e6e8-d4bb-b13d-7aaa-7aea83ffaad9@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On 20/09/2022 09:59, Tomer Maimon wrote: >>>>>>> + pinctrl: pinctrl@f0800000 { >>>>>>> + compatible = "nuvoton,npcm845-pinctrl"; >>>>>>> + ranges = <0x0 0x0 0xf0010000 0x8000>; >>>>>>> + #address-cells = <1>; >>>>>>> + #size-cells = <1>; >>>>>>> + nuvoton,sysgcr = <&gcr>; >>>>>>> + >>>>>>> + gpio0: gpio@f0010000 { >>>>>> >>>>>> gpio@0 >>>>>> >>>>>> Is this really a child block of the pinctrl? Doesn't really look like it >>>>>> based on addressess. Where are the pinctrl registers? In the sysgcr? If >>>>>> so, then pinctrl should be a child of it. But that doesn't really work >>>>>> too well with gpio child nodes... >>>>> the pin controller mux is handled by sysgcr this is why the sysgcr in >>>>> the mother node, >>>>> and the pin configuration are handled by the GPIO registers. each >>>>> GPIO bank (child) contains 32 GPIO. >>>>> this is why the GPIO is the child node. >>>> >>>> Then maybe pinctrl should be the sysgcr and expose regmap for other devices? >>> The pin controller using the sysgcr to handle the pinmux, this is why >>> the sysgcr is in the mother node, is it problematic? >> >> You said pin-controller mux registers are in sysgcr, so it should not be >> used via syscon. > Sorry but maybe I missed something. > the sysgcr is used for miscellaneous features and not only for the pin > controller mux, this is why it used syscon and defined in the dtsi: > gcr: system-controller@f0800000 { > compatible = "nuvoton,npcm845-gcr", "syscon"; > reg = <0x0 0xf0800000 0x0 0x1000>; > }; >> >> Please provide address map description to convince us that this is >> correct HW representation. > GCR (sysgcr) registers 0xf0800000-0xf0801000 - used for miscellaneous > features, not only pin mux. > GPIO0 0xf0010000-0xf0011000 > GPIO1 0xf0011000-0xf0012000 > ... > GPIO7 0xf0017000-0xf0018000 >> Then why your pinctrl is in sysgcr IO range? (pinctrl@f0800000) Your map looks quite different from what you described in example. Best regards, Krzysztof