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From: Dave Hansen <dave.hansen@intel.com>
To: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>, x86@kernel.org
Cc: Ricardo Neri <ricardo.neri@intel.com>,
	linux-kernel@vger.kernel.org,
	Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>,
	Len Brown <len.brown@intel.com>,
	"Rafael J. Wysocki" <rafael.j.wysocki@intel.com>,
	Zhang Rui <rui.zhang@intel.com>, Chen Yu <yu.c.chen@intel.com>,
	stable@vger.kernel.org
Subject: Re: [PATCH] x86/cacheinfo: Define per-CPU num_cache_leaves
Date: Mon, 20 Mar 2023 09:44:04 -0700	[thread overview]
Message-ID: <2b1b5ded-522f-1fcf-6daa-354796bedb74@intel.com> (raw)
In-Reply-To: <20230314231658.30169-1-ricardo.neri-calderon@linux.intel.com>

On 3/14/23 16:16, Ricardo Neri wrote:
> -static unsigned short num_cache_leaves;
> +static DEFINE_PER_CPU(unsigned short, num_cache_leaves);
> +
> +static inline unsigned short get_num_cache_leaves(unsigned int cpu)
> +{
> +	return per_cpu(num_cache_leaves, cpu);
> +}

I know it's in generic code, but we do already have this:

static DEFINE_PER_CPU(struct cpu_cacheinfo, ci_cpu_cacheinfo);

which has a num_leaves in it:

struct cpu_cacheinfo {
        struct cacheinfo *info_list;
        unsigned int num_levels;
        unsigned int num_leaves;
        bool cpu_map_populated;
};

That's currently _populated_ from the arch code that you are modifying.
Do we really need this data stored identically in two different per-cpu
locations?

I'd also love to hear some more background on "Intel Meteor Lake" and
_why_ it has an asymmetric cache topology.

  reply	other threads:[~2023-03-20 16:53 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-14 23:16 [PATCH] x86/cacheinfo: Define per-CPU num_cache_leaves Ricardo Neri
2023-03-20 16:44 ` Dave Hansen [this message]
2023-03-24  1:07   ` Ricardo Neri
  -- strict thread matches above, loose matches on Subject: below --
2023-03-14 23:15 Ricardo Neri
2023-03-14 23:23 ` Ricardo Neri

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