From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46354) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ehPbH-0000cs-Pi for qemu-devel@nongnu.org; Thu, 01 Feb 2018 19:54:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ehPVG-0000Vm-Iz for qemu-devel@nongnu.org; Thu, 01 Feb 2018 19:48:00 -0500 Received: from mail-cys01nam02on0050.outbound.protection.outlook.com ([104.47.37.50]:48816 helo=NAM02-CY1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ehPVG-0000TG-1W for qemu-devel@nongnu.org; Thu, 01 Feb 2018 19:46:54 -0500 From: Alistair Francis Date: Thu, 1 Feb 2018 16:42:15 -0800 Message-ID: <2b1f2a135fcc38848a3cbd8746b87b526fe43351.1517532021.git.alistair.francis@xilinx.com> In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v5 5/6] xlnx-zcu102: Specify the valid CPUs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: alistair.francis@xilinx.com, alistair23@gmail.com, ehabkost@redhat.com, marcel@redhat.com, imammedo@redhat.com, f4bug@amsat.org, peter.maydell@linaro.org List all possible valid CPU options. Signed-off-by: Alistair Francis Reviewed-by: Eduardo Habkost Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- An implementation for single CPU machines is still being discussed. A solution proposed by Eduardo is this: 1) Change the default on TYPE_MACHINE to: mc->valid_cpu_types =3D { TYPE_CPU, NULL }; This will keep the existing behavior for all boards. 2) mc->valid_cpu_types=3DNULL be interpreted as "no CPU model except the default is accepted" or "-cpu is not accepted" in machine_run_board_init() (I prefer the former, but both options would be correct) 3) Boards like xlnx_zynqmp could then just do this: static void xxx_class_init(...) { mc->default_cpu_type =3D MY_CPU_TYPE; /* Reason: XXX_init() is hardcoded to MY_CPU_TYPE */ mc->valid_cpu_types =3D NULL; } V5: - Use cpu_model names V4: - Remove spaces V3: - Make variable static V2: - Don't use the users -cpu - Fixup allignment hw/arm/xlnx-zcu102.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index b126cf148b..994b19a36f 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -184,6 +184,11 @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineSta= te *machine) arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_zcu102_binfo); } =20 +static const char *xlnx_zynqmp_valid_cpus[] =3D { + "cortex-a53", + NULL +}; + static void xlnx_ep108_init(MachineState *machine) { XlnxZCU102 *s =3D EP108_MACHINE(machine); @@ -216,6 +221,12 @@ static void xlnx_ep108_machine_class_init(ObjectClass = *oc, void *data) mc->ignore_memory_transaction_failures =3D true; mc->max_cpus =3D XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS; mc->default_cpus =3D XLNX_ZYNQMP_NUM_APU_CPUS; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a53"); + /* The ZynqMP SoC is always a Cortex-A53. We add this here to give + * users a sane error if they specify a different CPU, but we never + * use their CPU choice. + */ + mc->valid_cpu_types =3D xlnx_zynqmp_valid_cpus; } =20 static const TypeInfo xlnx_ep108_machine_init_typeinfo =3D { @@ -274,6 +285,12 @@ static void xlnx_zcu102_machine_class_init(ObjectClass= *oc, void *data) mc->ignore_memory_transaction_failures =3D true; mc->max_cpus =3D XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS; mc->default_cpus =3D XLNX_ZYNQMP_NUM_APU_CPUS; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a53"); + /* The ZynqMP SoC is always a Cortex-A53. We add this here to give + * users a sane error if they specify a different CPU, but we never + * use their CPU choice. + */ + mc->valid_cpu_types =3D xlnx_zynqmp_valid_cpus; } =20 static const TypeInfo xlnx_zcu102_machine_init_typeinfo =3D { --=20 2.14.1