From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55951) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bmzcG-0004iW-DJ for qemu-devel@nongnu.org; Thu, 22 Sep 2016 04:44:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bmzcA-0008Vv-Aq for qemu-devel@nongnu.org; Thu, 22 Sep 2016 04:44:23 -0400 Received: from mo69.mail-out.ovh.net ([178.32.228.69]:60088) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bmzc9-0008VS-VP for qemu-devel@nongnu.org; Thu, 22 Sep 2016 04:44:18 -0400 Received: from player779.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo69.mail-out.ovh.net (Postfix) with ESMTP id 1B02BFF850C for ; Thu, 22 Sep 2016 10:44:16 +0200 (CEST) References: <1473943560-14846-1-git-send-email-clg@kaod.org> <1473943560-14846-11-git-send-email-clg@kaod.org> <20160921063035.GF20488@umbus> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: <2bf61d99-ac3b-251e-27d3-c8bb9b519b0f@kaod.org> Date: Thu, 22 Sep 2016 10:44:13 +0200 MIME-Version: 1.0 In-Reply-To: <20160921063035.GF20488@umbus> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v3 10/10] ppc/pnv: add a ISA bus List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson Cc: qemu-ppc@nongnu.org, Benjamin Herrenschmidt , qemu-devel@nongnu.org >> +static ISABus *pnv_isa_create(PnvChip *chip) >> +{ >> + PnvLpcController *lpc = &chip->lpc; >> + ISABus *isa_bus; >> + qemu_irq *irqs; >> + PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); >> + >> + /* Instanciate ISA bus. let isa_bus_new() create its own bridge on > > Instantiate has 3 't's and no 'c's; English orthography strikes again. he :) thanks. >> + * sysbus otherwise devices speficied on the command line will >> + * fail to create. >> + */ >> + isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, >> + &error_fatal); > > It's not clear to me if this belongs in the chip code or on the lpc > code - the lpc does create a device node as 'isa@', although it also > does some other stuff. In fact, the isabus in the qemu model is at the machine level, see below, next to the 'Instanc^Htiate'. each chip has a lpc controller but skiboot use a default one to route the traffic. So we choose the chip[0] one for that. Looking closer, I should make sure the "primary" cell is not added in the device tree for chip_id != 0. Thanks, C. >> + >> + /* Not all variants have a working serial irq decoder. If not, >> + * handling of LPC interrupts becomes a platform issue (some >> + * platforms have a CPLD to do it). >> + */ >> + if (pcc->chip_type == PNV_CHIP_POWER8NVL) { >> + irqs = qemu_allocate_irqs(pnv_lpc_isa_irq_handler, lpc, 16); >> + } else { >> + irqs = qemu_allocate_irqs(pnv_lpc_isa_irq_handler_cpld, NULL, 16); >> + } >> + >> + isa_bus_irqs(isa_bus, irqs); >> + return isa_bus; >> +} >> + >> static void ppc_powernv_init(MachineState *machine) >> { >> PnvMachineState *pnv = POWERNV_MACHINE(machine); >> @@ -389,6 +444,15 @@ static void ppc_powernv_init(MachineState *machine) >> object_property_set_bool(chip, true, "realized", &error_fatal); >> } >> g_free(chip_typename); >> + >> + /* Instanciate ISA bus on chip 0 */ >> + pnv->isa_bus = pnv_isa_create(pnv->chips[0]); >> + >> + /* Create serial port */ >> + serial_hds_isa_init(pnv->isa_bus, MAX_SERIAL_PORTS); >> + >> + /* Create an RTC ISA device too */ >> + rtc_init(pnv->isa_bus, 2000, NULL); >> } >> >> static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) >> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h >> index a30579a5817f..e75f937d40dd 100644 >> --- a/include/hw/ppc/pnv.h >> +++ b/include/hw/ppc/pnv.h >> @@ -123,6 +123,8 @@ typedef struct PnvMachineState { >> >> uint32_t num_chips; >> PnvChip **chips; >> + >> + ISABus *isa_bus; >> } PnvMachineState; >> >> #define POWERNV_FDT_ADDR 0x01000000 >