[Qemu-devel] [PATCH 0/9] Honor CPU_DUMP_FPU

[Qemu-devel] [PATCH 0/9] Honor CPU_DUMP_FPU

[Richard Henderson]

With Peter's new patch for "-d fpu", it makes sense to honor
this setting in as many targets as currently dump the fpu.


r~


Richard Henderson (9):
  target/alpha: Honor CPU_DUMP_FPU
  target/mips: Honor CPU_DUMP_FPU
  target/ppc: Honor CPU_DUMP_FPU
  target/riscv: Introduce cpu_riscv_get_fcsr
  target/riscv: Honor CPU_DUMP_FPU
  target/s390x: Honor CPU_DUMP_FPU
  target/sparc: Honor CPU_DUMP_FPU
  target/unicore32: Honor CPU_DUMP_FPU
  target/xtensa: Honor CPU_DUMP_FPU

 target/riscv/cpu.h           |  1 +
 target/alpha/helper.c        | 17 ++++++++---------
 target/mips/translate.c      |  3 ++-
 target/ppc/translate.c       | 20 +++++++++++++-------
 target/riscv/cpu.c           | 16 +++++++++++-----
 target/riscv/fpu_helper.c    |  6 ++++++
 target/riscv/op_helper.c     |  3 +--
 target/s390x/helper.c        | 23 ++++++++++++-----------
 target/sparc/cpu.c           | 17 ++++++++++-------
 target/unicore32/translate.c |  4 +++-
 target/xtensa/translate.c    |  3 ++-
 11 files changed, 69 insertions(+), 44 deletions(-)

-- 
2.17.0

[Qemu-devel] [PATCH 1/9] target/alpha: Honor CPU_DUMP_FPU

[Richard Henderson]

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/alpha/helper.c | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/target/alpha/helper.c b/target/alpha/helper.c
index 8a6a948572..57e2c212b3 100644
--- a/target/alpha/helper.c
+++ b/target/alpha/helper.c
@@ -442,20 +442,19 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
     cpu_fprintf(f, "     PC  " TARGET_FMT_lx "      PS  %02x\n",
                 env->pc, extract32(env->flags, ENV_FLAG_PS_SHIFT, 8));
     for (i = 0; i < 31; i++) {
-        cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx " ", i,
-                    linux_reg_names[i], cpu_alpha_load_gr(env, i));
-        if ((i % 3) == 2)
-            cpu_fprintf(f, "\n");
+        cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx "%c", i,
+                    linux_reg_names[i], cpu_alpha_load_gr(env, i),
+                    (i % 3) == 2 ? '\n' : ' ');
     }
 
     cpu_fprintf(f, "lock_a   " TARGET_FMT_lx " lock_v   " TARGET_FMT_lx "\n",
                 env->lock_addr, env->lock_value);
 
-    for (i = 0; i < 31; i++) {
-        cpu_fprintf(f, "FIR%02d    " TARGET_FMT_lx " ", i,
-                    *((uint64_t *)(&env->fir[i])));
-        if ((i % 3) == 2)
-            cpu_fprintf(f, "\n");
+    if (flags & CPU_DUMP_FPU) {
+        for (i = 0; i < 31; i++) {
+            cpu_fprintf(f, "FIR%02d    %016" PRIx64 "%c", i, env->fir[i],
+                        (i % 3) == 2 ? '\n' : ' ');
+        }
     }
     cpu_fprintf(f, "\n");
 }
-- 
2.17.0

[Qemu-devel] [PATCH 2/9] target/mips: Honor CPU_DUMP_FPU

[Richard Henderson]

Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/mips/translate.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index d05ee67e63..136947adc5 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -20445,8 +20445,9 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
                 env->CP0_Config2, env->CP0_Config3);
     cpu_fprintf(f, "    Config4 0x%08x Config5 0x%08x\n",
                 env->CP0_Config4, env->CP0_Config5);
-    if (env->hflags & MIPS_HFLAG_FPU)
+    if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) {
         fpu_dump_state(env, f, cpu_fprintf, flags);
+    }
 }
 
 void mips_tcg_init(void)
-- 
2.17.0

[Qemu-devel] [PATCH 3/9] target/ppc: Honor CPU_DUMP_FPU

[Richard Henderson]

Cc: Alexander Graf <agraf@suse.de>
Cc: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/ppc/translate.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 2a4140f420..fd66c80cc7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7048,14 +7048,20 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
     }
     cpu_fprintf(f, " ]             RES " TARGET_FMT_lx "\n",
                 env->reserve_addr);
-    for (i = 0; i < 32; i++) {
-        if ((i & (RFPL - 1)) == 0)
-            cpu_fprintf(f, "FPR%02d", i);
-        cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
-        if ((i & (RFPL - 1)) == (RFPL - 1))
-            cpu_fprintf(f, "\n");
+
+    if (flags & CPU_DUMP_FPU) {
+        for (i = 0; i < 32; i++) {
+            if ((i & (RFPL - 1)) == 0) {
+                cpu_fprintf(f, "FPR%02d", i);
+            }
+            cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
+            if ((i & (RFPL - 1)) == (RFPL - 1)) {
+                cpu_fprintf(f, "\n");
+            }
+        }
+        cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
     }
-    cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
+
 #if !defined(CONFIG_USER_ONLY)
     cpu_fprintf(f, " SRR0 " TARGET_FMT_lx "  SRR1 " TARGET_FMT_lx
                    "    PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
-- 
2.17.0

[Qemu-devel] [PATCH 4/9] target/riscv: Introduce cpu_riscv_get_fcsr

[Richard Henderson]

Cc: Michael Clark <mjc@sifive.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/cpu.h        | 1 +
 target/riscv/fpu_helper.c | 6 ++++++
 target/riscv/op_helper.c  | 3 +--
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 34abc383e3..f2bc243b95 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -265,6 +265,7 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
                                           uint32_t exception, uintptr_t pc);
 
 target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
+target_ulong cpu_riscv_get_fcsr(CPURISCVState *env);
 void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
 
 #define TB_FLAGS_MMU_MASK  3
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index abbadead5c..41c7352115 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -37,6 +37,12 @@ target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
     return hard;
 }
 
+target_ulong cpu_riscv_get_fcsr(CPURISCVState *env)
+{
+    return (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
+         | (env->frm << FSR_RD_SHIFT);
+}
+
 void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong hard)
 {
     int soft = 0;
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 3abf52453c..fd2d8c0a9d 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -423,8 +423,7 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
         return env->frm;
     case CSR_FCSR:
         validate_mstatus_fs(env, GETPC());
-        return (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
-                | (env->frm << FSR_RD_SHIFT);
+        return cpu_riscv_get_fcsr(env);
     /* rdtime/rdtimeh is trapped and emulated by bbl in system mode */
 #ifdef CONFIG_USER_ONLY
     case CSR_TIME:
-- 
2.17.0

[Qemu-devel] [PATCH 5/9] target/riscv: Honor CPU_DUMP_FPU

[Richard Henderson]

Cc: Michael Clark <mjc@sifive.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/cpu.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4e5a56d4e3..4612f324c9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -199,6 +199,10 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,
     int i;
 
     cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
+    if (flags & CPU_DUMP_FPU) {
+        cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "fcsr    ",
+                    cpu_riscv_get_fcsr(env));
+    }
 #ifndef CONFIG_USER_ONLY
     cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
     cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
@@ -219,11 +223,13 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,
             cpu_fprintf(f, "\n");
         }
     }
-    for (i = 0; i < 32; i++) {
-        cpu_fprintf(f, " %s %016" PRIx64,
-            riscv_fpr_regnames[i], env->fpr[i]);
-        if ((i & 3) == 3) {
-            cpu_fprintf(f, "\n");
+    if (flags & CPU_DUMP_FPU) {
+        for (i = 0; i < 32; i++) {
+            cpu_fprintf(f, " %s %016" PRIx64,
+                riscv_fpr_regnames[i], env->fpr[i]);
+            if ((i & 3) == 3) {
+                cpu_fprintf(f, "\n");
+            }
         }
     }
 }
-- 
2.17.0

[Qemu-devel] [PATCH 6/9] target/s390x: Honor CPU_DUMP_FPU

[Richard Henderson]

Also do not dump both "fpu" and "vector" registers
as the former overlaps the latter.

Cc: Alexander Graf <agraf@suse.de>
Cc: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/s390x/helper.c | 23 ++++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/target/s390x/helper.c b/target/s390x/helper.c
index e8548f340a..fd5791f134 100644
--- a/target/s390x/helper.c
+++ b/target/s390x/helper.c
@@ -327,21 +327,22 @@ void s390_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
         }
     }
 
-    for (i = 0; i < 16; i++) {
-        cpu_fprintf(f, "F%02d=%016" PRIx64, i, get_freg(env, i)->ll);
-        if ((i % 4) == 3) {
-            cpu_fprintf(f, "\n");
+    if (flags & CPU_DUMP_FPU) {
+        if (s390_has_feat(S390_FEAT_VECTOR)) {
+            for (i = 0; i < 32; i++) {
+                cpu_fprintf(f, "V%02d=%016" PRIx64 "%016" PRIx64 "%c",
+                            i, env->vregs[i][0].ll, env->vregs[i][1].ll,
+                            i % 2 ? '\n' : ' ');
+            }
         } else {
-            cpu_fprintf(f, " ");
+            for (i = 0; i < 16; i++) {
+                cpu_fprintf(f, "F%02d=%016" PRIx64 "%c",
+                            i, get_freg(env, i)->ll,
+                            (i % 4) == 3 ? '\n' : ' ');
+            }
         }
     }
 
-    for (i = 0; i < 32; i++) {
-        cpu_fprintf(f, "V%02d=%016" PRIx64 "%016" PRIx64, i,
-                    env->vregs[i][0].ll, env->vregs[i][1].ll);
-        cpu_fprintf(f, (i % 2) ? "\n" : " ");
-    }
-
 #ifndef CONFIG_USER_ONLY
     for (i = 0; i < 16; i++) {
         cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
-- 
2.17.0

[Qemu-devel] [PATCH 7/9] target/sparc: Honor CPU_DUMP_FPU

[Richard Henderson]

Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Cc: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/cpu.c | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index ff6ed91f9a..0f090ece54 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -647,15 +647,18 @@ void sparc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
         }
     }
 
-    for (i = 0; i < TARGET_DPREGS; i++) {
-        if ((i & 3) == 0) {
-            cpu_fprintf(f, "%%f%02d: ", i * 2);
-        }
-        cpu_fprintf(f, " %016" PRIx64, env->fpr[i].ll);
-        if ((i & 3) == 3) {
-            cpu_fprintf(f, "\n");
+    if (flags & CPU_DUMP_FPU) {
+        for (i = 0; i < TARGET_DPREGS; i++) {
+            if ((i & 3) == 0) {
+                cpu_fprintf(f, "%%f%02d: ", i * 2);
+            }
+            cpu_fprintf(f, " %016" PRIx64, env->fpr[i].ll);
+            if ((i & 3) == 3) {
+                cpu_fprintf(f, "\n");
+            }
         }
     }
+
 #ifdef TARGET_SPARC64
     cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate,
                 (unsigned)cpu_get_ccr(env));
-- 
2.17.0

[Qemu-devel] [PATCH 8/9] target/unicore32: Honor CPU_DUMP_FPU

[Richard Henderson]

Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/unicore32/translate.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
index 5b51f2166d..63619e7d2c 100644
--- a/target/unicore32/translate.c
+++ b/target/unicore32/translate.c
@@ -2101,7 +2101,9 @@ void uc32_cpu_dump_state(CPUState *cs, FILE *f,
                 psr & (1 << 28) ? 'V' : '-',
                 cpu_mode_names[psr & 0xf]);
 
-    cpu_dump_state_ucf64(env, f, cpu_fprintf, flags);
+    if (flags & CPU_DUMP_FPU) {
+        cpu_dump_state_ucf64(env, f, cpu_fprintf, flags);
+    }
 }
 
 void restore_state_to_opc(CPUUniCore32State *env, TranslationBlock *tb,
-- 
2.17.0

[Qemu-devel] [PATCH 9/9] target/xtensa: Honor CPU_DUMP_FPU

[Richard Henderson]

Cc: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/xtensa/translate.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 4f6d03059f..2afe395ecf 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1244,7 +1244,8 @@ void xtensa_cpu_dump_state(CPUState *cs, FILE *f,
         }
     }
 
-    if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
+    if ((flags & CPU_DUMP_FPU) &&
+        xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
         cpu_fprintf(f, "\n");
 
         for (i = 0; i < 16; ++i) {
-- 
2.17.0

Re: [Qemu-devel] [PATCH 9/9] target/xtensa: Honor CPU_DUMP_FPU

[Max Filippov]

On Thu, May 10, 2018 at 8:52 PM, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Cc: Max Filippov <jcmvbkbc@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/xtensa/translate.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

Acked-by: Max Filippov <jcmvbkbc@gmail.com>

-- 
Thanks.
-- Max

Re: [Qemu-devel] [PATCH 6/9] target/s390x: Honor CPU_DUMP_FPU

[David Hildenbrand]

On 11.05.2018 05:52, Richard Henderson wrote:
> Also do not dump both "fpu" and "vector" registers
> as the former overlaps the latter.
> 
> Cc: Alexander Graf <agraf@suse.de>
> Cc: David Hildenbrand <david@redhat.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/s390x/helper.c | 23 ++++++++++++-----------
>  1 file changed, 12 insertions(+), 11 deletions(-)
> 
> diff --git a/target/s390x/helper.c b/target/s390x/helper.c
> index e8548f340a..fd5791f134 100644
> --- a/target/s390x/helper.c
> +++ b/target/s390x/helper.c
> @@ -327,21 +327,22 @@ void s390_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
>          }
>      }
>  
> -    for (i = 0; i < 16; i++) {
> -        cpu_fprintf(f, "F%02d=%016" PRIx64, i, get_freg(env, i)->ll);
> -        if ((i % 4) == 3) {
> -            cpu_fprintf(f, "\n");
> +    if (flags & CPU_DUMP_FPU) {
> +        if (s390_has_feat(S390_FEAT_VECTOR)) {

CPU model should always be initialized at this point, so this check
actually returns the right thing.

Reviewed-by: David Hildenbrand <david@redhat.com>

> +            for (i = 0; i < 32; i++) {
> +                cpu_fprintf(f, "V%02d=%016" PRIx64 "%016" PRIx64 "%c",
> +                            i, env->vregs[i][0].ll, env->vregs[i][1].ll,
> +                            i % 2 ? '\n' : ' ');
> +            }
>          } else {
> -            cpu_fprintf(f, " ");
> +            for (i = 0; i < 16; i++) {
> +                cpu_fprintf(f, "F%02d=%016" PRIx64 "%c",
> +                            i, get_freg(env, i)->ll,
> +                            (i % 4) == 3 ? '\n' : ' ');
> +            }
>          }
>      }
>  
> -    for (i = 0; i < 32; i++) {
> -        cpu_fprintf(f, "V%02d=%016" PRIx64 "%016" PRIx64, i,
> -                    env->vregs[i][0].ll, env->vregs[i][1].ll);
> -        cpu_fprintf(f, (i % 2) ? "\n" : " ");
> -    }
> -
>  #ifndef CONFIG_USER_ONLY
>      for (i = 0; i < 16; i++) {
>          cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
> 


-- 

Thanks,

David / dhildenb

Re: [Qemu-devel] [PATCH 1/9] target/alpha: Honor CPU_DUMP_FPU

[Philippe Mathieu-Daudé]

On 05/11/2018 12:52 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/alpha/helper.c | 17 ++++++++---------
>  1 file changed, 8 insertions(+), 9 deletions(-)
> 
> diff --git a/target/alpha/helper.c b/target/alpha/helper.c
> index 8a6a948572..57e2c212b3 100644
> --- a/target/alpha/helper.c
> +++ b/target/alpha/helper.c
> @@ -442,20 +442,19 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
>      cpu_fprintf(f, "     PC  " TARGET_FMT_lx "      PS  %02x\n",
>                  env->pc, extract32(env->flags, ENV_FLAG_PS_SHIFT, 8));
>      for (i = 0; i < 31; i++) {
> -        cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx " ", i,
> -                    linux_reg_names[i], cpu_alpha_load_gr(env, i));
> -        if ((i % 3) == 2)
> -            cpu_fprintf(f, "\n");
> +        cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx "%c", i,
> +                    linux_reg_names[i], cpu_alpha_load_gr(env, i),
> +                    (i % 3) == 2 ? '\n' : ' ');
>      }
>  
>      cpu_fprintf(f, "lock_a   " TARGET_FMT_lx " lock_v   " TARGET_FMT_lx "\n",
>                  env->lock_addr, env->lock_value);
>  
> -    for (i = 0; i < 31; i++) {
> -        cpu_fprintf(f, "FIR%02d    " TARGET_FMT_lx " ", i,
> -                    *((uint64_t *)(&env->fir[i])));
> -        if ((i % 3) == 2)
> -            cpu_fprintf(f, "\n");
> +    if (flags & CPU_DUMP_FPU) {
> +        for (i = 0; i < 31; i++) {
> +            cpu_fprintf(f, "FIR%02d    %016" PRIx64 "%c", i, env->fir[i],

Cleaner :)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> +                        (i % 3) == 2 ? '\n' : ' ');
> +        }
>      }
>      cpu_fprintf(f, "\n");
>  }
> 

Re: [Qemu-devel] [PATCH 2/9] target/mips: Honor CPU_DUMP_FPU

[Philippe Mathieu-Daudé]

On 05/11/2018 12:52 AM, Richard Henderson wrote:
> Cc: Aurelien Jarno <aurelien@aurel32.net>
> Cc: Yongbok Kim <yongbok.kim@mips.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  target/mips/translate.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index d05ee67e63..136947adc5 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -20445,8 +20445,9 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
>                  env->CP0_Config2, env->CP0_Config3);
>      cpu_fprintf(f, "    Config4 0x%08x Config5 0x%08x\n",
>                  env->CP0_Config4, env->CP0_Config5);
> -    if (env->hflags & MIPS_HFLAG_FPU)
> +    if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) {
>          fpu_dump_state(env, f, cpu_fprintf, flags);
> +    }
>  }
>  
>  void mips_tcg_init(void)
> 

Re: [Qemu-devel] [PATCH 3/9] target/ppc: Honor CPU_DUMP_FPU

[Philippe Mathieu-Daudé]

On 05/11/2018 12:52 AM, Richard Henderson wrote:
> Cc: Alexander Graf <agraf@suse.de>
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  target/ppc/translate.c | 20 +++++++++++++-------
>  1 file changed, 13 insertions(+), 7 deletions(-)
> 
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 2a4140f420..fd66c80cc7 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -7048,14 +7048,20 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
>      }
>      cpu_fprintf(f, " ]             RES " TARGET_FMT_lx "\n",
>                  env->reserve_addr);
> -    for (i = 0; i < 32; i++) {
> -        if ((i & (RFPL - 1)) == 0)
> -            cpu_fprintf(f, "FPR%02d", i);
> -        cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
> -        if ((i & (RFPL - 1)) == (RFPL - 1))
> -            cpu_fprintf(f, "\n");
> +
> +    if (flags & CPU_DUMP_FPU) {
> +        for (i = 0; i < 32; i++) {
> +            if ((i & (RFPL - 1)) == 0) {
> +                cpu_fprintf(f, "FPR%02d", i);
> +            }
> +            cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
> +            if ((i & (RFPL - 1)) == (RFPL - 1)) {
> +                cpu_fprintf(f, "\n");
> +            }
> +        }
> +        cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
>      }
> -    cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
> +
>  #if !defined(CONFIG_USER_ONLY)
>      cpu_fprintf(f, " SRR0 " TARGET_FMT_lx "  SRR1 " TARGET_FMT_lx
>                     "    PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
> 

Re: [Qemu-devel] [PATCH 4/9] target/riscv: Introduce cpu_riscv_get_fcsr

[Philippe Mathieu-Daudé]

On 05/11/2018 12:52 AM, Richard Henderson wrote:
> Cc: Michael Clark <mjc@sifive.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  target/riscv/cpu.h        | 1 +
>  target/riscv/fpu_helper.c | 6 ++++++
>  target/riscv/op_helper.c  | 3 +--
>  3 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 34abc383e3..f2bc243b95 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -265,6 +265,7 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
>                                            uint32_t exception, uintptr_t pc);
>  
>  target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
> +target_ulong cpu_riscv_get_fcsr(CPURISCVState *env);
>  void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
>  
>  #define TB_FLAGS_MMU_MASK  3
> diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
> index abbadead5c..41c7352115 100644
> --- a/target/riscv/fpu_helper.c
> +++ b/target/riscv/fpu_helper.c
> @@ -37,6 +37,12 @@ target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
>      return hard;
>  }
>  
> +target_ulong cpu_riscv_get_fcsr(CPURISCVState *env)
> +{
> +    return (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
> +         | (env->frm << FSR_RD_SHIFT);
> +}
> +
>  void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong hard)
>  {
>      int soft = 0;
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 3abf52453c..fd2d8c0a9d 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -423,8 +423,7 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
>          return env->frm;
>      case CSR_FCSR:
>          validate_mstatus_fs(env, GETPC());
> -        return (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
> -                | (env->frm << FSR_RD_SHIFT);
> +        return cpu_riscv_get_fcsr(env);
>      /* rdtime/rdtimeh is trapped and emulated by bbl in system mode */
>  #ifdef CONFIG_USER_ONLY
>      case CSR_TIME:
> 

Re: [Qemu-devel] [PATCH 5/9] target/riscv: Honor CPU_DUMP_FPU

[Philippe Mathieu-Daudé]

On 05/11/2018 12:52 AM, Richard Henderson wrote:
> Cc: Michael Clark <mjc@sifive.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  target/riscv/cpu.c | 16 +++++++++++-----
>  1 file changed, 11 insertions(+), 5 deletions(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 4e5a56d4e3..4612f324c9 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -199,6 +199,10 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,
>      int i;
>  
>      cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
> +    if (flags & CPU_DUMP_FPU) {
> +        cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "fcsr    ",
> +                    cpu_riscv_get_fcsr(env));
> +    }
>  #ifndef CONFIG_USER_ONLY
>      cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
>      cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
> @@ -219,11 +223,13 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,
>              cpu_fprintf(f, "\n");
>          }
>      }
> -    for (i = 0; i < 32; i++) {
> -        cpu_fprintf(f, " %s %016" PRIx64,
> -            riscv_fpr_regnames[i], env->fpr[i]);
> -        if ((i & 3) == 3) {
> -            cpu_fprintf(f, "\n");
> +    if (flags & CPU_DUMP_FPU) {
> +        for (i = 0; i < 32; i++) {
> +            cpu_fprintf(f, " %s %016" PRIx64,
> +                riscv_fpr_regnames[i], env->fpr[i]);
> +            if ((i & 3) == 3) {
> +                cpu_fprintf(f, "\n");
> +            }
>          }
>      }
>  }
> 

Re: [Qemu-devel] [PATCH 7/9] target/sparc: Honor CPU_DUMP_FPU

[Philippe Mathieu-Daudé]

On 05/11/2018 12:52 AM, Richard Henderson wrote:
> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Cc: Artyom Tarasenko <atar4qemu@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  target/sparc/cpu.c | 17 ++++++++++-------
>  1 file changed, 10 insertions(+), 7 deletions(-)
> 
> diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
> index ff6ed91f9a..0f090ece54 100644
> --- a/target/sparc/cpu.c
> +++ b/target/sparc/cpu.c
> @@ -647,15 +647,18 @@ void sparc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
>          }
>      }
>  
> -    for (i = 0; i < TARGET_DPREGS; i++) {
> -        if ((i & 3) == 0) {
> -            cpu_fprintf(f, "%%f%02d: ", i * 2);
> -        }
> -        cpu_fprintf(f, " %016" PRIx64, env->fpr[i].ll);
> -        if ((i & 3) == 3) {
> -            cpu_fprintf(f, "\n");
> +    if (flags & CPU_DUMP_FPU) {
> +        for (i = 0; i < TARGET_DPREGS; i++) {
> +            if ((i & 3) == 0) {
> +                cpu_fprintf(f, "%%f%02d: ", i * 2);
> +            }
> +            cpu_fprintf(f, " %016" PRIx64, env->fpr[i].ll);
> +            if ((i & 3) == 3) {
> +                cpu_fprintf(f, "\n");
> +            }
>          }
>      }
> +
>  #ifdef TARGET_SPARC64
>      cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate,
>                  (unsigned)cpu_get_ccr(env));
> 

Re: [Qemu-devel] [PATCH 8/9] target/unicore32: Honor CPU_DUMP_FPU

[Philippe Mathieu-Daudé]

On 05/11/2018 12:52 AM, Richard Henderson wrote:
> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  target/unicore32/translate.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
> index 5b51f2166d..63619e7d2c 100644
> --- a/target/unicore32/translate.c
> +++ b/target/unicore32/translate.c
> @@ -2101,7 +2101,9 @@ void uc32_cpu_dump_state(CPUState *cs, FILE *f,
>                  psr & (1 << 28) ? 'V' : '-',
>                  cpu_mode_names[psr & 0xf]);
>  
> -    cpu_dump_state_ucf64(env, f, cpu_fprintf, flags);
> +    if (flags & CPU_DUMP_FPU) {
> +        cpu_dump_state_ucf64(env, f, cpu_fprintf, flags);
> +    }
>  }
>  
>  void restore_state_to_opc(CPUUniCore32State *env, TranslationBlock *tb,
> 

Re: [Qemu-devel] [PATCH 9/9] target/xtensa: Honor CPU_DUMP_FPU

[Philippe Mathieu-Daudé]

On 05/11/2018 12:52 AM, Richard Henderson wrote:
> Cc: Max Filippov <jcmvbkbc@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  target/xtensa/translate.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
> index 4f6d03059f..2afe395ecf 100644
> --- a/target/xtensa/translate.c
> +++ b/target/xtensa/translate.c
> @@ -1244,7 +1244,8 @@ void xtensa_cpu_dump_state(CPUState *cs, FILE *f,
>          }
>      }
>  
> -    if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
> +    if ((flags & CPU_DUMP_FPU) &&
> +        xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
>          cpu_fprintf(f, "\n");
>  
>          for (i = 0; i < 16; ++i) {
> 

Re: [Qemu-devel] [PATCH 5/9] target/riscv: Honor CPU_DUMP_FPU

[Michael Clark]

On Sun, May 13, 2018 at 12:52 PM, Philippe Mathieu-Daudé <f4bug@amsat.org>
wrote:

> On 05/11/2018 12:52 AM, Richard Henderson wrote:
> > Cc: Michael Clark <mjc@sifive.com>
> > Cc: Palmer Dabbelt <palmer@sifive.com>
> > Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> > Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


Reviewed-by: Michael Clark <mjc@sifive.com>


> > ---
> >  target/riscv/cpu.c | 16 +++++++++++-----
> >  1 file changed, 11 insertions(+), 5 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 4e5a56d4e3..4612f324c9 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -199,6 +199,10 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE
> *f,
> >      int i;
> >
> >      cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
> > +    if (flags & CPU_DUMP_FPU) {
> > +        cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "fcsr    ",
> > +                    cpu_riscv_get_fcsr(env));
> > +    }
> >  #ifndef CONFIG_USER_ONLY
> >      cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
> >      cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
> > @@ -219,11 +223,13 @@ static void riscv_cpu_dump_state(CPUState *cs,
> FILE *f,
> >              cpu_fprintf(f, "\n");
> >          }
> >      }
> > -    for (i = 0; i < 32; i++) {
> > -        cpu_fprintf(f, " %s %016" PRIx64,
> > -            riscv_fpr_regnames[i], env->fpr[i]);
> > -        if ((i & 3) == 3) {
> > -            cpu_fprintf(f, "\n");
> > +    if (flags & CPU_DUMP_FPU) {
> > +        for (i = 0; i < 32; i++) {
> > +            cpu_fprintf(f, " %s %016" PRIx64,
> > +                riscv_fpr_regnames[i], env->fpr[i]);
> > +            if ((i & 3) == 3) {
> > +                cpu_fprintf(f, "\n");
> > +            }
> >          }
> >      }
> >  }
> >
>

Re: [Qemu-devel] [PATCH 4/9] target/riscv: Introduce cpu_riscv_get_fcsr

[Michael Clark]

On Fri, May 11, 2018 at 3:52 PM, Richard Henderson <
richard.henderson@linaro.org> wrote:

> Cc: Michael Clark <mjc@sifive.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>

I'm not against this change but it conflicts with changes in the riscv
repo. I should post my patch queue to the list...

We have made a somewhat medium sized change and have unraveled two
monolithic switch statements out of csr_read_helper switch and
csr_write_helper into clearly decomposed functions for modifying control
and status registers, along with an interface to allow CPUs to hook custom
control and status registers. This was done to support atomic
read/modify/write CSRs which was not possible to achieve with the current
helpers which separately called via the csr_read_helper followed by
csr_write_helper. Given the only way to modify CSRs was via the switch
statements, we needed to move them out to provide a mechanism for CSRs that
wish to be truly atomic. e.g. 'mip'. The CSR functions are defined in The
RISC-V Instruction Set Manual Volume I: User-Level ISA Document Version 2.2
as "atomic" instructions:

- CSRRW (Atomic Read/Write CSR)
- CSRRS (Atomic Read and Set Bits in CSR)
- CSRRC (Atomic Read and Clear Bits in CSR)

We have thus changed QEMU to allow truly atomic CSR implementations. The
new implementation replaces the compiler doing compare/branch vs jump table
switch codegen for a sparse CSR address space with a single array of
function pointers. i.e. load, indirect jump. Along with this change we have
also renamed functions in target/riscv to use riscv_ prefix and added a
public interface to hook custom CSRs. The CSR changes will allow out of
tree code to hook custom CSRs without needing to change target/riscv code.

- riscv_cpu_ won over cpu_riscv_ given the number of functions conforming
with the former riscv_ prefix and the desire for consistency in target/riscv

In the riscv tree we now have riscv_csr_read(env, CSR_FCSR)
and riscv_csr_write(env, CSR_FCSR, fcsr) as the method to read and write
the composite. There is also a user in linux-user/riscv/signal.c that
should probably use the new interface. We could change
linux-user/riscv/signal.c to use your new interface however your interface
only provides a read method and no write method, so the write interface
remains in the (current) big CSR switch statement, leaving an inconsitency
between the encapsulation of read and write. We currently have the new fcsr
read and write encapsulated in static functions read_fcsr and write_fcsr in
a new csr module (which should perhaps be called csr_helper.c).

See:

- https://github.com/riscv/riscv-qemu/commits/qemu-2.13-for-upstream
-
https://github.com/riscv/riscv-qemu/commit/0783ce5ea580552b1f8e2f16a3e3cc1af19db69b
-
https://github.com/riscv/riscv-qemu/commit/fa17549fbc726e83a3c163b1534c7465147c6718


> ---
>  target/riscv/cpu.h        | 1 +
>  target/riscv/fpu_helper.c | 6 ++++++
>  target/riscv/op_helper.c  | 3 +--
>  3 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 34abc383e3..f2bc243b95 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -265,6 +265,7 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState
> *env,
>                                            uint32_t exception, uintptr_t
> pc);
>
>  target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
> +target_ulong cpu_riscv_get_fcsr(CPURISCVState *env);
>  void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
>
>  #define TB_FLAGS_MMU_MASK  3
> diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
> index abbadead5c..41c7352115 100644
> --- a/target/riscv/fpu_helper.c
> +++ b/target/riscv/fpu_helper.c
> @@ -37,6 +37,12 @@ target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
>      return hard;
>  }
>
> +target_ulong cpu_riscv_get_fcsr(CPURISCVState *env)
> +{
> +    return (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
> +         | (env->frm << FSR_RD_SHIFT);
> +}
> +
>  void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong hard)
>  {
>      int soft = 0;
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 3abf52453c..fd2d8c0a9d 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -423,8 +423,7 @@ target_ulong csr_read_helper(CPURISCVState *env,
> target_ulong csrno)
>          return env->frm;
>      case CSR_FCSR:
>          validate_mstatus_fs(env, GETPC());
> -        return (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
> -                | (env->frm << FSR_RD_SHIFT);
> +        return cpu_riscv_get_fcsr(env);
>      /* rdtime/rdtimeh is trapped and emulated by bbl in system mode */
>  #ifdef CONFIG_USER_ONLY
>      case CSR_TIME:
> --
> 2.17.0
>
>

Re: [Qemu-devel] [PATCH 4/9] target/riscv: Introduce cpu_riscv_get_fcsr

[Richard Henderson]

On 05/17/2018 07:46 PM, Michael Clark wrote:
> 
> 
> On Fri, May 11, 2018 at 3:52 PM, Richard Henderson
> <richard.henderson@linaro.org <mailto:richard.henderson@linaro.org>> wrote:
> 
>     Cc: Michael Clark <mjc@sifive.com <mailto:mjc@sifive.com>>
>     Cc: Palmer Dabbelt <palmer@sifive.com <mailto:palmer@sifive.com>>
>     Cc: Sagar Karandikar <sagark@eecs.berkeley.edu
>     <mailto:sagark@eecs.berkeley.edu>>
>     Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de
>     <mailto:kbastian@mail.uni-paderborn.de>>
>     Signed-off-by: Richard Henderson <richard.henderson@linaro.org
>     <mailto:richard.henderson@linaro.org>>
> 
> 
> I'm not against this change but it conflicts with changes in the riscv repo. I
> should post my patch queue to the list...

Ok, I'll drop this for now, and the dump of the FCSR in the next patch.
To be revisited once your csr reorg is upstream...


r~