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From: "Souza, Jose" <jose.souza@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>
Cc: "intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"dri-devel@lists.freedesktop.org"
	<dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH 4/4] drm/i915/display: Set TRANS_DDI_MODE_SELECT to default value when disabling TRANS_DDI
Date: Thu, 30 Jan 2020 20:07:07 +0000	[thread overview]
Message-ID: <2c578720445cfb0a036502b7dba94f1ebd2e8ca0.camel@intel.com> (raw)
In-Reply-To: <20200130172502.GH13686@intel.com>

On Thu, 2020-01-30 at 19:25 +0200, Ville Syrjälä wrote:
> On Thu, Jan 16, 2020 at 05:58:37PM -0800, José Roberto de Souza
> wrote:
> > TGL timeouts when disabling MST transcoder and fifo underruns over
> > MST
> > transcoders are fixed when setting TRANS_DDI_MODE_SELECT to 0(HDMI
> > mode) during the disable sequence.
> > 
> > Although BSpec disable sequence don't require this step it is a
> > harmless change and it is also done by Windows driver.
> > Anyhow HW team was notified about that but it can take some time to
> > documentation to be updated.
> > 
> > A case that always lead to those issues is:
> > - do a modeset enabling pipe A and pipe B in the same MST stream
> > leaving A as master
> > - disable pipe A, promote B as master doing a full modeset in A
> > - enable pipe A, changing the master transcoder back to A(doing a
> > full modeset in B)
> > - Pow: underruns and timeouts
> > 
> > The transcoders involved will only work again when complete
> > disabled
> > and their power wells turned off causing a reset in their
> > registers.
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 32ea3c7e8b62..82e90f271974 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -1997,6 +1997,7 @@ void intel_ddi_disable_transcoder_func(const
> > struct intel_crtc_state *crtc_state
> >  
> >  	val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> >  	val &= ~TRANS_DDI_FUNC_ENABLE;
> > +	val &= ~TRANS_DDI_MODE_SELECT_MASK;
> 
> Feels a bit early since IIRC we still leave a bunch of other stuff
> enabled/selected here. In fact we don't seem to be clearing the DDI
> select
> anywhere at all? That one I would be more suspicious of than the
> mode.
> But maybe we should just clear both somewhere? I would suggest it
> should
> be when we clear the port select finally.

We are clearing DDI select, in our code it is named as
TGL_TRANS_DDI_PORT_MASK/TRANS_DDI_PORT_MASK.

For TGL in MST mode we clear DDI select in the block below for MST
slaves and then in intel_ddi_post_disable_dp() for MST master as
instructed by Display port sequences.

> 
> >  
> >  	if (INTEL_GEN(dev_priv) >= 12) {
> >  		if (!intel_dp_mst_is_master_trans(crtc_state))
> > -- 
> > 2.25.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

WARNING: multiple messages have this Message-ID (diff)
From: "Souza, Jose" <jose.souza@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>
Cc: "intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"dri-devel@lists.freedesktop.org"
	<dri-devel@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 4/4] drm/i915/display: Set TRANS_DDI_MODE_SELECT to default value when disabling TRANS_DDI
Date: Thu, 30 Jan 2020 20:07:07 +0000	[thread overview]
Message-ID: <2c578720445cfb0a036502b7dba94f1ebd2e8ca0.camel@intel.com> (raw)
In-Reply-To: <20200130172502.GH13686@intel.com>

On Thu, 2020-01-30 at 19:25 +0200, Ville Syrjälä wrote:
> On Thu, Jan 16, 2020 at 05:58:37PM -0800, José Roberto de Souza
> wrote:
> > TGL timeouts when disabling MST transcoder and fifo underruns over
> > MST
> > transcoders are fixed when setting TRANS_DDI_MODE_SELECT to 0(HDMI
> > mode) during the disable sequence.
> > 
> > Although BSpec disable sequence don't require this step it is a
> > harmless change and it is also done by Windows driver.
> > Anyhow HW team was notified about that but it can take some time to
> > documentation to be updated.
> > 
> > A case that always lead to those issues is:
> > - do a modeset enabling pipe A and pipe B in the same MST stream
> > leaving A as master
> > - disable pipe A, promote B as master doing a full modeset in A
> > - enable pipe A, changing the master transcoder back to A(doing a
> > full modeset in B)
> > - Pow: underruns and timeouts
> > 
> > The transcoders involved will only work again when complete
> > disabled
> > and their power wells turned off causing a reset in their
> > registers.
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 32ea3c7e8b62..82e90f271974 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -1997,6 +1997,7 @@ void intel_ddi_disable_transcoder_func(const
> > struct intel_crtc_state *crtc_state
> >  
> >  	val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> >  	val &= ~TRANS_DDI_FUNC_ENABLE;
> > +	val &= ~TRANS_DDI_MODE_SELECT_MASK;
> 
> Feels a bit early since IIRC we still leave a bunch of other stuff
> enabled/selected here. In fact we don't seem to be clearing the DDI
> select
> anywhere at all? That one I would be more suspicious of than the
> mode.
> But maybe we should just clear both somewhere? I would suggest it
> should
> be when we clear the port select finally.

We are clearing DDI select, in our code it is named as
TGL_TRANS_DDI_PORT_MASK/TRANS_DDI_PORT_MASK.

For TGL in MST mode we clear DDI select in the block below for MST
slaves and then in intel_ddi_post_disable_dp() for MST master as
instructed by Display port sequences.

> 
> >  
> >  	if (INTEL_GEN(dev_priv) >= 12) {
> >  		if (!intel_dp_mst_is_master_trans(crtc_state))
> > -- 
> > 2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2020-01-30 20:07 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-17  1:58 [PATCH 1/4] drm/mst: Don't do atomic checks over disabled managers José Roberto de Souza
2020-01-17  1:58 ` [Intel-gfx] " José Roberto de Souza
2020-01-17  1:58 ` [PATCH 2/4] drm/mst: Some style improvements in drm_dp_mst_topology_mgr_set_mst() José Roberto de Souza
2020-01-17  1:58   ` [Intel-gfx] " José Roberto de Souza
2020-01-17 20:22   ` Lyude Paul
2020-01-17 20:22     ` [Intel-gfx] " Lyude Paul
2020-01-17 21:20   ` Lyude Paul
2020-01-17 21:20     ` [Intel-gfx] " Lyude Paul
2020-01-17  1:58 ` [PATCH 3/4] drm/i915/display: Remove useless call intel_dp_mst_encoder_cleanup() José Roberto de Souza
2020-01-17  1:58   ` [Intel-gfx] " José Roberto de Souza
2020-01-30 17:16   ` Ville Syrjälä
2020-01-30 17:16     ` Ville Syrjälä
2020-01-31  0:14     ` Souza, Jose
2020-01-31  0:14       ` Souza, Jose
2020-02-11 10:53   ` Lisovskiy, Stanislav
2020-02-11 10:53     ` [Intel-gfx] " Lisovskiy, Stanislav
2020-01-17  1:58 ` [PATCH 4/4] drm/i915/display: Set TRANS_DDI_MODE_SELECT to default value when disabling TRANS_DDI José Roberto de Souza
2020-01-17  1:58   ` [Intel-gfx] " José Roberto de Souza
2020-01-30 17:25   ` Ville Syrjälä
2020-01-30 17:25     ` [Intel-gfx] " Ville Syrjälä
2020-01-30 20:07     ` Souza, Jose [this message]
2020-01-30 20:07       ` Souza, Jose
2020-01-31 11:20       ` Ville Syrjälä
2020-01-31 11:20         ` [Intel-gfx] " Ville Syrjälä
2020-05-13  8:28         ` Sharma, Swati2
2020-05-13  8:28           ` Sharma, Swati2
2020-05-13 12:09           ` Ville Syrjälä
2020-05-13 12:09             ` Ville Syrjälä
2020-05-13 12:14             ` Ville Syrjälä
2020-05-13 12:14               ` Ville Syrjälä
2020-02-11 11:23   ` Lisovskiy, Stanislav
2020-02-11 11:23     ` [Intel-gfx] " Lisovskiy, Stanislav
2020-01-17  3:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/mst: Don't do atomic checks over disabled managers Patchwork
2020-01-17  3:08 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork
2020-01-17 13:51 ` [PATCH 1/4] " Mikita Lipski
2020-01-17 13:51   ` [Intel-gfx] " Mikita Lipski
2020-01-17 20:21 ` Lyude Paul
2020-01-17 20:21   ` [Intel-gfx] " Lyude Paul
2020-01-17 21:24   ` Alex Deucher
2020-01-17 21:24     ` [Intel-gfx] " Alex Deucher
2020-01-20 10:42 ` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] " Patchwork

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