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From: Xiang W <wxjstz@126.com>
To: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>
Cc: Guo Ren <guoren@linux.alibaba.com>, Bin Meng <bmeng.cn@gmail.com>,
	 Samuel Holland <samuel@sholland.org>,
	Atish Patra <atish.patra@wdc.com>,
	Rob Herring <robh+dt@kernel.org>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Anup Patel <anup.patel@wdc.com>,
	 linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	 linux-riscv@lists.infradead.org, opensbi@lists.infradead.org
Subject: Re: [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT
Date: Sun, 17 Oct 2021 15:54:38 +0800	[thread overview]
Message-ID: <2cca0c29a56fd8be0dc9b25f68f5c308484d093b.camel@126.com> (raw)
In-Reply-To: <20211015100941.17621-1-heinrich.schuchardt@canonical.com>

在 2021-10-15星期五的 12:09 +0200，Heinrich Schuchardt写道：
> The CLINT in the T-HEAD 9xx processors do not support 64bit mmio
> access to
> the MTIMER device. The current schema does not allow to specify this.
> 
> OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to
> indicate the
> restriction. Samuael Holland suggested in
> lib: utils/timer: Use standard property to specify 32-bit I/O
> https://github.com/smaeul/opensbi/commit/b95e9cf7cf93b0af16fc89204378bc59ff30008e
> to use "reg-io-width = <4>;" as the reg-io-width property is
> generally used
> in the devicetree schema for such a condition.
> 
> A release candidate of the ACLINT specification is available at
> https://github.com/riscv/riscv-aclint/releases
> 
> Add reg-io-width as optional property to the SiFive Core Local
> Interruptor.
> 
> Signed-off-by: Heinrich Schuchardt
> <heinrich.schuchardt@canonical.com>
> ---
>  Documentation/devicetree/bindings/timer/sifive,clint.yaml | 7
> +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git
> a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> index a35952f48742..266012d887b5 100644
> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> @@ -41,6 +41,13 @@ properties:
>    reg:
>      maxItems: 1
>  
> +  reg-io-width:
> +    description: |
> +      Some CLINT implementations, e.g. on the T-HEAD 9xx, only
> support
> +      32bit access for MTIMER.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    const: 4
> +
>    interrupts-extended:
>      minItems: 1
>  
I think we can move has_64bit_mmio to fdt_match->data.This way we no
longer rely on 'clint, has-no-64bit-mmio' or 'reg-io-width'

Regards,
Xiang W



_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Xiang W <wxjstz@126.com>
To: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>
Cc: Guo Ren <guoren@linux.alibaba.com>, Bin Meng <bmeng.cn@gmail.com>,
	Samuel Holland <samuel@sholland.org>,
	Atish Patra <atish.patra@wdc.com>,
	Rob Herring <robh+dt@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Anup Patel <anup.patel@wdc.com>,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, opensbi@lists.infradead.org
Subject: Re: [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT
Date: Sun, 17 Oct 2021 15:54:38 +0800	[thread overview]
Message-ID: <2cca0c29a56fd8be0dc9b25f68f5c308484d093b.camel@126.com> (raw)
In-Reply-To: <20211015100941.17621-1-heinrich.schuchardt@canonical.com>

在 2021-10-15星期五的 12:09 +0200，Heinrich Schuchardt写道：
> The CLINT in the T-HEAD 9xx processors do not support 64bit mmio
> access to
> the MTIMER device. The current schema does not allow to specify this.
> 
> OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to
> indicate the
> restriction. Samuael Holland suggested in
> lib: utils/timer: Use standard property to specify 32-bit I/O
> https://github.com/smaeul/opensbi/commit/b95e9cf7cf93b0af16fc89204378bc59ff30008e
> to use "reg-io-width = <4>;" as the reg-io-width property is
> generally used
> in the devicetree schema for such a condition.
> 
> A release candidate of the ACLINT specification is available at
> https://github.com/riscv/riscv-aclint/releases
> 
> Add reg-io-width as optional property to the SiFive Core Local
> Interruptor.
> 
> Signed-off-by: Heinrich Schuchardt
> <heinrich.schuchardt@canonical.com>
> ---
>  Documentation/devicetree/bindings/timer/sifive,clint.yaml | 7
> +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git
> a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> index a35952f48742..266012d887b5 100644
> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> @@ -41,6 +41,13 @@ properties:
>    reg:
>      maxItems: 1
>  
> +  reg-io-width:
> +    description: |
> +      Some CLINT implementations, e.g. on the T-HEAD 9xx, only
> support
> +      32bit access for MTIMER.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    const: 4
> +
>    interrupts-extended:
>      minItems: 1
>  
I think we can move has_64bit_mmio to fdt_match->data.This way we no
longer rely on 'clint, has-no-64bit-mmio' or 'reg-io-width'

Regards,
Xiang W



  parent reply	other threads:[~2021-10-17  7:55 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-15 10:09 [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT Heinrich Schuchardt
2021-10-15 10:09 ` Heinrich Schuchardt
2021-10-15 10:14 ` Bin Meng
2021-10-15 10:14   ` Bin Meng
2021-10-15 11:54   ` Heinrich Schuchardt
2021-10-15 11:54     ` Heinrich Schuchardt
2021-10-15 12:15     ` Jessica Clarke
2021-10-15 12:15       ` Jessica Clarke
2021-10-15 12:42       ` Heinrich Schuchardt
2021-10-15 12:42         ` Heinrich Schuchardt
2021-10-15 13:46       ` Bin Meng
2021-10-15 13:46         ` Bin Meng
2021-10-17  7:54 ` Xiang W [this message]
2021-10-17  7:54   ` Xiang W
2021-10-19  6:10 ` Guo Ren
2021-10-19  6:10   ` Guo Ren

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