From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 383C4C433F5 for ; Wed, 2 Mar 2022 23:47:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229750AbiCBXse (ORCPT ); Wed, 2 Mar 2022 18:48:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229709AbiCBXsW (ORCPT ); Wed, 2 Mar 2022 18:48:22 -0500 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A60A010CF0C; Wed, 2 Mar 2022 15:47:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1646264846; x=1677800846; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=KwJmzLMc/dS9fM65kAwlsOu7mLCuAExYDF3cN1aB5fM=; b=uFYyYCLMS+HWnTe1OOp5JlMBkFIXEMPvzRM/igfYi7LxziGCduhhAHq8 5Bp2BdFlZtx3njofac6OkPZ0CEm6dzrx/lPLc6Z1jfNj+hTGtxMR5MpTP gEtkKHUDbjvmIPR75O8WqScn8pSaCHrzJCwkNXCVxDTRLXeLg9KX8VJFm w=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-02.qualcomm.com with ESMTP; 02 Mar 2022 15:47:25 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg02-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2022 15:47:25 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Wed, 2 Mar 2022 15:47:24 -0800 Received: from [10.110.107.103] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Wed, 2 Mar 2022 15:47:24 -0800 Message-ID: <2cd02c8b-9c1b-e87b-a90c-6e591b3a21a4@quicinc.com> Date: Wed, 2 Mar 2022 15:47:23 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.5.1 Subject: Re: [PATCH v2 1/6] arm64: dts: qcom: msm8996: Drop flags for mdss irqs Content-Language: en-US To: Dmitry Baryshkov , Andy Gross , Bjorn Andersson , Rob Clark , Sean Paul , Rob Herring CC: Stephen Boyd , , , References: <20220302225411.2456001-1-dmitry.baryshkov@linaro.org> From: Abhinav Kumar In-Reply-To: <20220302225411.2456001-1-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 3/2/2022 2:54 PM, Dmitry Baryshkov wrote: > The number of interrupt cells for the mdss interrupt controller is 1, > meaning there should only be one cell for the interrupt number, not two. > Drop the second cell containing (unused) irq flags. > > Reviewed-by: Stephen Boyd > Fixes: 12d540375736 ("arm64: dts: qcom: msm8996: Add DSI0 nodes") > Fixes: 3a4547c1fc2f ("arm64: qcom: msm8996.dtsi: Add Display nodes") > Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar > --- > arch/arm64/boot/dts/qcom/msm8996.dtsi | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi > index f0f81c23c16f..0597d865a4a6 100644 > --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi > @@ -788,7 +788,7 @@ mdp: mdp@901000 { > reg-names = "mdp_phys"; > > interrupt-parent = <&mdss>; > - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; > + interrupts = <0>; > > clocks = <&mmcc MDSS_AHB_CLK>, > <&mmcc MDSS_AXI_CLK>, > @@ -834,7 +834,7 @@ dsi0: dsi@994000 { > reg-names = "dsi_ctrl"; > > interrupt-parent = <&mdss>; > - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; > + interrupts = <4>; > > clocks = <&mmcc MDSS_MDP_CLK>, > <&mmcc MDSS_BYTE0_CLK>, > @@ -904,7 +904,7 @@ hdmi: hdmi-tx@9a0000 { > "hdcp_physical"; > > interrupt-parent = <&mdss>; > - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; > + interrupts = <8>; > > clocks = <&mmcc MDSS_MDP_CLK>, > <&mmcc MDSS_AHB_CLK>,