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[83.57.170.138]) by smtp.gmail.com with ESMTPSA id w16sm1303673wrg.95.2020.07.08.10.56.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Jul 2020 10:56:30 -0700 (PDT) Subject: Re: [PATCH v4 05/12] hw/arm: Add NPCM730 and NPCM750 SoC models From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= To: Havard Skinnemoen , peter.maydell@linaro.org References: <20200707184730.3047754-1-hskinnemoen@google.com> <20200707184730.3047754-6-hskinnemoen@google.com> <4b7130f2-032c-3067-b2b6-876a2b17b707@amsat.org> Autocrypt: addr=f4bug@amsat.org; keydata= mQINBDU8rLoBEADb5b5dyglKgWF9uDbIjFXU4gDtcwiga9wJ/wX6xdhBqU8tlQ4BroH7AeRl u4zXP0QnBDAG7EetxlQzcfYbPmxFISWjckDBFvDbFsojrZmwF2/LkFSzlvKiN5KLghzzJhLO HhjGlF8deEZz/d/G8qzO9mIw8GIBS8uuWh6SIcG/qq7+y+2+aifaj92EdwU79apZepT/U3vN YrfcAuo1Ycy7/u0hJ7rlaFUn2Fu5KIgV2O++hHYtCCQfdPBg/+ujTL+U+sCDawCyq+9M5+LJ ojCzP9rViLZDd/gS6jX8T48hhidtbtsFRj/e9QpdZgDZfowRMVsRx+TB9yzjFdMO0YaYybXp dg/wCUepX5xmDBrle6cZ8VEe00+UQCAU1TY5Hs7QFfBbjgR3k9pgJzVXNUKcJ9DYQP0OBH9P ZbZvM0Ut2Bk6bLBO5iCVDOco0alrPkX7iJul2QWBy3Iy9j02GnA5jZ1Xtjr9kpCqQT+sRXso Vpm5TPGWaWljIeLWy/qL8drX1eyJzwTB3A36Ck4r3YmjMjfmvltSZB1uAdo1elHTlFEULpU/ HiwvvqXQ9koB15U154VCuguvx/Qnboz8GFb9Uw8VyawzVxYVNME7xw7CQF8FYxzj6eI7rBf2 Dj/II6wxWPgDEy3oUzuNOxTB7sT3b/Ym76yOJzWX5BylXQIJ5wARAQABtDFQaGlsaXBwZSBN YXRoaWV1LURhdWTDqSAoRjRCVUcpIDxmNGJ1Z0BhbXNhdC5vcmc+iQJVBBMBCAA/AhsPBgsJ CAcDAgYVCAIJCgsEFgIDAQIeAQIXgBYhBPqr514SkXIh3P1rsuPjLCzercDeBQJd660aBQks klzgAAoJEOPjLCzercDe2iMP+gMG2dUf+qHz2uG8nTBGMjgK0aEJrKVPodFA+iedQ5Kp3BMo jrTg3/DG1HMYdcvQu/NFLYwamUfUasyor1k+3dB23hY09O4xOsYJBWdilkBGsJTKErUmkUO2 3J/kawosvYtJJSHUpw3N6mwz/iWnjkT8BPp7fFXSujV63aZWZINueTbK7Y8skFHI0zpype9s loU8xc4JBrieGccy3n4E/kogGrTG5jcMTNHZ106DsQkhFnjhWETp6g9xOKrzZQbETeRBOe4P sRsY9YSG2Sj+ZqmZePvO8LyzGRjYU7T6Z80S1xV0lH6KTMvq7vvz5rd92f3pL4YrXq+e//HZ JsiLen8LH/FRhTsWRgBtNYkOsd5F9NvfJtSM0qbX32cSXMAStDVnS4U+H2vCVCWnfNug2TdY 7v4NtdpaCi4CBBa3ZtqYVOU05IoLnlx0miKTBMqmI05kpgX98pi2QUPJBYi/+yNu3fjjcuS9 K5WmpNFTNi6yiBbNjJA5E2qUKbIT/RwQFQvhrxBUcRCuK4x/5uOZrysjFvhtR8YGm08h+8vS n0JCnJD5aBhiVdkohEFAz7e5YNrAg6kOA5IVRHB44lTBOatLqz7ntwdGD0rteKuHaUuXpTYy CRqCVAKqFJtxhvJvaX0vLS1Z2dwtDwhjfIdgPiKEGOgCNGH7R8l+aaM4OPOd Message-ID: <2d1e272b-6575-30df-22ff-5d720973951d@amsat.org> Date: Wed, 8 Jul 2020 19:56:30 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <4b7130f2-032c-3067-b2b6-876a2b17b707@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kfting@nuvoton.com, qemu-arm@nongnu.org, Joel Stanley , Avi.Fishman@nuvoton.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/8/20 7:31 PM, Philippe Mathieu-Daudé wrote: > Hi Havard, > > On 7/7/20 8:47 PM, Havard Skinnemoen wrote: >> The Nuvoton NPCM7xx SoC family are used to implement Baseboard >> Management Controllers in servers. While the family includes four SoCs, >> this patch implements limited support for two of them: NPCM730 (targeted >> for Data Center applications) and NPCM750 (targeted for Enterprise >> applications). >> >> This patch includes little more than the bare minimum needed to boot a >> Linux kernel built with NPCM7xx support in direct-kernel mode: >> >> - Two Cortex-A9 CPU cores with built-in periperhals. >> - Global Configuration Registers. >> - Clock Management. >> - 3 Timer Modules with 5 timers each. >> - 4 serial ports. >> >> The chips themselves have a lot more features, some of which will be >> added to the model at a later stage. [...] >> +static void npcm7xx_realize(DeviceState *dev, Error **errp) >> +{ >> + NPCM7xxState *s = NPCM7XX(dev); >> + NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s); >> + Error *err = NULL; >> + int i; >> + >> + /* I/O space -- unimplemented unless overridden below. */ >> + create_unimplemented_device("npcm7xx.io", NPCM7XX_MMIO_BA, NPCM7XX_MMIO_SZ); > > I still insist this is not the best, but as "The data sheet for these > SoCs is not generally available" there is not much I can suggest to > improve. >From your other comment I found: https://github.com/Nuvoton-Israel/bootblock/blob/master/SWC_HAL/Chips/npcm750/npcm750.h In particular: #define AHB1_BASE_ADDR 0xF0000000 /* AHB1 allocation (Including APB allocations) */ #define AHB18_BASE_ADDR 0x80000000 /* AHB18 allocation */ #define AHB3_BASE_ADDR 0xA0000000 /* AHB3 allocation */ #define XBUSR_BASE_ADDR 0xC0002000 /* XBUS registers */ #define AHB14_BASE_ADDR 0xE0000000 /* AHB14 Allocation */ #define APB14_BASE_ADDR 0xE0000000 /* APB14 Allocation */ #define VDMX_BASE_ADDR 0xE0800000 /* VDMX */ XBUS doesn't seem important. If SPI flashes aren't connected, returning bus transaction sounds correct: #define SPI0CS0_BASE_ADDR 0x80000000 /* SPI0 direct access CS0 */ #define SPI0CS1_BASE_ADDR 0x88000000 /* SPI0 direct access CS1 */ #define SPI0CS2_BASE_ADDR 0x90000000 /* SPI0 direct access CS2 */ #define SPI0CS3_BASE_ADDR 0x98000000 /* SPI0 direct access CS3 */ #define SPI3CS0_BASE_ADDR 0xA0000000 /* SPI3 direct access CS0 */ #define SPI3CS1_BASE_ADDR 0xA8000000 /* SPI3 direct access CS1 */ #define SPI3CS2_BASE_ADDR 0xB0000000 /* SPI3 direct access CS2 */ #define SPI3CS3_BASE_ADDR 0xB8000000 /* SPI3 direct access CS3 */ So I'd prefer you use: create_unimplemented_device("npcm7xx.AHB1", 0xf0000000, 256 * MiB); Maybe for the PCI root complex: create_unimplemented_device("npcm7xx.AHB14", 0xe0000000, 256 * MiB); What do you think? Regards, Phil.