From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF10CC433E0 for ; Tue, 5 Jan 2021 08:24:31 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id 3E9DF2256F for ; Tue, 5 Jan 2021 08:24:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3E9DF2256F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 63EDF4B2E3; Tue, 5 Jan 2021 03:24:30 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id mkIsxPTS97w0; Tue, 5 Jan 2021 03:24:29 -0500 (EST) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 2D4844B2CF; Tue, 5 Jan 2021 03:24:29 -0500 (EST) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 28B0C4B2CF for ; Tue, 5 Jan 2021 03:24:27 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MBxtr0S1T8b0 for ; Tue, 5 Jan 2021 03:24:25 -0500 (EST) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 118004B2B8 for ; Tue, 5 Jan 2021 03:24:25 -0500 (EST) Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id B3C5D22482; Tue, 5 Jan 2021 08:24:23 +0000 (UTC) Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.94) (envelope-from ) id 1kwhdd-005O61-BX; Tue, 05 Jan 2021 08:24:21 +0000 MIME-Version: 1.0 Date: Tue, 05 Jan 2021 08:24:21 +0000 From: Marc Zyngier To: Jing Zhang Subject: Re: [PATCH 04/17] arm64: Provide an 'upgrade to VHE' stub hypercall In-Reply-To: References: <20201228104958.1848833-1-maz@kernel.org> <20201228104958.1848833-5-maz@kernel.org> User-Agent: Roundcube Webmail/1.4.9 Message-ID: <2dad221aeef58d380d73c9768e430cd3@kernel.org> X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: jingzhangos@google.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kernel-team@android.com, catalin.marinas@arm.com, will@kernel.org, ardb@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: kernel-team@android.com, Catalin Marinas , Ard Biesheuvel , Will Deacon , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On 2021-01-04 23:39, Jing Zhang wrote: > On Mon, Dec 28, 2020 at 4:50 AM Marc Zyngier wrote: >> >> As we are about to change the way a VHE system boots, let's >> provide the core helper, in the form of a stub hypercall that >> enables VHE and replicates the full EL1 context at EL2, thanks >> to EL1 and VHE-EL2 being extremely similar. >> >> On exception return, the kernel carries on at EL2. Fancy! >> >> Nothing calls this new hypercall yet, so no functional change. >> >> Signed-off-by: Marc Zyngier >> --- >> arch/arm64/include/asm/virt.h | 7 +++- >> arch/arm64/kernel/hyp-stub.S | 70 >> ++++++++++++++++++++++++++++++++++- >> 2 files changed, 74 insertions(+), 3 deletions(-) >> >> diff --git a/arch/arm64/include/asm/virt.h >> b/arch/arm64/include/asm/virt.h >> index ee6a48df89d9..7379f35ae2c6 100644 >> --- a/arch/arm64/include/asm/virt.h >> +++ b/arch/arm64/include/asm/virt.h >> @@ -35,8 +35,13 @@ >> */ >> #define HVC_RESET_VECTORS 2 >> >> +/* >> + * HVC_VHE_RESTART - Upgrade the CPU from EL1 to EL2, if possible >> + */ >> +#define HVC_VHE_RESTART 3 >> + >> /* Max number of HYP stub hypercalls */ >> -#define HVC_STUB_HCALL_NR 3 >> +#define HVC_STUB_HCALL_NR 4 >> >> /* Error returned when an invalid stub number is passed into x0 */ >> #define HVC_STUB_ERR 0xbadca11 >> diff --git a/arch/arm64/kernel/hyp-stub.S >> b/arch/arm64/kernel/hyp-stub.S >> index 160f5881a0b7..6ffdc1f7778b 100644 >> --- a/arch/arm64/kernel/hyp-stub.S >> +++ b/arch/arm64/kernel/hyp-stub.S >> @@ -8,9 +8,9 @@ >> >> #include >> #include >> -#include >> >> #include >> +#include >> #include >> #include >> #include >> @@ -47,10 +47,16 @@ SYM_CODE_END(__hyp_stub_vectors) >> >> SYM_CODE_START_LOCAL(el1_sync) >> cmp x0, #HVC_SET_VECTORS >> - b.ne 2f >> + b.ne 1f >> msr vbar_el2, x1 >> b 9f >> >> +1: cmp x0, #HVC_VHE_RESTART >> + b.ne 2f >> + mov x0, #HVC_SOFT_RESTART >> + adr x1, mutate_to_vhe >> + // fall through... >> + >> 2: cmp x0, #HVC_SOFT_RESTART >> b.ne 3f >> mov x0, x2 >> @@ -70,6 +76,66 @@ SYM_CODE_START_LOCAL(el1_sync) >> eret >> SYM_CODE_END(el1_sync) >> >> +// nVHE? No way! Give me the real thing! >> +SYM_CODE_START_LOCAL(mutate_to_vhe) >> + // Sanity check: MMU *must* be off >> + mrs x0, sctlr_el2 >> + tbnz x0, #0, 1f >> + >> + // Needs to be VHE capable, obviously >> + mrs x0, id_aa64mmfr1_el1 >> + ubfx x0, x0, #ID_AA64MMFR1_VHE_SHIFT, #4 >> + cbz x0, 1f >> + >> + // Engage the VHE magic! >> + mov_q x0, HCR_HOST_VHE_FLAGS >> + msr hcr_el2, x0 >> + isb >> + >> + // Doesn't do much on VHE, but still, worth a shot >> + init_el2_state vhe >> + >> + // Use the EL1 allocated stack, per-cpu offset >> + mrs x0, sp_el1 >> + mov sp, x0 >> + mrs x0, tpidr_el1 >> + msr tpidr_el2, x0 >> + >> + // FP configuration, vectors >> + mrs_s x0, SYS_CPACR_EL12 >> + msr cpacr_el1, x0 >> + mrs_s x0, SYS_VBAR_EL12 >> + msr vbar_el1, x0 >> + >> + // Transfert the MM state from EL1 to EL2 > > Transfert, typo? Yes, thanks. If you are going to review this, may I suggest you look at v2 [1] instead? The initial version had so many issues that I'm trying to pretend it never happened. Cheers, M. [1] https://lore.kernel.org/r/20210104135011.2063104-1-maz@kernel.org -- Jazz is not dead. It just smells funny... _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C72AFC433DB for ; Tue, 5 Jan 2021 08:26:20 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 379A022257 for ; Tue, 5 Jan 2021 08:26:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 379A022257 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:Message-ID:References:In-Reply-To:Subject:To:From: Date:MIME-Version:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=bEZmOMzMh2FgreCbRccY6UIIyja1new0tBaw24tZlOU=; b=Lmfzmabb8MZYSD60mWttGEsTL xuxCCU7t3FocQfXoQpZ16dC8PCYVwbTLnfrySE81uzLWIcO0aW/MVmmHkN4rWMWk1X5tfaH+IJcU9 GlC74L0vnxtdL/kKa5iAhqhY3HvkVfP/zxUJ4V1s4LINlq58rHlIqT5zZzG9uSwEoVcudYjvDQumo 3JaahhY23i5l6PmINWIK9Efo5/VfWlPMrO2cRZcmcKhEtQ63DWXlRnGsFgPXkjYBbaS4n8jVEcngu yq7xFZTjQPSv5dYcox/b1XauxrgjXC6I81M5SxClaN12e9soVRNJa8Hm2mCb/QkyW2rQAjumNfPUh kyYZ4zFcg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kwhdj-00082m-Sk; Tue, 05 Jan 2021 08:24:27 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kwhdh-00082D-1r for linux-arm-kernel@lists.infradead.org; Tue, 05 Jan 2021 08:24:26 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id B3C5D22482; Tue, 5 Jan 2021 08:24:23 +0000 (UTC) Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.94) (envelope-from ) id 1kwhdd-005O61-BX; Tue, 05 Jan 2021 08:24:21 +0000 MIME-Version: 1.0 Date: Tue, 05 Jan 2021 08:24:21 +0000 From: Marc Zyngier To: Jing Zhang Subject: Re: [PATCH 04/17] arm64: Provide an 'upgrade to VHE' stub hypercall In-Reply-To: References: <20201228104958.1848833-1-maz@kernel.org> <20201228104958.1848833-5-maz@kernel.org> User-Agent: Roundcube Webmail/1.4.9 Message-ID: <2dad221aeef58d380d73c9768e430cd3@kernel.org> X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: jingzhangos@google.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kernel-team@android.com, catalin.marinas@arm.com, will@kernel.org, ardb@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210105_032425_275366_47059809 X-CRM114-Status: GOOD ( 16.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kernel-team@android.com, Catalin Marinas , Ard Biesheuvel , Will Deacon , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2021-01-04 23:39, Jing Zhang wrote: > On Mon, Dec 28, 2020 at 4:50 AM Marc Zyngier wrote: >> >> As we are about to change the way a VHE system boots, let's >> provide the core helper, in the form of a stub hypercall that >> enables VHE and replicates the full EL1 context at EL2, thanks >> to EL1 and VHE-EL2 being extremely similar. >> >> On exception return, the kernel carries on at EL2. Fancy! >> >> Nothing calls this new hypercall yet, so no functional change. >> >> Signed-off-by: Marc Zyngier >> --- >> arch/arm64/include/asm/virt.h | 7 +++- >> arch/arm64/kernel/hyp-stub.S | 70 >> ++++++++++++++++++++++++++++++++++- >> 2 files changed, 74 insertions(+), 3 deletions(-) >> >> diff --git a/arch/arm64/include/asm/virt.h >> b/arch/arm64/include/asm/virt.h >> index ee6a48df89d9..7379f35ae2c6 100644 >> --- a/arch/arm64/include/asm/virt.h >> +++ b/arch/arm64/include/asm/virt.h >> @@ -35,8 +35,13 @@ >> */ >> #define HVC_RESET_VECTORS 2 >> >> +/* >> + * HVC_VHE_RESTART - Upgrade the CPU from EL1 to EL2, if possible >> + */ >> +#define HVC_VHE_RESTART 3 >> + >> /* Max number of HYP stub hypercalls */ >> -#define HVC_STUB_HCALL_NR 3 >> +#define HVC_STUB_HCALL_NR 4 >> >> /* Error returned when an invalid stub number is passed into x0 */ >> #define HVC_STUB_ERR 0xbadca11 >> diff --git a/arch/arm64/kernel/hyp-stub.S >> b/arch/arm64/kernel/hyp-stub.S >> index 160f5881a0b7..6ffdc1f7778b 100644 >> --- a/arch/arm64/kernel/hyp-stub.S >> +++ b/arch/arm64/kernel/hyp-stub.S >> @@ -8,9 +8,9 @@ >> >> #include >> #include >> -#include >> >> #include >> +#include >> #include >> #include >> #include >> @@ -47,10 +47,16 @@ SYM_CODE_END(__hyp_stub_vectors) >> >> SYM_CODE_START_LOCAL(el1_sync) >> cmp x0, #HVC_SET_VECTORS >> - b.ne 2f >> + b.ne 1f >> msr vbar_el2, x1 >> b 9f >> >> +1: cmp x0, #HVC_VHE_RESTART >> + b.ne 2f >> + mov x0, #HVC_SOFT_RESTART >> + adr x1, mutate_to_vhe >> + // fall through... >> + >> 2: cmp x0, #HVC_SOFT_RESTART >> b.ne 3f >> mov x0, x2 >> @@ -70,6 +76,66 @@ SYM_CODE_START_LOCAL(el1_sync) >> eret >> SYM_CODE_END(el1_sync) >> >> +// nVHE? No way! Give me the real thing! >> +SYM_CODE_START_LOCAL(mutate_to_vhe) >> + // Sanity check: MMU *must* be off >> + mrs x0, sctlr_el2 >> + tbnz x0, #0, 1f >> + >> + // Needs to be VHE capable, obviously >> + mrs x0, id_aa64mmfr1_el1 >> + ubfx x0, x0, #ID_AA64MMFR1_VHE_SHIFT, #4 >> + cbz x0, 1f >> + >> + // Engage the VHE magic! >> + mov_q x0, HCR_HOST_VHE_FLAGS >> + msr hcr_el2, x0 >> + isb >> + >> + // Doesn't do much on VHE, but still, worth a shot >> + init_el2_state vhe >> + >> + // Use the EL1 allocated stack, per-cpu offset >> + mrs x0, sp_el1 >> + mov sp, x0 >> + mrs x0, tpidr_el1 >> + msr tpidr_el2, x0 >> + >> + // FP configuration, vectors >> + mrs_s x0, SYS_CPACR_EL12 >> + msr cpacr_el1, x0 >> + mrs_s x0, SYS_VBAR_EL12 >> + msr vbar_el1, x0 >> + >> + // Transfert the MM state from EL1 to EL2 > > Transfert, typo? Yes, thanks. If you are going to review this, may I suggest you look at v2 [1] instead? The initial version had so many issues that I'm trying to pretend it never happened. Cheers, M. [1] https://lore.kernel.org/r/20210104135011.2063104-1-maz@kernel.org -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel