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From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH 11/16] target/arm: Add minimal RAS registers
Date: Mon, 11 Apr 2022 14:25:52 -0700	[thread overview]
Message-ID: <2dc12f93-9e47-f4c9-f4ed-0cc3ae8f5b51@linaro.org> (raw)
In-Reply-To: <CAFEAcA_ASQ7Dwm5YMsXvPa6SS721HNuUkD7JPSCpuNOyDikJtw@mail.gmail.com>

On 4/11/22 08:49, Peter Maydell wrote:
>> +    { .name = "ERRSELR_EL1", .state = ARM_CP_STATE_BOTH,
>> +      .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 1,
>> +      .access = PL1_RW, .accessfn = access_terr,
>> +      .fieldoffset = offsetof(CPUARMState, cp15.errselr_el1) },
> 
> By my reading of the spec we could make ERRSELR_EL1 RAZ/WI, because
> writing an over-large number has a number of behaviours including
> that the value the guest can read back is UNKNOWN. That would save
> having the CPU state struct field.

Good point, I should have read the fine print myself:

If ERRIDR_EL1 indicates that zero error records are implemented, then it is IMPLEMENTATION 
DEFINED whether ERRSELR_EL1 is UNDEFINED or RES 0.

so perhaps it's better to leave it UNDEFINED.


r~


  reply	other threads:[~2022-04-11 21:26 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-09  0:07 [PATCH 00/16] target/arm: Implement features Debugv8p4, RAS, IESB Richard Henderson
2022-04-09  0:07 ` [PATCH 01/16] target/arm: Add isar predicates for FEAT_Debugv8p2 Richard Henderson
2022-04-11 12:33   ` Peter Maydell
2022-04-09  0:07 ` [PATCH 02/16] target/arm: Adjust definition of CONTEXTIDR_EL2 Richard Henderson
2022-04-11 12:34   ` Peter Maydell
2022-04-09  0:07 ` [PATCH 03/16] target/arm: Update qemu-system-arm -cpu max to cortex-a57 Richard Henderson
2022-04-11 15:37   ` Peter Maydell
2022-04-11 16:28     ` Richard Henderson
2022-04-09  0:07 ` [PATCH 04/16] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max Richard Henderson
2022-04-11 12:36   ` Peter Maydell
2022-04-09  0:07 ` [PATCH 05/16] target/arm: Split out arm32_max_features Richard Henderson
2022-04-11 12:52   ` Peter Maydell
2022-04-09  0:07 ` [PATCH 06/16] target/arm: Annotate arm_max_initfn with FEAT identifiers Richard Henderson
2022-04-11 12:55   ` Peter Maydell
2022-04-09  0:07 ` [PATCH 07/16] target/arm: Use field names for manipulating EL2 and EL3 modes Richard Henderson
2022-04-11 12:56   ` Peter Maydell
2022-04-09  0:07 ` [PATCH 08/16] target/arm: Enable FEAT_Debugv8p2 for -cpu max Richard Henderson
2022-04-11 13:09   ` Peter Maydell
2022-04-11 17:48     ` Peter Maydell
2022-04-09  0:07 ` [PATCH 09/16] target/arm: Enable FEAT_Debugv8p4 " Richard Henderson
2022-04-11 13:27   ` Peter Maydell
2022-04-09  0:07 ` [PATCH 10/16] target/arm: Add isar_feature_{aa64,any}_ras Richard Henderson
2022-04-11 13:29   ` Peter Maydell
2022-04-09  0:07 ` [PATCH 11/16] target/arm: Add minimal RAS registers Richard Henderson
2022-04-11 15:49   ` Peter Maydell
2022-04-11 21:25     ` Richard Henderson [this message]
2022-04-09  0:07 ` [PATCH 12/16] target/arm: Enable SCR and HCR bits for RAS Richard Henderson
2022-04-11 15:50   ` Peter Maydell
2022-04-09  0:07 ` [PATCH 13/16] target/arm: Implement virtual SError exceptions Richard Henderson
2022-04-11 16:00   ` Peter Maydell
2022-04-11 16:32   ` Peter Maydell
2022-04-11 21:42     ` Richard Henderson
2022-04-09  0:07 ` [PATCH 14/16] target/arm: Implement ESB instruction Richard Henderson
2022-04-11 16:18   ` Peter Maydell
2022-04-11 22:14     ` Richard Henderson
2022-04-12  9:56       ` Peter Maydell
2022-04-12 14:31         ` Richard Henderson
2022-04-09  0:07 ` [PATCH 15/16] target/arm: Enable FEAT_RAS for -cpu max Richard Henderson
2022-04-11 16:32   ` Peter Maydell
2022-04-09  0:07 ` [PATCH 16/16] target/arm: Enable FEAT_IESB " Richard Henderson
2022-04-11 16:33   ` Peter Maydell

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