From mboxrd@z Thu Jan  1 00:00:00 1970
From: Kever Yang <kever.yang@rock-chips.com>
Date: Fri, 13 Nov 2020 18:12:44 +0800
Subject: [PATCH v2 1/2] rockchip: rk3399: Init clocks in U-Boot proper if
 SPL was not run
In-Reply-To: <20201027211511.14544-1-alpernebiyasak@gmail.com>
References: <20201027211511.14544-1-alpernebiyasak@gmail.com>
Message-ID: <2dcebbfd-09fc-1243-f35c-76fdbae5dd2a@rock-chips.com>
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On 2020/10/28 ??5:15, Alper Nebi Yasak wrote:
> It's possible to chainload U-Boot proper from the vendor firmware in
> rk3399 chromebooks, but the way the vendor firmware sets up clocks is
> somehow different than what U-Boot expects. This causes the display to
> stay devoid of content even though vidconsole claims to work (with
> patches in process of being upstreamed).
>
> This is meant to be a rk3399 version of commit d3cb46aa8c41 ("rockchip:
> Init clocks again when chain-loading") which can detect the discrepancy,
> but this patch instead checks whether SPL (and therefore the clock init)
> was run via the handoff functionality and runs the init if it was not.
>
> Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>
> Changes in v2:
> - Check for SPL handoff instead of always re-initializing
>
> v1: https://patchwork.ozlabs.org/project/uboot/patch/20201022203740.24528-1-alpernebiyasak at gmail.com/
>
>   drivers/clk/rockchip/clk_rk3399.c | 22 ++++++++++++++++------
>   1 file changed, 16 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index 1ea41f3c5b2e..64e0e2348db5 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -23,6 +23,8 @@
>   #include <linux/bitops.h>
>   #include <linux/delay.h>
>   
> +DECLARE_GLOBAL_DATA_PTR;
> +
>   #if CONFIG_IS_ENABLED(OF_PLATDATA)
>   struct rk3399_clk_plat {
>   	struct dtd_rockchip_rk3399_cru dtd;
> @@ -50,10 +52,9 @@ struct pll_div {
>   	.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
>   	.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
>   
> -#if defined(CONFIG_SPL_BUILD)
>   static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
>   static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
> -#else
> +#if !defined(CONFIG_SPL_BUILD)
>   static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
>   #endif
>   
> @@ -1274,7 +1275,6 @@ static struct clk_ops rk3399_clk_ops = {
>   	.disable = rk3399_clk_disable,
>   };
>   
> -#ifdef CONFIG_SPL_BUILD
>   static void rkclk_init(struct rockchip_cru *cru)
>   {
>   	u32 aclk_div;
> @@ -1352,20 +1352,30 @@ static void rkclk_init(struct rockchip_cru *cru)
>   		     hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
>   		     HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
>   }
> -#endif
>   
>   static int rk3399_clk_probe(struct udevice *dev)
>   {
> -#ifdef CONFIG_SPL_BUILD
>   	struct rk3399_clk_priv *priv = dev_get_priv(dev);
> +	bool init_clocks = false;
>   
>   #if CONFIG_IS_ENABLED(OF_PLATDATA)
>   	struct rk3399_clk_plat *plat = dev_get_platdata(dev);
>   
>   	priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
>   #endif
> -	rkclk_init(priv->cru);
> +
> +#if defined(CONFIG_SPL_BUILD)
> +	init_clocks = true;
> +#elif CONFIG_IS_ENABLED(HANDOFF)
> +	if (!(gd->flags & GD_FLG_RELOC)) {
> +		if (!(gd->spl_handoff))
> +			init_clocks = true;
> +	}
>   #endif
> +
> +	if (init_clocks)
> +		rkclk_init(priv->cru);
> +
>   	return 0;
>   }
>