From: Richard Henderson <richard.henderson@linaro.org>
To: Philipp Tomsich <philipp.tomsich@vrull.eu>, qemu-devel@nongnu.org
Cc: Kito Cheng <kito.cheng@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PATCH v3 01/15] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
Date: Mon, 23 Aug 2021 09:58:36 -0700 [thread overview]
Message-ID: <2de18301-63fb-fd98-4239-adad0d6589c0@linaro.org> (raw)
In-Reply-To: <20210823164038.2195113-2-philipp.tomsich@vrull.eu>
On 8/23/21 9:40 AM, Philipp Tomsich wrote:
> The bitmanipulation ISA extensions will be ratified as individual
> small extension packages instead of a large B-extension. The first
> new instructions through the door (these have completed public review)
> are Zb[abcs].
>
> This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for
> these in target/riscv/cpu.[ch].
>
> Signed-off-by: Philipp Tomsich<philipp.tomsich@vrull.eu>
> ---
>
> Changes in v3:
> - Split off removal of 'x-b' property and 'ext_b' field into a separate
> patch to ensure bisectability.
>
> target/riscv/cpu.c | 4 ++++
> target/riscv/cpu.h | 4 ++++
> 2 files changed, 8 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2021-08-23 17:02 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-23 16:40 [PATCH v3 00/15] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
2021-08-23 16:40 ` [PATCH v3 01/15] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties Philipp Tomsich
2021-08-23 16:58 ` Richard Henderson [this message]
2021-08-23 16:40 ` [PATCH v3 02/15] target/riscv: Reassign instructions to the Zba-extension Philipp Tomsich
2021-08-23 16:59 ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 03/15] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits Philipp Tomsich
2021-08-23 17:02 ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 04/15] target/riscv: Remove the W-form instructions from Zbs Philipp Tomsich
2021-08-23 17:04 ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 05/15] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) Philipp Tomsich
2021-08-23 17:04 ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 06/15] target/riscv: Reassign instructions to the Zbs-extension Philipp Tomsich
2021-08-23 17:07 ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 07/15] target/riscv: Add instructions of the Zbc-extension Philipp Tomsich
2021-08-23 17:17 ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 08/15] target/riscv: Reassign instructions to the Zbb-extension Philipp Tomsich
2021-08-23 17:20 ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 09/15] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci Philipp Tomsich
2021-08-23 17:24 ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 10/15] target/riscv: Add a REQUIRE_32BIT macro Philipp Tomsich
2021-08-23 17:25 ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 11/15] target/riscv: Add rev8 instruction, removing grev/grevi Philipp Tomsich
2021-08-23 17:29 ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 12/15] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh Philipp Tomsich
2021-08-23 17:31 ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 13/15] target/riscv: Remove RVB (replaced by Zb[abcs] Philipp Tomsich
2021-08-23 17:33 ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 14/15] target/riscv: rewrite slli.uw implementation to mirror formal spec Philipp Tomsich
2021-08-23 17:36 ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 15/15] disas/riscv: Add Zb[abcs] instructions Philipp Tomsich
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