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From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Alejandro Vallejo <alejandro.vallejo@cloud.com>,
	Xen-devel <xen-devel@lists.xenproject.org>
Cc: "Jan Beulich" <jbeulich@suse.com>,
	"Roger Pau Monné" <roger.pau@citrix.com>, "Wei Liu" <wl@xen.org>
Subject: Re: [PATCH v2 2/3] x86: Expose Automatic IBRS to guests
Date: Tue, 30 May 2023 18:31:03 +0100	[thread overview]
Message-ID: <2e1bea58-9f6f-08c0-ce00-148f79ba12ff@citrix.com> (raw)
In-Reply-To: <20230530135854.1517-3-alejandro.vallejo@cloud.com>

On 30/05/2023 2:58 pm, Alejandro Vallejo wrote:
> Expose AutoIBRS to HVM guests. EFER is swapped by VMRUN, so Xen only has to
> make sure writes to EFER.AIBRSE are gated on the feature being exposed.
>
> Also hide EFER.AIBRSE from PV guests as they have no say in the matter.
>
> Signed-off-by: Alejandro Vallejo <alejandro.vallejo@cloud.com>
> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

I've committed this, but made two tweaks to the commit message.  First,
"x86/hvm" in the subject because it's important context at a glance.

Second, I've adjusted the bit about PV guests.  The reason why we can't
expose it yet is because Xen doesn't currently context switch EFER
between PV guests.

~Andrew


  reply	other threads:[~2023-05-30 17:31 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-30 13:58 [PATCH v2 0/3] Add Automatic IBRS support Alejandro Vallejo
2023-05-30 13:58 ` [PATCH v2 1/3] x86: Add bit definitions for Automatic IBRS Alejandro Vallejo
2023-05-30 17:29   ` Andrew Cooper
2023-05-31  8:42     ` Alejandro Vallejo
2023-05-30 13:58 ` [PATCH v2 2/3] x86: Expose Automatic IBRS to guests Alejandro Vallejo
2023-05-30 17:31   ` Andrew Cooper [this message]
2023-05-31  9:01     ` Alejandro Vallejo
2023-05-31 12:38       ` Andrew Cooper
2023-05-30 13:58 ` [PATCH v2 3/3] x86: Add support for AMD's Automatic IBRS Alejandro Vallejo
2023-06-01 10:35   ` Jan Beulich
2023-06-01 10:36     ` Andrew Cooper

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