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* [U-Boot] Pull request: u-boot-riscv/master
@ 2020-05-25  8:01 uboot at andestech.com
  2020-05-25 15:40 ` Tom Rini
  0 siblings, 1 reply; 53+ messages in thread
From: uboot at andestech.com @ 2020-05-25  8:01 UTC (permalink / raw)
  To: u-boot

Hi Tom,

Please pull some riscv updates:

- Add Sipeed Maix support.
- sifive: fix palmer's email address.
- Move all SMP related SBI calls to SBI_v01.

https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/690778926

Thanks
Rick


The following changes since commit 9c5fef577494769e3ff07952a85f9b7125ef765b:

  Merge git://git.denx.de/u-boot-usb (2020-05-22 22:58:50 -0400)

are available in the Git repository at:

  git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to 421c4eb2dcf39f65c31c1804369267ed8a7b5607:

  riscv: Add Sipeed Maix support (2020-05-25 10:01:21 +0800)

----------------------------------------------------------------
Atish Patra (1):
      riscv: Move all SMP related SBI calls to SBI_v01

Pragnesh Patel (1):
      sifive: fix palmer's email address

Sean Anderson (21):
      clk: Always use the supplied struct clk
      clk: Check that ops of composite clock components exist before calling
      clk: Unconditionally recursively en-/dis-able clocks
      clk: Fix clk_get_by_* handling of index
      clk: Add K210 pll support
      clk: Add a bypass clock for K210
      clk: Add K210 clock support
      dm: Add support for simple-pm-bus
      dm: Fix error handling for dev_read_addr_ptr
      reset: Add generic reset driver
      lib: Always set errno in hcreate_r
      riscv: Add headers for asm/global_data.h
      riscv: Clear pending interrupts before enabling IPIs
      riscv: Clean up IPI initialization code
      riscv: Add option to support RISC-V privileged spec 1.9
      riscv: Allow use of reset drivers
      riscv: Try to get cpu frequency from a "clocks" node if it exists
      riscv: Enable cpu clock if it is present
      riscv: Add device tree for K210 and Sipeed Maix BitM
      doc: riscv: Add documentation for Sipeed Maix Bit
      riscv: Add Sipeed Maix support

 MAINTAINERS                                           |   7 +
 arch/riscv/Kconfig                                    |  14 ++
 arch/riscv/cpu/cpu.c                                  |  15 +++
 arch/riscv/cpu/start.S                                |   2 +
 arch/riscv/dts/Makefile                               |   1 +
 arch/riscv/dts/k210-maix-bit.dts                      |  47 +++++++
 arch/riscv/dts/k210.dtsi                              | 594 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/riscv/include/asm/csr.h                          |  40 ++++++
 arch/riscv/include/asm/global_data.h                  |   2 +
 arch/riscv/include/asm/sbi.h                          |   5 +-
 arch/riscv/include/asm/smp.h                          |  43 +++++++
 arch/riscv/lib/andes_plic.c                           |  34 ++---
 arch/riscv/lib/reset.c                                |   2 +
 arch/riscv/lib/sbi.c                                  |  37 +++---
 arch/riscv/lib/sbi_ipi.c                              |   5 +
 arch/riscv/lib/sifive_clint.c                         |  33 ++---
 arch/riscv/lib/smp.c                                  |  49 +------
 arch/sandbox/dts/test.dts                             |  21 +++
 arch/sandbox/include/asm/clk.h                        |   1 +
 board/sifive/fu540/MAINTAINERS                        |   2 +-
 board/sipeed/maix/Kconfig                             |  47 +++++++
 board/sipeed/maix/MAINTAINERS                         |  11 ++
 board/sipeed/maix/Makefile                            |   5 +
 board/sipeed/maix/maix.c                              |  41 ++++++
 common/spl/spl_opensbi.c                              |   5 +
 configs/sandbox_defconfig                             |   3 +
 configs/sipeed_maix_bitm_defconfig                    |   8 ++
 doc/board/index.rst                                   |   1 +
 doc/board/sipeed/index.rst                            |   9 ++
 doc/board/sipeed/maix.rst                             | 298 +++++++++++++++++++++++++++++++++++++++++++
 doc/device-tree-bindings/bus/simple-pm-bus.txt        |  44 +++++++
 doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt |  33 +++++
 doc/device-tree-bindings/reset/syscon-reset.txt       |  36 ++++++
 doc/imx/clk/ccf.txt                                   |  63 ++++-----
 drivers/clk/Kconfig                                   |   1 +
 drivers/clk/Makefile                                  |   1 +
 drivers/clk/clk-composite.c                           |  64 ++++++----
 drivers/clk/clk-divider.c                             |   6 +-
 drivers/clk/clk-fixed-factor.c                        |   3 +-
 drivers/clk/clk-gate.c                                |   6 +-
 drivers/clk/clk-mux.c                                 |  12 +-
 drivers/clk/clk-uclass.c                              |  68 +++++-----
 drivers/clk/imx/clk-gate2.c                           |   4 +-
 drivers/clk/imx/clk-imx8mp.c                          |   2 +-
 drivers/clk/kendryte/Kconfig                          |  12 ++
 drivers/clk/kendryte/Makefile                         |   1 +
 drivers/clk/kendryte/bypass.c                         | 270 +++++++++++++++++++++++++++++++++++++++
 drivers/clk/kendryte/clk.c                            | 663 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/kendryte/pll.c                            | 601 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/core/Kconfig                                  |   7 +
 drivers/core/Makefile                                 |   1 +
 drivers/core/read.c                                   |   2 +-
 drivers/core/simple-pm-bus.c                          |  56 ++++++++
 drivers/cpu/riscv_cpu.c                               |  39 +++++-
 drivers/pinctrl/broadcom/pinctrl-bcm283x.c            |   2 +-
 drivers/pinctrl/mediatek/pinctrl-mtk-common.c         |   2 +-
 drivers/reset/Kconfig                                 |   5 +
 drivers/reset/Makefile                                |   1 +
 drivers/reset/reset-syscon.c                          |  81 ++++++++++++
 include/configs/sipeed-maix.h                         |  24 ++++
 include/dm/read.h                                     |   4 +-
 include/dt-bindings/clock/k210-sysctl.h               |  59 +++++++++
 include/dt-bindings/mfd/k210-sysctl.h                 |  38 ++++++
 include/dt-bindings/reset/k210-sysctl.h               |  38 ++++++
 include/kendryte/bypass.h                             |  31 +++++
 include/kendryte/clk.h                                |  35 +++++
 include/kendryte/pll.h                                |  57 +++++++++
 include/test/export.h                                 |  16 +++
 lib/hashtable.c                                       |   8 +-
 test/dm/Makefile                                      |   3 +
 test/dm/k210_pll.c                                    |  96 ++++++++++++++
 test/dm/simple-pm-bus.c                               |  45 +++++++
 test/dm/syscon-reset.c                                |  59 +++++++++
 73 files changed, 3754 insertions(+), 227 deletions(-)
 create mode 100644 arch/riscv/dts/k210-maix-bit.dts
 create mode 100644 arch/riscv/dts/k210.dtsi
 create mode 100644 board/sipeed/maix/Kconfig
 create mode 100644 board/sipeed/maix/MAINTAINERS
 create mode 100644 board/sipeed/maix/Makefile
 create mode 100644 board/sipeed/maix/maix.c
 create mode 100644 configs/sipeed_maix_bitm_defconfig
 create mode 100644 doc/board/sipeed/index.rst
 create mode 100644 doc/board/sipeed/maix.rst
 create mode 100644 doc/device-tree-bindings/bus/simple-pm-bus.txt
 create mode 100644 doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt
 create mode 100644 doc/device-tree-bindings/reset/syscon-reset.txt
 create mode 100644 drivers/clk/kendryte/Kconfig
 create mode 100644 drivers/clk/kendryte/Makefile
 create mode 100644 drivers/clk/kendryte/bypass.c
 create mode 100644 drivers/clk/kendryte/clk.c
 create mode 100644 drivers/clk/kendryte/pll.c
 create mode 100644 drivers/core/simple-pm-bus.c
 create mode 100644 drivers/reset/reset-syscon.c
 create mode 100644 include/configs/sipeed-maix.h
 create mode 100644 include/dt-bindings/clock/k210-sysctl.h
 create mode 100644 include/dt-bindings/mfd/k210-sysctl.h
 create mode 100644 include/dt-bindings/reset/k210-sysctl.h
 create mode 100644 include/kendryte/bypass.h
 create mode 100644 include/kendryte/clk.h
 create mode 100644 include/kendryte/pll.h
 create mode 100644 include/test/export.h
 create mode 100644 test/dm/k210_pll.c
 create mode 100644 test/dm/simple-pm-bus.c
 create mode 100644 test/dm/syscon-reset.c

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2020-05-25  8:01 [U-Boot] Pull request: u-boot-riscv/master uboot at andestech.com
@ 2020-05-25 15:40 ` Tom Rini
       [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA470F21C@ATCPCS16.andestech.com>
  0 siblings, 1 reply; 53+ messages in thread
From: Tom Rini @ 2020-05-25 15:40 UTC (permalink / raw)
  To: u-boot

On Mon, May 25, 2020 at 04:01:08PM +0800, uboot at andestech.com wrote:

> Hi Tom,
> 
> Please pull some riscv updates:
> 
> - Add Sipeed Maix support.
> - sifive: fix palmer's email address.
> - Move all SMP related SBI calls to SBI_v01.
> 
> https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/690778926
> 
> Thanks
> Rick
> 
> 
> The following changes since commit 9c5fef577494769e3ff07952a85f9b7125ef765b:
> 
>   Merge git://git.denx.de/u-boot-usb (2020-05-22 22:58:50 -0400)
> 
> are available in the Git repository at:
> 
>   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> 
> for you to fetch changes up to 421c4eb2dcf39f65c31c1804369267ed8a7b5607:
> 
>   riscv: Add Sipeed Maix support (2020-05-25 10:01:21 +0800)
> 

There's too many generic changes in this PR for this late in the cycle,
for things I gather related to the Maix platform.  All of the clk and DM
changes impact virtually all platforms.  Please re-do this PR to drop
the Maix platform support for now, and resubmit that for -next, which I
will be opening shortly.  Everything else however is good for master.
Sorry.

-- 
Tom
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^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
       [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA470F21C@ATCPCS16.andestech.com>
@ 2020-05-26  7:41     ` Rick Chen
  2020-06-22  6:03     ` Rick Chen
  1 sibling, 0 replies; 53+ messages in thread
From: Rick Chen @ 2020-05-26  7:41 UTC (permalink / raw)
  To: u-boot

Hi Tom

> From: Tom Rini [mailto:trini at konsulko.com]
> Sent: Monday, May 25, 2020 11:40 PM
> To: Open Source Project uboot
> Cc: u-boot at lists.denx.de; Rick Jian-Zhi Chen(???)
> Subject: Re: [U-Boot] Pull request: u-boot-riscv/master
>
> On Mon, May 25, 2020 at 04:01:08PM +0800, uboot at andestech.com wrote:
>
> > Hi Tom,
> >
> > Please pull some riscv updates:
> >
> > - Add Sipeed Maix support.
> > - sifive: fix palmer's email address.
> > - Move all SMP related SBI calls to SBI_v01.
> >
> > https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/690778926
> >
> > Thanks
> > Rick
> >
> >
> > The following changes since commit 9c5fef577494769e3ff07952a85f9b7125ef765b:
> >
> >   Merge git://git.denx.de/u-boot-usb (2020-05-22 22:58:50 -0400)
> >
> > are available in the Git repository at:
> >
> >   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> >
> > for you to fetch changes up to 421c4eb2dcf39f65c31c1804369267ed8a7b5607:
> >
> >   riscv: Add Sipeed Maix support (2020-05-25 10:01:21 +0800)
> >
>
> There's too many generic changes in this PR for this late in the cycle, for things I gather related to the Maix platform.  All of the clk and DM changes impact virtually all platforms.  Please re-do this PR to drop the Maix platform support for now, and resubmit that for -next, which I will be opening shortly.  Everything else however is good for master.

Thanks for your explanations.
Actually I have the same concern with you before sending this PR.

I have tried to ask Sean don't mix all codes together in one patchset.
He shall separate and send them individually, If they are not highly dependent.

Following are my suggestions from those patch-work:

Re: [PATCH v2 01/11] clk: Always use the supplied struct clk
https://patchwork.ozlabs.org/project/uboot/patch/da401261-b73f-afae-0702-ada1e7dd836b at gmail.com/

Re: [PATCH v4 07/17] spi: dw: Add mem_ops
https://patchwork.ozlabs.org/project/uboot/patch/20200211060425.1619471-8-seanga2 at gmail.com/

Re: [PATCH v5 33/33] riscv: Add Sipeed Maix support
http://u-boot.10912.n7.nabble.com/PATCH-v5-00-33-riscv-Add-Sipeed-Maix-support-tt401784.html#a402055

Re: [PATCH v6 04/19] clk: Add functions to register CCF clock structs
https://patchwork.ozlabs.org/project/uboot/patch/20200305181308.944595-5-seanga2 at gmail.com/

I will drop the Maix platform support in next PR and re-send again.

Thanks,
Rick


> Sorry.
>
> --
> Tom

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
       [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA470F21C@ATCPCS16.andestech.com>
  2020-05-26  7:41     ` Rick Chen
@ 2020-06-22  6:03     ` Rick Chen
  2020-06-23  0:45       ` Tom Rini
  1 sibling, 1 reply; 53+ messages in thread
From: Rick Chen @ 2020-06-22  6:03 UTC (permalink / raw)
  To: u-boot

Hi Tom

> From: Tom Rini [mailto:trini at konsulko.com]
> Sent: Monday, May 25, 2020 11:40 PM
> To: Open Source Project uboot
> Cc: u-boot at lists.denx.de; Rick Jian-Zhi Chen(???)
> Subject: Re: [U-Boot] Pull request: u-boot-riscv/master
>
> On Mon, May 25, 2020 at 04:01:08PM +0800, uboot at andestech.com wrote:
>
> > Hi Tom,
> >
> > Please pull some riscv updates:
> >
> > - Add Sipeed Maix support.
> > - sifive: fix palmer's email address.
> > - Move all SMP related SBI calls to SBI_v01.
> >
> > https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/690778926
> >
> > Thanks
> > Rick
> >
> >
> > The following changes since commit 9c5fef577494769e3ff07952a85f9b7125ef765b:
> >
> >   Merge git://git.denx.de/u-boot-usb (2020-05-22 22:58:50 -0400)
> >
> > are available in the Git repository at:
> >
> >   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> >
> > for you to fetch changes up to 421c4eb2dcf39f65c31c1804369267ed8a7b5607:
> >
> >   riscv: Add Sipeed Maix support (2020-05-25 10:01:21 +0800)
> >
>
> There's too many generic changes in this PR for this late in the cycle, for things I gather related to the Maix platform.  All of the clk and DM changes impact virtually all platforms.  Please re-do this PR to drop the Maix platform support for now, and resubmit that for -next, which I will be opening shortly.  Everything else however is good for master.

May I ask for your suggestions about this patch series about "riscv:
Add Sipeed Maix support " ?
Shall I send a PR include this patch series in early release cycle or
shall I suggest Sean to re-edit this patch series for less generic
changes which may bring virtual impacts?

Thanks,
Rick

> Sorry.


>
> --
> Tom

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2020-06-22  6:03     ` Rick Chen
@ 2020-06-23  0:45       ` Tom Rini
  2020-06-23  2:05         ` Rick Chen
  2020-06-24  1:31         ` Rick Chen
  0 siblings, 2 replies; 53+ messages in thread
From: Tom Rini @ 2020-06-23  0:45 UTC (permalink / raw)
  To: u-boot

On Mon, Jun 22, 2020 at 02:03:52PM +0800, Rick Chen wrote:
> Hi Tom
> 
> > From: Tom Rini [mailto:trini at konsulko.com]
> > Sent: Monday, May 25, 2020 11:40 PM
> > To: Open Source Project uboot
> > Cc: u-boot at lists.denx.de; Rick Jian-Zhi Chen(???)
> > Subject: Re: [U-Boot] Pull request: u-boot-riscv/master
> >
> > On Mon, May 25, 2020 at 04:01:08PM +0800, uboot at andestech.com wrote:
> >
> > > Hi Tom,
> > >
> > > Please pull some riscv updates:
> > >
> > > - Add Sipeed Maix support.
> > > - sifive: fix palmer's email address.
> > > - Move all SMP related SBI calls to SBI_v01.
> > >
> > > https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/690778926
> > >
> > > Thanks
> > > Rick
> > >
> > >
> > > The following changes since commit 9c5fef577494769e3ff07952a85f9b7125ef765b:
> > >
> > >   Merge git://git.denx.de/u-boot-usb (2020-05-22 22:58:50 -0400)
> > >
> > > are available in the Git repository at:
> > >
> > >   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> > >
> > > for you to fetch changes up to 421c4eb2dcf39f65c31c1804369267ed8a7b5607:
> > >
> > >   riscv: Add Sipeed Maix support (2020-05-25 10:01:21 +0800)
> > >
> >
> > There's too many generic changes in this PR for this late in the cycle, for things I gather related to the Maix platform.  All of the clk and DM changes impact virtually all platforms.  Please re-do this PR to drop the Maix platform support for now, and resubmit that for -next, which I will be opening shortly.  Everything else however is good for master.
> 
> May I ask for your suggestions about this patch series about "riscv:
> Add Sipeed Maix support " ?
> Shall I send a PR include this patch series in early release cycle or
> shall I suggest Sean to re-edit this patch series for less generic
> changes which may bring virtual impacts?

So I looked over the generic changes again.  There's no other way to
support the platform without those type of changes, yes?  If so, yes,
lets put it in to -next.

-- 
Tom
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^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2020-06-23  0:45       ` Tom Rini
@ 2020-06-23  2:05         ` Rick Chen
  2020-06-24  1:31         ` Rick Chen
  1 sibling, 0 replies; 53+ messages in thread
From: Rick Chen @ 2020-06-23  2:05 UTC (permalink / raw)
  To: u-boot

Hi Tom,

> On Mon, Jun 22, 2020 at 02:03:52PM +0800, Rick Chen wrote:
> > Hi Tom
> >
> > > From: Tom Rini [mailto:trini at konsulko.com]
> > > Sent: Monday, May 25, 2020 11:40 PM
> > > To: Open Source Project uboot
> > > Cc: u-boot at lists.denx.de; Rick Jian-Zhi Chen(???)
> > > Subject: Re: [U-Boot] Pull request: u-boot-riscv/master
> > >
> > > On Mon, May 25, 2020 at 04:01:08PM +0800, uboot at andestech.com wrote:
> > >
> > > > Hi Tom,
> > > >
> > > > Please pull some riscv updates:
> > > >
> > > > - Add Sipeed Maix support.
> > > > - sifive: fix palmer's email address.
> > > > - Move all SMP related SBI calls to SBI_v01.
> > > >
> > > > https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/690778926
> > > >
> > > > Thanks
> > > > Rick
> > > >
> > > >
> > > > The following changes since commit 9c5fef577494769e3ff07952a85f9b7125ef765b:
> > > >
> > > >   Merge git://git.denx.de/u-boot-usb (2020-05-22 22:58:50 -0400)
> > > >
> > > > are available in the Git repository at:
> > > >
> > > >   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> > > >
> > > > for you to fetch changes up to 421c4eb2dcf39f65c31c1804369267ed8a7b5607:
> > > >
> > > >   riscv: Add Sipeed Maix support (2020-05-25 10:01:21 +0800)
> > > >
> > >
> > > There's too many generic changes in this PR for this late in the cycle, for things I gather related to the Maix platform.  All of the clk and DM changes impact virtually all platforms.  Please re-do this PR to drop the Maix platform support for now, and resubmit that for -next, which I will be opening shortly.  Everything else however is good for master.
> >
> > May I ask for your suggestions about this patch series about "riscv:
> > Add Sipeed Maix support " ?
> > Shall I send a PR include this patch series in early release cycle or
> > shall I suggest Sean to re-edit this patch series for less generic
> > changes which may bring virtual impacts?
>
> So I looked over the generic changes again.  There's no other way to
> support the platform without those type of changes, yes?

Yes. Discusstion between Sean and Lukasz about clk as below:
https://patchwork.ozlabs.org/project/uboot/patch/da401261-b73f-afae-0702-ada1e7dd836b at gmail.com/#2346363

If so, yes,
> lets put it in to -next.

Thanks for your reply.

Rick

>
> --
> Tom

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2020-06-23  0:45       ` Tom Rini
  2020-06-23  2:05         ` Rick Chen
@ 2020-06-24  1:31         ` Rick Chen
  2020-06-24  3:37           ` Sean Anderson
  1 sibling, 1 reply; 53+ messages in thread
From: Rick Chen @ 2020-06-24  1:31 UTC (permalink / raw)
  To: u-boot

Hi Sean

Tom Rini <trini@konsulko.com> ? 2020?6?23? ?? ??8:45???
>
> On Mon, Jun 22, 2020 at 02:03:52PM +0800, Rick Chen wrote:
> > Hi Tom
> >
> > > From: Tom Rini [mailto:trini at konsulko.com]
> > > Sent: Monday, May 25, 2020 11:40 PM
> > > To: Open Source Project uboot
> > > Cc: u-boot at lists.denx.de; Rick Jian-Zhi Chen(???)
> > > Subject: Re: [U-Boot] Pull request: u-boot-riscv/master
> > >
> > > On Mon, May 25, 2020 at 04:01:08PM +0800, uboot at andestech.com wrote:
> > >
> > > > Hi Tom,
> > > >
> > > > Please pull some riscv updates:
> > > >
> > > > - Add Sipeed Maix support.
> > > > - sifive: fix palmer's email address.
> > > > - Move all SMP related SBI calls to SBI_v01.
> > > >
> > > > https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/690778926
> > > >
> > > > Thanks
> > > > Rick
> > > >
> > > >
> > > > The following changes since commit 9c5fef577494769e3ff07952a85f9b7125ef765b:
> > > >
> > > >   Merge git://git.denx.de/u-boot-usb (2020-05-22 22:58:50 -0400)
> > > >
> > > > are available in the Git repository at:
> > > >
> > > >   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> > > >
> > > > for you to fetch changes up to 421c4eb2dcf39f65c31c1804369267ed8a7b5607:
> > > >
> > > >   riscv: Add Sipeed Maix support (2020-05-25 10:01:21 +0800)
> > > >
> > >
> > > There's too many generic changes in this PR for this late in the cycle, for things I gather related to the Maix platform.  All of the clk and DM changes impact virtually all platforms.  Please re-do this PR to drop the Maix platform support for now, and resubmit that for -next, which I will be opening shortly.  Everything else however is good for master.
> >
> > May I ask for your suggestions about this patch series about "riscv:
> > Add Sipeed Maix support " ?
> > Shall I send a PR include this patch series in early release cycle or
> > shall I suggest Sean to re-edit this patch series for less generic
> > changes which may bring virtual impacts?
>
> So I looked over the generic changes again.  There's no other way to
> support the platform without those type of changes, yes?  If so, yes,
> lets put it in to -next.

Please rebase -next for upstream
There are some conflicts needed to be fixed.

Applying: clk: Always use the supplied struct clk
Applying: clk: Check that ops of composite clock components exist before calling
Applying: clk: Unconditionally recursively en-/dis-able clocks
Applying: clk: Fix clk_get_by_* handling of index
Applying: clk: Add K210 pll support
Applying: clk: Add a bypass clock for K210
Applying: clk: Add K210 clock support
Applying: dm: Add support for simple-pm-bus
Applying: dm: Fix error handling for dev_read_addr_ptr
Applying: reset: Add generic reset driver
error: patch failed: configs/sandbox_defconfig:196
error: configs/sandbox_defconfig: patch does not apply
Patch failed at 0010 reset: Add generic reset driver

Thanks,
Rick

>
> --
> Tom

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2020-06-24  1:31         ` Rick Chen
@ 2020-06-24  3:37           ` Sean Anderson
  0 siblings, 0 replies; 53+ messages in thread
From: Sean Anderson @ 2020-06-24  3:37 UTC (permalink / raw)
  To: u-boot

On 5/26/20 3:41 AM, Rick Chen wrote:
> Hi Tom
> 
>> From: Tom Rini [mailto:trini at konsulko.com]
>> Sent: Monday, May 25, 2020 11:40 PM
>> To: Open Source Project uboot
>> Cc: u-boot at lists.denx.de; Rick Jian-Zhi Chen(???)
>> Subject: Re: [U-Boot] Pull request: u-boot-riscv/master
>>
>> On Mon, May 25, 2020 at 04:01:08PM +0800, uboot at andestech.com wrote:
>>
>>> Hi Tom,
>>>
>>> Please pull some riscv updates:
>>>
>>> - Add Sipeed Maix support.
>>> - sifive: fix palmer's email address.
>>> - Move all SMP related SBI calls to SBI_v01.
>>>
>>> https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/690778926
>>>
>>> Thanks
>>> Rick
>>>
>>>
>>> The following changes since commit 9c5fef577494769e3ff07952a85f9b7125ef765b:
>>>
>>>   Merge git://git.denx.de/u-boot-usb (2020-05-22 22:58:50 -0400)
>>>
>>> are available in the Git repository at:
>>>
>>>   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
>>>
>>> for you to fetch changes up to 421c4eb2dcf39f65c31c1804369267ed8a7b5607:
>>>
>>>   riscv: Add Sipeed Maix support (2020-05-25 10:01:21 +0800)
>>>
>>

Hi, I just saw this thread, and I would like to comment on a few things.

>> There's too many generic changes in this PR for this late in the cycle, for things I gather related to the Maix platform.  All of the clk and DM changes impact virtually all platforms.  Please re-do this PR to drop the Maix platform support for now, and resubmit that for -next, which I will be opening shortly.  Everything else however is good for master.
> 
> Thanks for your explanations.
> Actually I have the same concern with you before sending this PR.
> 
> I have tried to ask Sean don't mix all codes together in one patchset.
> He shall separate and send them individually, If they are not highly dependent.

I have been asked by Bin Meng and others to keep together related
patches so that the patch which uses changed/new behaviour is in the
same series as the patch which changes the behavior. I have tried to
split out unrelated patches and minimize changes. Would you rather all
patches which do not explicitly add maix support be split off from this
series?

> 
> Following are my suggestions from those patch-work:
> 
> Re: [PATCH v2 01/11] clk: Always use the supplied struct clk
> https://patchwork.ozlabs.org/project/uboot/patch/da401261-b73f-afae-0702-ada1e7dd836b at gmail.com/

The composite clock framework is only used by IMX in U-Boot as far as I
can tell. As such, it has a number of (mis)features which make it
unsuitable for generic code. These quirks are generally worked around in
a variety of ways by IMX code, often by using custom functions instead
of those within the CCF itself. The maix platform has around 40 clocks
in a complicated tree, and is not constrained by RAM or flash. Given
these circumstances, I think using the CCF is the correct choice.
However, in order to do so, I have had to address many of the quirks. I
could also add support for maix by effectively duplicating the CCF
within the maix driver. However, I think such a duplication of code is
likely to rot over time.

I have tried to describe why I think each of the clk patches should be
included in their commit messages. It may be unclear what the impact
will be on other users of the clock subsystem and the CCF.

[01/21] clk: Always use the supplied struct clk

This patch only affects users of the CCF. As discussed in the above
link, this specific behaviour is left over from when the CCF was ported
from Linux, due to the different semantics between struct clk and struct
clk_core. The problem here is that with the current system, either a
struct device must be associated with each CCF clock (a significant
overhead), or custom functions must be used for CCF clock operations.
The latter approach is used by the IMX code, but I would like to be able
to use the generic functions which are provided by CCF clocks.

[v13,02/21] clk: Check that ops of composite clock components exist before calling 

This only affects the CCF subsystem. This is a bugfix for drivers which
use composite clocks and do not always have the same sub-clocks. Without
this patch, if one registers a composite clock with a gate sub-clock,
and then registers another composite clock without a gate sub-clock,
calling a enable or disable on the latter clock will result in calling a
NULL pointer. No drivers currently use this functionality, but it is a
"gotcha" if one implements a driver which does.

[v13,03/21] clk: Unconditionally recursively en-/dis-able clocks

This affects all clock drivers, but primarily affects CCF clocks. This
patch is designed to handle a case with a configuration like


   A
  / \
 B   C
 |
 D

where B is a clock with an id of 0. If D is enabled, B and A will not be
enabled. If C is enabled, A will also be enabled. If C is then disabled,
A will also be disabled. This can cause strange behaviour. I have since
added ids to all clocks I use, so this patch can be split off.

[v13,04/21] clk: Fix clk_get_by_* handling of index 

This affects all clock drivers, but is a bugfix. The parameters passed
to clk_get_by_index_tail have the wrong semantics. This patch primarily
affects callers of clk_get_by_index_nodev (2 drivers), and improves
error messages.

So of these four patches, I think 3 are 100% necessary for new drivers
using the CCF. One is nice to have, but could be split off to reduce the
scope of this patch. I would have liked to get all of these patches
reviewed by Lukas, but he hasn't commented on this series for several
months. I would also love to test some of these patches on IMX, but I
don't own any boards with IMX on them.

> Re: [PATCH v4 07/17] spi: dw: Add mem_ops
> https://patchwork.ozlabs.org/project/uboot/patch/20200211060425.1619471-8-seanga2 at gmail.com/

Here I took your advice and split off the pinctrl-, gpio-, and spi-related patches.

> 
> Re: [PATCH v5 33/33] riscv: Add Sipeed Maix support
> http://u-boot.10912.n7.nabble.com/PATCH-v5-00-33-riscv-Add-Sipeed-Maix-support-tt401784.html#a402055

ditto

> 
> Re: [PATCH v6 04/19] clk: Add functions to register CCF clock structs
> https://patchwork.ozlabs.org/project/uboot/patch/20200305181308.944595-5-seanga2 at gmail.com/

I removed this patch in the next revision of the series.

On 6/23/20 9:31 PM, Rick Chen wrote:
> Hi Sean
> 
> Tom Rini <trini@konsulko.com> ? 2020?6?23? ?? ??8:45???
>> So I looked over the generic changes again.  There's no other way to
>> support the platform without those type of changes, yes?  If so, yes,
>> lets put it in to -next.

I saw this only after writing the above explanation, but hopefully it
will stioll be helpful.

> 
> Please rebase -next for upstream
> There are some conflicts needed to be fixed.
> 
> Applying: clk: Always use the supplied struct clk
> Applying: clk: Check that ops of composite clock components exist before calling
> Applying: clk: Unconditionally recursively en-/dis-able clocks
> Applying: clk: Fix clk_get_by_* handling of index
> Applying: clk: Add K210 pll support
> Applying: clk: Add a bypass clock for K210
> Applying: clk: Add K210 clock support
> Applying: dm: Add support for simple-pm-bus
> Applying: dm: Fix error handling for dev_read_addr_ptr
> Applying: reset: Add generic reset driver
> error: patch failed: configs/sandbox_defconfig:196
> error: configs/sandbox_defconfig: patch does not apply
> Patch failed at 0010 reset: Add generic reset driver

Ok, I can rebase again.

--Sean

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2020-07-03  6:01     ` Rick Chen
@ 2020-07-03  6:52       ` Bin Meng
  0 siblings, 0 replies; 53+ messages in thread
From: Bin Meng @ 2020-07-03  6:52 UTC (permalink / raw)
  To: u-boot

Hi Rick,

On Fri, Jul 3, 2020 at 2:01 PM Rick Chen <rickchen36@gmail.com> wrote:
>
> > From: Tom Rini [mailto:trini at konsulko.com]
> > Sent: Thursday, July 02, 2020 9:53 PM
> > To: Open Source Project uboot
> > Cc: u-boot at lists.denx.de; Rick Jian-Zhi Chen(???)
> > Subject: Re: [U-Boot] Pull request: u-boot-riscv/master
> >
> > On Thu, Jul 02, 2020 at 10:51:48AM +0800, uboot at andestech.com wrote:
> >
> > > Hi Tom,
> > >
> > > Please pull some riscv updates:
> > >
> > > - sbi: Add newline to error message
> > > - fu540: dts: Correct reg size of otp and dmc nodes
> > > - Enhance reserved memory fixup about PMP information passed from
> > > OpenSbi
> > > - sifive: fu540: Add gpio-restart support
> > > - qemu: Add syscon reboot and poweroff support
> > > - qemu-riscv: Update QEMU run command
> > > - Assorted fixes related to reserved memory
> > > - fu540: enable all cache ways from U-Boot proper
> > > - use log functions in fdt_fixup
> >
> > This changes a few MIPS and ARM platforms.  We're a few days away from release, so I don't feel comfortable taking this right now as I assume it hasn't been tested on the other platforms as well.  Sorry.
>
> Hi Tom,
>
> Thanks for your suggestions.
>
>
> Hi Bin,
>
> Can you separate this series about sysreset into two series ?
> [PATCH 1/5] sysreset: syscon: Don't assume default value for offset
> and mask property
> [PATCH 2/5] sysreset: syscon: Support value property
> [PATCH 3/5] riscv: Do not build reset.c if SYSRESET is on
> [PATCH 4/5] riscv: qemu: Add syscon reboot and poweroff support
> [PATCH 5/5] riscv: sifive: fu540: Add gpio-restart support
>
> It looks like that patch 3/5, 4/5, 5/5 doesn't depend on patch 1/5 and 2/5.

Patch 3 and 5 can be targeted for this release, and let's do patch
1,2,4 for the next release.

So you can drop patch 1,2,4 in your queue and resend the PR. Thanks!

Regards,
Bin

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
       [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA47207DF@ATCPCS16.andestech.com>
@ 2020-07-03  6:01     ` Rick Chen
  2020-07-03  6:52       ` Bin Meng
  0 siblings, 1 reply; 53+ messages in thread
From: Rick Chen @ 2020-07-03  6:01 UTC (permalink / raw)
  To: u-boot

> From: Tom Rini [mailto:trini at konsulko.com]
> Sent: Thursday, July 02, 2020 9:53 PM
> To: Open Source Project uboot
> Cc: u-boot at lists.denx.de; Rick Jian-Zhi Chen(???)
> Subject: Re: [U-Boot] Pull request: u-boot-riscv/master
>
> On Thu, Jul 02, 2020 at 10:51:48AM +0800, uboot at andestech.com wrote:
>
> > Hi Tom,
> >
> > Please pull some riscv updates:
> >
> > - sbi: Add newline to error message
> > - fu540: dts: Correct reg size of otp and dmc nodes
> > - Enhance reserved memory fixup about PMP information passed from
> > OpenSbi
> > - sifive: fu540: Add gpio-restart support
> > - qemu: Add syscon reboot and poweroff support
> > - qemu-riscv: Update QEMU run command
> > - Assorted fixes related to reserved memory
> > - fu540: enable all cache ways from U-Boot proper
> > - use log functions in fdt_fixup
>
> This changes a few MIPS and ARM platforms.  We're a few days away from release, so I don't feel comfortable taking this right now as I assume it hasn't been tested on the other platforms as well.  Sorry.

Hi Tom,

Thanks for your suggestions.


Hi Bin,

Can you separate this series about sysreset into two series ?
[PATCH 1/5] sysreset: syscon: Don't assume default value for offset
and mask property
[PATCH 2/5] sysreset: syscon: Support value property
[PATCH 3/5] riscv: Do not build reset.c if SYSRESET is on
[PATCH 4/5] riscv: qemu: Add syscon reboot and poweroff support
[PATCH 5/5] riscv: sifive: fu540: Add gpio-restart support

It looks like that patch 3/5, 4/5, 5/5 doesn't depend on patch 1/5 and 2/5.

Thanks,
Rick

>
> --

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2020-07-02  2:51 uboot at andestech.com
@ 2020-07-02 13:53 ` Tom Rini
       [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA47207DF@ATCPCS16.andestech.com>
  0 siblings, 1 reply; 53+ messages in thread
From: Tom Rini @ 2020-07-02 13:53 UTC (permalink / raw)
  To: u-boot

On Thu, Jul 02, 2020 at 10:51:48AM +0800, uboot at andestech.com wrote:

> Hi Tom,
> 
> Please pull some riscv updates:
> 
> - sbi: Add newline to error message
> - fu540: dts: Correct reg size of otp and dmc nodes
> - Enhance reserved memory fixup about PMP information passed from OpenSbi
> - sifive: fu540: Add gpio-restart support
> - qemu: Add syscon reboot and poweroff support
> - qemu-riscv: Update QEMU run command
> - Assorted fixes related to reserved memory
> - fu540: enable all cache ways from U-Boot proper
> - use log functions in fdt_fixup

This changes a few MIPS and ARM platforms.  We're a few days away from
release, so I don't feel comfortable taking this right now as I assume
it hasn't been tested on the other platforms as well.  Sorry.

-- 
Tom
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^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
@ 2020-07-02  2:51 uboot at andestech.com
  2020-07-02 13:53 ` Tom Rini
  0 siblings, 1 reply; 53+ messages in thread
From: uboot at andestech.com @ 2020-07-02  2:51 UTC (permalink / raw)
  To: u-boot

Hi Tom,

Please pull some riscv updates:

- sbi: Add newline to error message
- fu540: dts: Correct reg size of otp and dmc nodes
- Enhance reserved memory fixup about PMP information passed from OpenSbi
- sifive: fu540: Add gpio-restart support
- qemu: Add syscon reboot and poweroff support
- qemu-riscv: Update QEMU run command
- Assorted fixes related to reserved memory
- fu540: enable all cache ways from U-Boot proper
- use log functions in fdt_fixup

Thanks
Rick

https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/703843003

The following changes since commit bcfe764ee925d0820e82c69ccf75b71d142644c7:

  Merge tag 'efi-2020-07-rc6-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi (2020-06-30 17:15:39 -0400)

are available in the Git repository at:

  git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to f889e3183a003e4e238f87cc9bb01bfcbd5548a5:

  riscv: use log functions in fdt_fixup (2020-07-02 10:31:39 +0800)

----------------------------------------------------------------
Atish Patra (2):
      riscv: Do not return error if reserved node already exists
      riscv: Use optimized version of fdtdec_get_addr_size_no_parent

Bin Meng (11):
      riscv: fu540: dts: Remove the unnecessary space in the cpu2_intc node
      riscv: fu540: dts: Correct reg size of otp and dmc nodes
      riscv: Avoid the reserved memory fixup if src and dst point to the same place
      riscv: Expand the DT size before copy reserved memory node
      riscv: Enable CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATE
      sysreset: syscon: Don't assume default value for offset and mask property
      sysreset: syscon: Support value property
      riscv: Do not build reset.c if SYSRESET is on
      riscv: qemu: Add syscon reboot and poweroff support
      riscv: sifive: fu540: Add gpio-restart support
      doc: qemu-riscv: Update QEMU run command

Heinrich Schuchardt (1):
      riscv: use log functions in fdt_fixup

Pragnesh Patel (1):
      riscv: sifive: fu540: enable all cache ways from U-Boot proper

Sean Anderson (1):
      riscv: sbi: Add newline to error message

 arch/riscv/Kconfig                        |  3 +++
 arch/riscv/cpu/fu540/Makefile             |  1 +
 arch/riscv/cpu/fu540/cache.c              | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/riscv/dts/fu540-c000-u-boot.dtsi     | 10 +++++++---
 arch/riscv/include/asm/arch-fu540/cache.h | 14 ++++++++++++++
 arch/riscv/lib/Makefile                   |  2 ++
 arch/riscv/lib/fdt_fixup.c                | 46 ++++++++++++++++++++++++++++++++--------------
 board/emulation/qemu-riscv/Kconfig        |  4 ++++
 board/sifive/fu540/Kconfig                |  2 ++
 board/sifive/fu540/fu540.c                | 10 +++++++++-
 common/spl/spl_opensbi.c                  |  2 +-
 configs/sifive_fu540_defconfig            |  1 -
 doc/board/emulation/qemu-riscv.rst        | 10 +++++-----
 drivers/sysreset/sysreset_syscon.c        | 28 +++++++++++++++++++++++++---
 14 files changed, 158 insertions(+), 28 deletions(-)
 create mode 100644 arch/riscv/cpu/fu540/cache.c
 create mode 100644 arch/riscv/include/asm/arch-fu540/cache.h

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
       [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA471C57A@ATCPCS16.andestech.com>
@ 2020-06-24  3:13     ` Rick Chen
  0 siblings, 0 replies; 53+ messages in thread
From: Rick Chen @ 2020-06-24  3:13 UTC (permalink / raw)
  To: u-boot

Hi Tom

> From: Bin Meng [mailto:bmeng.cn at gmail.com]
> Sent: Wednesday, June 24, 2020 10:58 AM
> To: Open Source Project uboot
> Cc: Tom Rini; U-Boot Mailing List; Rick Jian-Zhi Chen(???)
> Subject: Re: [U-Boot] Pull request: u-boot-riscv/master
>
> Hi Rick,
>
> On Wed, Jun 24, 2020 at 10:41 AM <uboot@andestech.com> wrote:
> >
> > Hi Tom,
> >
> > Please pull some riscv updates:
> >
> > - fu540: dts: Correct reg size of otp and dmc nodes
> > - sbi: Add newline to error message
> > - sifive/fu540: Enable SPI-NOR support
> >
> > Thanks
> > Rick
> >
> > https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/701223929
> >
> >
> > The following changes since commit 4ff63383e3497389e66cf70943a83bdb1810462a:
> >
> >   Merge tag 'u-boot-imx-20200623' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2020-06-23 08:20:55 -0400)
> >
> > are available in the Git repository at:
> >
> >   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> >
> > for you to fetch changes up to 2148d9c76ef5efbf5b98ca3d3fcbaad465115e70:
> >
> >   riscv: fu540: dts: Correct reg size of otp and dmc nodes (2020-06-24 09:59:30 +0800)
> >
> > ----------------------------------------------------------------
> > Bin Meng (2):
> >       riscv: fu540: dts: Remove the unnecessary space in the cpu2_intc node
> >       riscv: fu540: dts: Correct reg size of otp and dmc nodes
> >
> > Jagan Teki (6):
> >       sifive: fu540: Add runtime boot mode detection
> >       sifive: fu540: Add Booting from SPI
> >       env: Enable SPI flash env for SiFive FU540
> >       sifive: fu540: Mark the default env as SPI flash
> >       sifive: fu540: Add boot flash script offset, size
> >       sifive: fu540: Enable SF distro bootcmd
>
> You missed my review comments for Jagan's series.
> https://lists.denx.de/pipermail/u-boot/2020-June/417066.html
>
> Please hold on.

Please drop this PR.

Thanks,
Rick

>
> >
> > Sean Anderson (1):
> >       riscv: sbi: Add newline to error message
> >
>
> Regards,
> Bin
> CONFIDENTIALITY NOTICE:
>
> This e-mail (and its attachments) may contain confidential and legally privileged information or information protected from disclosure. If you are not the intended recipient, you are hereby notified that any disclosure, copying, distribution, or use of the information contained herein is strictly prohibited. In this case, please immediately notify the sender by return e-mail, delete the message (and any accompanying documents) and destroy all printed hard copies. Thank you for your cooperation.
>
> Copyright ANDES TECHNOLOGY CORPORATION - All Rights Reserved.

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2020-06-24  2:30 uboot at andestech.com
@ 2020-06-24  2:57 ` Bin Meng
       [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA471C57A@ATCPCS16.andestech.com>
  0 siblings, 1 reply; 53+ messages in thread
From: Bin Meng @ 2020-06-24  2:57 UTC (permalink / raw)
  To: u-boot

Hi Rick,

On Wed, Jun 24, 2020 at 10:41 AM <uboot@andestech.com> wrote:
>
> Hi Tom,
>
> Please pull some riscv updates:
>
> - fu540: dts: Correct reg size of otp and dmc nodes
> - sbi: Add newline to error message
> - sifive/fu540: Enable SPI-NOR support
>
> Thanks
> Rick
>
> https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/701223929
>
>
> The following changes since commit 4ff63383e3497389e66cf70943a83bdb1810462a:
>
>   Merge tag 'u-boot-imx-20200623' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2020-06-23 08:20:55 -0400)
>
> are available in the Git repository at:
>
>   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
>
> for you to fetch changes up to 2148d9c76ef5efbf5b98ca3d3fcbaad465115e70:
>
>   riscv: fu540: dts: Correct reg size of otp and dmc nodes (2020-06-24 09:59:30 +0800)
>
> ----------------------------------------------------------------
> Bin Meng (2):
>       riscv: fu540: dts: Remove the unnecessary space in the cpu2_intc node
>       riscv: fu540: dts: Correct reg size of otp and dmc nodes
>
> Jagan Teki (6):
>       sifive: fu540: Add runtime boot mode detection
>       sifive: fu540: Add Booting from SPI
>       env: Enable SPI flash env for SiFive FU540
>       sifive: fu540: Mark the default env as SPI flash
>       sifive: fu540: Add boot flash script offset, size
>       sifive: fu540: Enable SF distro bootcmd

You missed my review comments for Jagan's series.
https://lists.denx.de/pipermail/u-boot/2020-June/417066.html

Please hold on.

>
> Sean Anderson (1):
>       riscv: sbi: Add newline to error message
>

Regards,
Bin

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
@ 2020-06-24  2:30 uboot at andestech.com
  2020-06-24  2:57 ` Bin Meng
  0 siblings, 1 reply; 53+ messages in thread
From: uboot at andestech.com @ 2020-06-24  2:30 UTC (permalink / raw)
  To: u-boot

Hi Tom,

Please pull some riscv updates:

- fu540: dts: Correct reg size of otp and dmc nodes
- sbi: Add newline to error message
- sifive/fu540: Enable SPI-NOR support

Thanks
Rick

https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/701223929


The following changes since commit 4ff63383e3497389e66cf70943a83bdb1810462a:

  Merge tag 'u-boot-imx-20200623' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2020-06-23 08:20:55 -0400)

are available in the Git repository at:

  git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to 2148d9c76ef5efbf5b98ca3d3fcbaad465115e70:

  riscv: fu540: dts: Correct reg size of otp and dmc nodes (2020-06-24 09:59:30 +0800)

----------------------------------------------------------------
Bin Meng (2):
      riscv: fu540: dts: Remove the unnecessary space in the cpu2_intc node
      riscv: fu540: dts: Correct reg size of otp and dmc nodes

Jagan Teki (6):
      sifive: fu540: Add runtime boot mode detection
      sifive: fu540: Add Booting from SPI
      env: Enable SPI flash env for SiFive FU540
      sifive: fu540: Mark the default env as SPI flash
      sifive: fu540: Add boot flash script offset, size
      sifive: fu540: Enable SF distro bootcmd

Sean Anderson (1):
      riscv: sbi: Add newline to error message

 arch/riscv/cpu/fu540/Kconfig                    | 15 +++++++++++++++
 arch/riscv/dts/fu540-c000-u-boot.dtsi           |  6 +++---
 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 12 ++++++++++++
 board/sifive/fu540/Kconfig                      |  1 +
 board/sifive/fu540/fu540.c                      | 25 +++++++++++++++++++------
 common/spl/spl_opensbi.c                        |  2 +-
 configs/sifive_fu540_defconfig                  |  4 ++++
 doc/board/sifive/fu540.rst                      | 41 +++++++++++++++++++++++++++++++++++++++++
 include/configs/sifive-fu540.h                  |  7 ++++++-
 9 files changed, 102 insertions(+), 11 deletions(-)

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2020-06-04  2:18 uboot at andestech.com
@ 2020-06-04 18:47 ` Tom Rini
  0 siblings, 0 replies; 53+ messages in thread
From: Tom Rini @ 2020-06-04 18:47 UTC (permalink / raw)
  To: u-boot

On Thu, Jun 04, 2020 at 10:18:07AM +0800, uboot at andestech.com wrote:

> Hi Tom,
> 
> Please pull some riscv updates:
> 
> - Fixes 7e249bc13aaf: ("riscv: Move all SMP related SBI calls to SBI_v01")
>    Move sbi_probe_extension() out of CONFIG_SBI_V01.
> - SiFive FU540 support SPL.
> 
> Thanks
> Rick
> 
> 
> https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/694099665
> 
> 
> The following changes since commit 0d8f35b58cc8458a5263b424896a386429ee49e5:
> 
>   Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spi (2020-06-03 12:27:51 -0400)
> 
> 	are available in the Git repository at:
> 
> 	  git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> 
> for you to fetch changes up to 0a94007e829876c7ebd49daebfaa90eea25801b8:
> 
>   riscv: sbi: Move sbi_probe_extension() out of CONFIG_SBI_V01 (2020-06-04 09:44:21 +0800)
> 

Applied to u-boot/master, thanks!

-- 
Tom
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^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
@ 2020-06-04  2:18 uboot at andestech.com
  2020-06-04 18:47 ` Tom Rini
  0 siblings, 1 reply; 53+ messages in thread
From: uboot at andestech.com @ 2020-06-04  2:18 UTC (permalink / raw)
  To: u-boot

Hi Tom,

Please pull some riscv updates:

- Fixes 7e249bc13aaf: ("riscv: Move all SMP related SBI calls to SBI_v01")
   Move sbi_probe_extension() out of CONFIG_SBI_V01.
- SiFive FU540 support SPL.

Thanks
Rick


https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/694099665


The following changes since commit 0d8f35b58cc8458a5263b424896a386429ee49e5:

  Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spi (2020-06-03 12:27:51 -0400)

	are available in the Git repository at:

	  git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to 0a94007e829876c7ebd49daebfaa90eea25801b8:

  riscv: sbi: Move sbi_probe_extension() out of CONFIG_SBI_V01 (2020-06-04 09:44:21 +0800)

----------------------------------------------------------------
Bin Meng (2):
      riscv: sbi: Remove sbi_spec_version
      riscv: sbi: Move sbi_probe_extension() out of CONFIG_SBI_V01

Jagan Teki (2):
      sifive: fu540: Add sample SD gpt partition layout
      sifive: fu540: Add U-Boot proper sector start

Pragnesh Patel (17):
      misc: add driver for the SiFive otp controller
      riscv: sifive: fu540: Use OTP DM driver for serial environment variable
      riscv: Add _image_binary_end for SPL
      lib: Makefile: build crc7.c when CONFIG_MMC_SPI
      riscv: sifive: dts: fu540: Add board -u-boot.dtsi files
      sifive: fu540: add ddr driver
	    sifive: dts: fu540: Add DDR controller and phy register settings
	    riscv: sifive: dts: fu540: add U-Boot dmc node
	    clk: sifive: fu540-prci: Add clock enable and disable ops
	    clk: sifive: fu540-prci: Add ddr clock initialization
	    clk: sifive: fu540-prci: Release ethernet clock reset
	    riscv: sifive: dts: fu540: set ethernet clock rate
	    riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux
	    riscv: cpu: fu540: Add support for cpu fu540
	    riscv: sifive: fu540: add SPL configuration
	    configs: fu540: Add config options for U-Boot SPL
	    doc: sifive: fu540: Add description for OpenSBI generic platform

arch/riscv/Kconfig                                 |    1 +
arch/riscv/cpu/fu540/Kconfig                       |   15 ++
arch/riscv/cpu/fu540/Makefile                      |   11 ++
arch/riscv/cpu/fu540/cpu.c                         |   22 +++
arch/riscv/cpu/fu540/dram.c                        |   38 +++++
arch/riscv/cpu/fu540/spl.c                         |   23 +++
arch/riscv/cpu/u-boot-spl.lds                      |    1 +
arch/riscv/dts/fu540-c000-u-boot.dtsi              |   89 +++++++++++
arch/riscv/dts/fu540-c000.dtsi                     |   37 ++++-
arch/riscv/dts/fu540-hifive-unleashed-a00-ddr.dtsi | 1489 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi    |   22 +++
arch/riscv/dts/hifive-unleashed-a00.dts            |    9 ++
arch/riscv/include/asm/arch-fu540/clk.h            |   14 ++
arch/riscv/include/asm/arch-fu540/gpio.h           |   38 +++++
arch/riscv/include/asm/arch-fu540/spl.h            |   14 ++
arch/riscv/include/asm/sbi.h                       |    2 -
arch/riscv/lib/sbi.c                               |   40 +++--
board/sifive/fu540/Kconfig                         |   18 ++-
board/sifive/fu540/Makefile                        |    4 +
board/sifive/fu540/fu540.c                         |  134 ++++++++--------
board/sifive/fu540/spl.c                           |   74 +++++++++
common/spl/Kconfig                                 |    3 +-
configs/sifive_fu540_defconfig                     |    8 +
doc/board/sifive/fu540.rst                         |  135 ++++++++++++++--
drivers/clk/sifive/fu540-prci.c                    |  177 ++++++++++++++++++---
drivers/misc/Kconfig                               |    7 +
drivers/misc/Makefile                              |    1 +
drivers/misc/sifive-otp.c                          |  275 +++++++++++++++++++++++++++++++++
drivers/ram/Kconfig                                |    1 +
drivers/ram/Makefile                               |    2 +
drivers/ram/sifive/Kconfig                         |   13 ++
drivers/ram/sifive/Makefile                        |    6 +
drivers/ram/sifive/fu540_ddr.c                     |  410 +++++++++++++++++++++++++++++++++++++++++++++++++
include/configs/sifive-fu540.h                     |   31 ++++
lib/Makefile                                       |    2 +-
35 files changed, 3037 insertions(+), 129 deletions(-)
create mode 100644 arch/riscv/cpu/fu540/Kconfig
create mode 100644 arch/riscv/cpu/fu540/Makefile
create mode 100644 arch/riscv/cpu/fu540/cpu.c
create mode 100644 arch/riscv/cpu/fu540/dram.c
create mode 100644 arch/riscv/cpu/fu540/spl.c
create mode 100644 arch/riscv/dts/fu540-c000-u-boot.dtsi
create mode 100644 arch/riscv/dts/fu540-hifive-unleashed-a00-ddr.dtsi
create mode 100644 arch/riscv/include/asm/arch-fu540/clk.h
create mode 100644 arch/riscv/include/asm/arch-fu540/gpio.h
create mode 100644 arch/riscv/include/asm/arch-fu540/spl.h
create mode 100644 board/sifive/fu540/spl.c
create mode 100644 drivers/misc/sifive-otp.c
create mode 100644 drivers/ram/sifive/Kconfig
create mode 100644 drivers/ram/sifive/Makefile
create mode 100644 drivers/ram/sifive/fu540_ddr.c

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2020-05-26  8:31 uboot at andestech.com
@ 2020-05-26 19:55 ` Tom Rini
  0 siblings, 0 replies; 53+ messages in thread
From: Tom Rini @ 2020-05-26 19:55 UTC (permalink / raw)
  To: u-boot

On Tue, May 26, 2020 at 04:31:43PM +0800, uboot at andestech.com wrote:

> Hi Tom,
> 
> Please pull some riscv updates:
> 
> - sifive: fix palmer's email address.
> - Move all SMP related SBI calls to SBI_v01.
> 
> Thanks
> Rick
> 
> 
> The following changes since commit 8c48bb21bd6a1778d1f299de30ff62c07929702b:
> 
>   Prepare v2020.07-rc3 (2020-05-25 20:34:01 -0400)
> 
> are available in the Git repository at:
> 
>   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> 
> for you to fetch changes up to 4ef196ce20fc832a412e8fedf51f2f20b3bd6e62:
> 
>   sifive: fix palmer's email address (2020-05-26 15:50:15 +0800)
> 

Applied to u-boot/master, thanks!


-- 
Tom
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* [U-Boot] Pull request: u-boot-riscv/master
@ 2020-05-26  8:31 uboot at andestech.com
  2020-05-26 19:55 ` Tom Rini
  0 siblings, 1 reply; 53+ messages in thread
From: uboot at andestech.com @ 2020-05-26  8:31 UTC (permalink / raw)
  To: u-boot

Hi Tom,

Please pull some riscv updates:

- sifive: fix palmer's email address.
- Move all SMP related SBI calls to SBI_v01.

Thanks
Rick


The following changes since commit 8c48bb21bd6a1778d1f299de30ff62c07929702b:

  Prepare v2020.07-rc3 (2020-05-25 20:34:01 -0400)

are available in the Git repository at:

  git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to 4ef196ce20fc832a412e8fedf51f2f20b3bd6e62:

  sifive: fix palmer's email address (2020-05-26 15:50:15 +0800)

----------------------------------------------------------------
Atish Patra (1):
      riscv: Move all SMP related SBI calls to SBI_v01

Pragnesh Patel (1):
      sifive: fix palmer's email address

 arch/riscv/include/asm/sbi.h   |  5 ++---
 arch/riscv/lib/sbi.c           | 37 ++++++++++++++++++-------------------
 board/sifive/fu540/MAINTAINERS |  2 +-
 3 files changed, 21 insertions(+), 23 deletions(-)

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2020-04-23  8:25 uboot at andestech.com
@ 2020-04-23 20:50 ` Tom Rini
  0 siblings, 0 replies; 53+ messages in thread
From: Tom Rini @ 2020-04-23 20:50 UTC (permalink / raw)
  To: u-boot

On Thu, Apr 23, 2020 at 04:25:55PM +0800, uboot at andestech.com wrote:

> Hi Tom,
> 
> Please pull some riscv updates:
> 
> - Adds few DT related fixes required for Linux EFI stub to work on RISC-V.
> - Makes SBI v0.2 the default SBI version to work with OpenSBI v0.7.
> - Revert "riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL"
> - Remove unnecessary CONFIG_IS_ENABLED().
> 
> https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/678432471
> 
> Thanks
> Rick
> 
> 
> The following changes since commit caad316b3165615f1a4848901811a4a084444c9d:
> 
>   Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell (2020-04-22 13:00:21 -0400)
> 
> are available in the Git repository at:
> 
>   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> 
> for you to fetch changes up to 177c53fe6c64d8656f5a647116a97047202c5455:
> 
>   riscv: Move all fdt fixups together (2020-04-23 10:14:16 +0800)
> 

Applied to u-boot/master, thanks!


-- 
Tom
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* [U-Boot] Pull request: u-boot-riscv/master
@ 2020-04-23  8:25 uboot at andestech.com
  2020-04-23 20:50 ` Tom Rini
  0 siblings, 1 reply; 53+ messages in thread
From: uboot at andestech.com @ 2020-04-23  8:25 UTC (permalink / raw)
  To: u-boot

Hi Tom,

Please pull some riscv updates:

- Adds few DT related fixes required for Linux EFI stub to work on RISC-V.
- Makes SBI v0.2 the default SBI version to work with OpenSBI v0.7.
- Revert "riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL"
- Remove unnecessary CONFIG_IS_ENABLED().

https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/678432471

Thanks
Rick


The following changes since commit caad316b3165615f1a4848901811a4a084444c9d:

  Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell (2020-04-22 13:00:21 -0400)

are available in the Git repository at:

  git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to 177c53fe6c64d8656f5a647116a97047202c5455:

  riscv: Move all fdt fixups together (2020-04-23 10:14:16 +0800)

----------------------------------------------------------------
Atish Patra (6):
      riscv: Add boot hartid to device tree
      fdtdec: Fix boundary check
      riscv: Provide a mechanism to fix DT for reserved memory
      riscv: Setup reserved-memory node for FU540
      riscv: Copy the reserved-memory nodes to final DT
      riscv: Move all fdt fixups together

Bin Meng (6):
      riscv: qemu: Remove the simple-bus driver for the SoC node
      riscv: Merge unnecessary SMP ifdefs in start.S
      riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL
      riscv: Add SMP Kconfig option dependency for U-Boot proper
      riscv: Add Kconfig option for SBI v0.2
      riscv: Make SBI v0.2 the default SBI version

Lukas Auer (1):
      Revert "riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL"

Pragnesh Patel (1):
      riscv: ax25: cache: Remove SPL_RISCV_MMODE config check

 arch/riscv/Kconfig                      |  34 +++++++++++++++++++++++--
 arch/riscv/cpu/ax25/cache.c             |  16 ++++++------
 arch/riscv/cpu/generic/cpu.c            |  14 -----------
 arch/riscv/cpu/start.S                  |  19 ++++++--------
 arch/riscv/include/asm/global_data.h    |   3 ++-
 arch/riscv/include/asm/u-boot-riscv.h   |   2 ++
 arch/riscv/lib/Makefile                 |   3 ++-
 arch/riscv/lib/asm-offsets.c            |   1 +
 arch/riscv/lib/bootm.c                  |   5 ----
 arch/riscv/lib/fdt_fixup.c              | 150 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/riscv/lib/spl.c                    |   2 +-
 board/emulation/qemu-riscv/Kconfig      |   1 -
 board/emulation/qemu-riscv/qemu-riscv.c |  39 -----------------------------
 common/spl/spl_opensbi.c                |   2 +-
 configs/sifive_fu540_defconfig          |   1 +
 doc/board/emulation/qemu-riscv.rst      |   2 +-
 lib/fdtdec.c                            |   3 ++-
 17 files changed, 211 insertions(+), 86 deletions(-)
 create mode 100644 arch/riscv/lib/fdt_fixup.c

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2020-03-17  8:03 uboot at andestech.com
@ 2020-03-18 13:56 ` Tom Rini
  0 siblings, 0 replies; 53+ messages in thread
From: Tom Rini @ 2020-03-18 13:56 UTC (permalink / raw)
  To: u-boot

On Tue, Mar 17, 2020 at 04:03:57PM +0800, uboot at andestech.com wrote:

> Hi Tom,
> 
> Please pull some riscv updates:
> 
> - Fix sbi_remote_sfence_vma{,_asid}.
> - Avoid calling sbi_clear_ipi().
> - Add new SBI v0.2 extensions support.
> 
> https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/663341855
> 
> Thanks
> Rick
> 
> 
> The following changes since commit a4df9d8ab848ea4ff10b247ae435b0a14bbbd066:
> 
>   Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell (2020-03-16 12:33:24 -0400)
> 
> are available in the Git repository at:
> 
>   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> 
> for you to fetch changes up to 5bde2152d42515f7af46d210d7edf14e3b10d5f5:
> 
>   riscv: Implement new SBI v0.2 extensions (2020-03-17 11:29:54 +0800)
> 

Applied to u-boot/master, thanks!


-- 
Tom
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* [U-Boot] Pull request: u-boot-riscv/master
@ 2020-03-17  8:03 uboot at andestech.com
  2020-03-18 13:56 ` Tom Rini
  0 siblings, 1 reply; 53+ messages in thread
From: uboot at andestech.com @ 2020-03-17  8:03 UTC (permalink / raw)
  To: u-boot

Hi Tom,

Please pull some riscv updates:

- Fix sbi_remote_sfence_vma{,_asid}.
- Avoid calling sbi_clear_ipi().
- Add new SBI v0.2 extensions support.

https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/663341855

Thanks
Rick


The following changes since commit a4df9d8ab848ea4ff10b247ae435b0a14bbbd066:

  Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell (2020-03-16 12:33:24 -0400)

are available in the Git repository at:

  git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to 5bde2152d42515f7af46d210d7edf14e3b10d5f5:

  riscv: Implement new SBI v0.2 extensions (2020-03-17 11:29:54 +0800)

----------------------------------------------------------------
Bin Meng (7):
      riscv: Fix sbi_remote_sfence_vma{,_asid}
      riscv: Avoid calling sbi_clear_ipi()
      riscv: Mark existing SBI as v0.1 SBI
      riscv: Add basic support for SBI v0.2
      riscv: Add SBI v0.2 extension definitions
      riscv: Introduce a new config for SBI v0.1
      riscv: Implement new SBI v0.2 extensions

 arch/riscv/Kconfig           |  13 +++++++++
 arch/riscv/include/asm/sbi.h | 163 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------------------------------------
 arch/riscv/lib/Makefile      |   1 +
 arch/riscv/lib/sbi.c         | 187 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/riscv/lib/sbi_ipi.c     |   3 +-
 5 files changed, 299 insertions(+), 68 deletions(-)
 create mode 100644 arch/riscv/lib/sbi.c

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2020-02-10  7:29 uboot at andestech.com
@ 2020-02-10 13:09 ` Tom Rini
  0 siblings, 0 replies; 53+ messages in thread
From: Tom Rini @ 2020-02-10 13:09 UTC (permalink / raw)
  To: u-boot

On Mon, Feb 10, 2020 at 03:29:56PM +0800, uboot at andestech.com wrote:

> Hi Tom,
> 
> Please pull some riscv updates:
> 
> - Fix ax25-ae350.rst document.
> - Refine RISC-V linker script and start.S.
> - Add option to print more information on exception.
> 
> https://travis-ci.org/rickchen36/u-boot-riscv/builds/646697243
> 
> Thanks
> Rick
> 
> 
> The following changes since commit e1dff2d69e5a21a61c3eb28e5d230a6d48749b6c:
> 
>   Merge branch '2020-02-07-master-imports' (2020-02-07 19:04:23 -0500)
> 
> are available in the Git repository at:
> 
>   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> 
> for you to fetch changes up to 404339759ef5e0bcd4fa7768d1148b1ace2d2bb6:
> 
>   riscv: Remove unnecessary instruction (2020-02-10 14:51:52 +0800)
> 

Applied to u-boot/master, thanks!


-- 
Tom
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* [U-Boot] Pull request: u-boot-riscv/master
@ 2020-02-10  7:29 uboot at andestech.com
  2020-02-10 13:09 ` Tom Rini
  0 siblings, 1 reply; 53+ messages in thread
From: uboot at andestech.com @ 2020-02-10  7:29 UTC (permalink / raw)
  To: u-boot

Hi Tom,

Please pull some riscv updates:

- Fix ax25-ae350.rst document.
- Refine RISC-V linker script and start.S.
- Add option to print more information on exception.

https://travis-ci.org/rickchen36/u-boot-riscv/builds/646697243

Thanks
Rick


The following changes since commit e1dff2d69e5a21a61c3eb28e5d230a6d48749b6c:

  Merge branch '2020-02-07-master-imports' (2020-02-07 19:04:23 -0500)

are available in the Git repository at:

  git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to 404339759ef5e0bcd4fa7768d1148b1ace2d2bb6:

  riscv: Remove unnecessary instruction (2020-02-10 14:51:52 +0800)

----------------------------------------------------------------
Heinrich Schuchardt (1):
      doc: fix AX25-AE350 RISC-V documentation

Jagan Teki (1):
      doc: fix opensbi build steps for AX25-AE350

Sean Anderson (3):
      riscv: Fix breakage caused by linker relaxation
      riscv: Add option to print registers on exception
      riscv: Remove unnecessary instruction

 arch/riscv/Kconfig                 |   3 +
 arch/riscv/cpu/mtrap.S             |   3 +-
 arch/riscv/cpu/start.S             |   5 +-
 arch/riscv/cpu/u-boot.lds          |   1 -
 arch/riscv/lib/interrupts.c        |  50 +++++++++++++----
 doc/board/AndesTech/ax25-ae350.rst | 343 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++---------------------------------------------------------
 6 files changed, 219 insertions(+), 186 deletions(-)

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2019-12-10  1:05 uboot at andestech.com
@ 2019-12-10  4:01 ` Tom Rini
  0 siblings, 0 replies; 53+ messages in thread
From: Tom Rini @ 2019-12-10  4:01 UTC (permalink / raw)
  To: u-boot

On Tue, Dec 10, 2019 at 09:05:59AM +0800, uboot at andestech.com wrote:

> Hi Tom,
> 
> Please pull some riscv updates:
> 
> - Increase stack size to avoid a stack overflow during distro boot.
> - Add hifive-unleashed-a00.dts for SIFIVE FU540.
> - Add OF_SEPARATE support for SIFIVE FU540.
> - Add SPL support for Andes AX25 AE350.
> - Improve U-Boot SPL / OpenSBI smp boot flow for RISC-V.
> 
> https://travis-ci.org/rickchen36/u-boot-riscv/builds/622462488
> 
> Thanks
> Rick
> 
> 
> The following changes since commit 0c5c3f293554614416a188d16a8c05e0a6c5bfbb:
> 
>   arm: -march=armv5t for ARM11 (2019-12-09 10:36:00 -0500)
> 
> are available in the Git repository at:
> 
>   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> 
> for you to fetch changes up to 0e1233ce9069a87a84a4385de456665d2bc9229d:
> 
>   spl: opensbi: wait for ack from secondary harts before entering OpenSBI (2019-12-10 08:23:10 +0800)
> 

Applied to u-boot/master, thanks!


-- 
Tom
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* [U-Boot] Pull request: u-boot-riscv/master
@ 2019-12-10  1:05 uboot at andestech.com
  2019-12-10  4:01 ` Tom Rini
  0 siblings, 1 reply; 53+ messages in thread
From: uboot at andestech.com @ 2019-12-10  1:05 UTC (permalink / raw)
  To: u-boot

Hi Tom,

Please pull some riscv updates:

- Increase stack size to avoid a stack overflow during distro boot.
- Add hifive-unleashed-a00.dts for SIFIVE FU540.
- Add OF_SEPARATE support for SIFIVE FU540.
- Add SPL support for Andes AX25 AE350.
- Improve U-Boot SPL / OpenSBI smp boot flow for RISC-V.

https://travis-ci.org/rickchen36/u-boot-riscv/builds/622462488

Thanks
Rick


The following changes since commit 0c5c3f293554614416a188d16a8c05e0a6c5bfbb:

  arm: -march=armv5t for ARM11 (2019-12-09 10:36:00 -0500)

are available in the Git repository at:

  git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to 0e1233ce9069a87a84a4385de456665d2bc9229d:

  spl: opensbi: wait for ack from secondary harts before entering OpenSBI (2019-12-10 08:23:10 +0800)

----------------------------------------------------------------
Jagan Teki (1):
      riscv: dts: Add hifive-unleashed-a00 dts from Linux

Lukas Auer (5):
      riscv: increase stack size to avoid a stack overflow during distro boot
      spl: opensbi: specify main hart as preferred boot hart
      riscv: add functions for reading the IPI status
      riscv: add option to wait for ack from secondary harts in smp functions
      spl: opensbi: wait for ack from secondary harts before entering OpenSBI

Rick Chen (11):
      Use dts support from U-Boot via OF_SEPARATE instead of depending from opensbi.
      riscv: ax25: add SPL support
      riscv: ax25-ae350: add SPL configuration
      riscv: ax25-ae350: Use generic memory size setup
      riscv: andes_plic: Fix some wrong configurations
      riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL
      spl: cache: Allow cache drivers in SPL
      riscv: Fix clear bss loop in the start-up code
      riscv: dts: Support four cores SMP
      riscv: dts: Add #address-cells and #size-cells in nor node
      doc: update AX25-AE350 RISC-V documentation

 arch/riscv/Kconfig                      |   2 +-
 arch/riscv/cpu/ax25/Kconfig             |   4 ++-
 arch/riscv/cpu/ax25/cache.c             |  60 ++++++++++++++++++++++++++++++++++-----------
 arch/riscv/cpu/start.S                  |   6 +++--
 arch/riscv/cpu/u-boot-spl.lds           |   2 +-
 arch/riscv/cpu/u-boot.lds               |   2 +-
 arch/riscv/dts/Makefile                 |   1 +
 arch/riscv/dts/ae350_32.dts             |  61 +++++++++++++++++++++++++++++++++++++++++++---
 arch/riscv/dts/ae350_64.dts             |  61 +++++++++++++++++++++++++++++++++++++++++++---
 arch/riscv/dts/fu540-c000.dtsi          | 251 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/riscv/dts/hifive-unleashed-a00.dts |  96 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/riscv/include/asm/smp.h            |   3 ++-
 arch/riscv/lib/andes_plic.c             |  22 ++++++++++++++---
 arch/riscv/lib/bootm.c                  |   2 +-
 arch/riscv/lib/sbi_ipi.c                |  11 +++++++++
 arch/riscv/lib/sifive_clint.c           |   9 +++++++
 arch/riscv/lib/smp.c                    |  43 ++++++++++++++++++++++++++-------
 arch/riscv/lib/spl.c                    |   2 +-
 board/AndesTech/ax25-ae350/Kconfig      |   9 +++++++
 board/AndesTech/ax25-ae350/MAINTAINERS  |   4 +++
 board/AndesTech/ax25-ae350/ax25-ae350.c |  48 +++++++++++++++++++++---------------
 common/spl/Kconfig                      |   7 ++++++
 common/spl/spl_opensbi.c                |  13 +++++++++-
 configs/ae350_rv32_spl_defconfig        |  38 +++++++++++++++++++++++++++++
 configs/ae350_rv32_spl_xip_defconfig    |  40 ++++++++++++++++++++++++++++++
 configs/ae350_rv64_spl_defconfig        |  39 ++++++++++++++++++++++++++++++
 configs/ae350_rv64_spl_xip_defconfig    |  41 +++++++++++++++++++++++++++++++
 configs/sifive_fu540_defconfig          |   3 ++-
 doc/board/AndesTech/ax25-ae350.rst      | 209 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++---
 doc/board/sifive/fu540.rst              |   5 +---
 drivers/Makefile                        |   1 +
 include/configs/ax25-ae350.h            |  17 +++++++++++++
 include/opensbi.h                       |  18 +++++++++++++-
 33 files changed, 1057 insertions(+), 73 deletions(-)
 create mode 100644 arch/riscv/dts/fu540-c000.dtsi
 create mode 100644 arch/riscv/dts/hifive-unleashed-a00.dts
 create mode 100644 configs/ae350_rv32_spl_defconfig
 create mode 100644 configs/ae350_rv32_spl_xip_defconfig
 create mode 100644 configs/ae350_rv64_spl_defconfig
 create mode 100644 configs/ae350_rv64_spl_xip_defconfig

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2019-10-18  7:00 uboot at andestech.com
@ 2019-10-19 14:24 ` Tom Rini
  0 siblings, 0 replies; 53+ messages in thread
From: Tom Rini @ 2019-10-19 14:24 UTC (permalink / raw)
  To: u-boot

On Fri, Oct 18, 2019 at 03:00:07PM +0800, uboot at andestech.com wrote:

> Hi Tom,
> 
> Please pull some riscv updates:
> 
> - Support sifive DM based gpio driver for FU540-SoC.
> - Align boot image header with Linux v5.3
> 
> https://travis-ci.org/rickchen36/u-boot-riscv/builds/599424917
> 
> Thanks
> Rick
> 
> 
> The following changes since commit a2fce50455c9831f36765e5813b0b5e98f55d70b:
> 
>   Merge tag 'for-v2020.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-ubi (2019-10-17 07:26:16 -0400)
> 
> are available in the Git repository at:
> 
>   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> 
> for you to fetch changes up to 70d64a4c7646aa51c0334618ccb9af0132d9d834:
> 
>   RISC-V: Align boot image header with Linux (2019-10-18 09:04:19 +0800)
> 

Applied to u-boot/master, thanks!


-- 
Tom
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* [U-Boot]  Pull request: u-boot-riscv/master
@ 2019-10-18  7:00 uboot at andestech.com
  2019-10-19 14:24 ` Tom Rini
  0 siblings, 1 reply; 53+ messages in thread
From: uboot at andestech.com @ 2019-10-18  7:00 UTC (permalink / raw)
  To: u-boot

Hi Tom,

Please pull some riscv updates:

- Support sifive DM based gpio driver for FU540-SoC.
- Align boot image header with Linux v5.3

https://travis-ci.org/rickchen36/u-boot-riscv/builds/599424917

Thanks
Rick


The following changes since commit a2fce50455c9831f36765e5813b0b5e98f55d70b:

  Merge tag 'for-v2020.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-ubi (2019-10-17 07:26:16 -0400)

are available in the Git repository at:

  git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to 70d64a4c7646aa51c0334618ccb9af0132d9d834:

  RISC-V: Align boot image header with Linux (2019-10-18 09:04:19 +0800)

----------------------------------------------------------------
Atish Patra (1):
      RISC-V: Align boot image header with Linux

Sagar Shrikant Kadam (2):
      gpio: sifive: add support for DM based gpio driver for FU540-SoC
      configs: fu540: enable gpio driver

 arch/riscv/include/asm/arch-generic/gpio.h |  35 +++++++++++++++++++++
 arch/riscv/include/asm/gpio.h              |   6 ++++
 arch/riscv/lib/image.c                     |  11 ++++---
 board/sifive/fu540/Kconfig                 |   3 ++
 drivers/gpio/Kconfig                       |   7 +++++
 drivers/gpio/Makefile                      |   1 +
 drivers/gpio/sifive-gpio.c                 | 177 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 7 files changed, 235 insertions(+), 5 deletions(-)
 create mode 100644 arch/riscv/include/asm/arch-generic/gpio.h
 create mode 100644 arch/riscv/include/asm/gpio.h
 create mode 100644 drivers/gpio/sifive-gpio.c

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2019-09-03  2:15 uboot at andestech.com
@ 2019-09-04  0:58 ` Tom Rini
  0 siblings, 0 replies; 53+ messages in thread
From: Tom Rini @ 2019-09-04  0:58 UTC (permalink / raw)
  To: u-boot

On Tue, Sep 03, 2019 at 10:15:42AM +0800, uboot at andestech.com wrote:

> Hi Tom,
> 
> Please pull some riscv updates:
> 
> - Skip unavailable hart in the get_count().
> - fu540 set serial env from otp.
> - fu540 add mmc0 as a boot target device.
> - Update fix_rela_dyn and add absolute reloc addend.
> - Andestech PLIC driver will skip unavailable hart.
> - Support Andestech V5L2 cache driver.
> 
> https://travis-ci.org/rickchen36/u-boot-riscv/builds/579707002
> 
> Thanks
> Rick
> 
> 
> The following changes since commit d22c8be964a870f59d2fdab6c67cefa0c4799364:
> 
>   Merge branch 'master' of git://git.denx.de/u-boot-sh (2019-09-01 13:33:12 -0400)
> 
> are available in the Git repository at:
> 
>   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> 
> for you to fetch changes up to 61ce84b2cf1a6672c8e402ce8174554b25629692:
> 
>   riscv: cache: use CCTL to flush d-cache (2019-09-03 09:31:03 +0800)
> 

Applied to u-boot/master, thanks!


-- 
Tom
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* [U-Boot]  Pull request: u-boot-riscv/master
@ 2019-09-03  2:15 uboot at andestech.com
  2019-09-04  0:58 ` Tom Rini
  0 siblings, 1 reply; 53+ messages in thread
From: uboot at andestech.com @ 2019-09-03  2:15 UTC (permalink / raw)
  To: u-boot

Hi Tom,

Please pull some riscv updates:

- Skip unavailable hart in the get_count().
- fu540 set serial env from otp.
- fu540 add mmc0 as a boot target device.
- Update fix_rela_dyn and add absolute reloc addend.
- Andestech PLIC driver will skip unavailable hart.
- Support Andestech V5L2 cache driver.

https://travis-ci.org/rickchen36/u-boot-riscv/builds/579707002

Thanks
Rick


The following changes since commit d22c8be964a870f59d2fdab6c67cefa0c4799364:

  Merge branch 'master' of git://git.denx.de/u-boot-sh (2019-09-01 13:33:12 -0400)

are available in the Git repository at:

  git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to 61ce84b2cf1a6672c8e402ce8174554b25629692:

  riscv: cache: use CCTL to flush d-cache (2019-09-03 09:31:03 +0800)

----------------------------------------------------------------
Alistair Francis (1):
      sifive-fu540: config: Add mmc0 as a boot target device

Bin Meng (1):
      riscv: cpu: Skip unavailable hart in the get_count() op

Marcus Comstedt (2):
      riscv: tools: Handle addend to absolute reloc in prelink-riscv
      riscv: update fix_rela_dyn

Rick Chen (9):
      riscv: andes_plic: init plic by scanning each cpu node
      dm: cache: Add enable and disable ops for cache uclass
      dm: cache: Add enable and disable ops for sandbox and test
      dm: cache: add v5l2 cache controller driver
      riscv: ae350: use the v5l2 driver to configure the cache
      riscv: ax25: add imply v5l2 cache controller
      riscv: cache: Flush L2 cache before jump to linux
      riscv: dts: move out AE350 L2 node from cpus node
      riscv: cache: use CCTL to flush d-cache

Sagar Shrikant Kadam (1):
      riscv: sifive: fu540: set serial environment variable from otp

 arch/riscv/cpu/ax25/Kconfig             |   1 +
 arch/riscv/cpu/ax25/cache.c             |  39 +++++++++++++++++------
 arch/riscv/cpu/start.S                  |  10 +++---
 arch/riscv/dts/ae350_32.dts             |  17 ++++++----
 arch/riscv/dts/ae350_64.dts             |  17 ++++++----
 arch/riscv/lib/andes_plic.c             |  36 ++++++++++++++-------
 board/AndesTech/ax25-ae350/ax25-ae350.c |   9 ++++++
 board/sifive/fu540/fu540.c              |  18 ++++++++---
 drivers/cache/Kconfig                   |   9 ++++++
 drivers/cache/Makefile                  |   1 +
 drivers/cache/cache-uclass.c            |  20 ++++++++++++
 drivers/cache/cache-v5l2.c              | 186 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/cache/sandbox_cache.c           |  13 ++++++++
 drivers/cpu/riscv_cpu.c                 |   4 +++
 include/cache.h                         |  31 +++++++++++++++++++
 include/configs/sifive-fu540.h          |   1 +
 test/dm/cache.c                         |   2 ++
 tools/prelink-riscv.inc                 |   8 +++--
 18 files changed, 379 insertions(+), 43 deletions(-)
 create mode 100644 drivers/cache/cache-v5l2.c

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2019-08-26  8:25 uboot at andestech.com
@ 2019-08-27  0:17 ` Tom Rini
  0 siblings, 0 replies; 53+ messages in thread
From: Tom Rini @ 2019-08-27  0:17 UTC (permalink / raw)
  To: u-boot

On Mon, Aug 26, 2019 at 04:25:31PM +0800, uboot at andestech.com wrote:

> Hi Tom,
> 
> Please pull some riscv updates:
> 
> - Support SPL and OpenSBI (FW_DYNAMIC firmware) boot.
> - Fix qemu kconfig build warning.
> 
> https://travis-ci.org/rickchen36/u-boot-riscv/builds/576608303
> 
> Thanks
> Rick
> 
> 
> The following changes since commit 50b4b80f597b9f59b98adbdbad691b1027bd501a:
> 
>   Merge tag 'u-boot-rockchip-20190823' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip (2019-08-24 08:33:27 -0400)
> 
> are available in the Git repository at:
> 
>   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> 
> for you to fetch changes up to 44016bc59870c8816fe2cd4721dc5ff11038dd98:
> 
>   riscv: qemu: Fix kconfig build warning (2019-08-26 16:09:02 +0800)
> 

Applied to u-boot/master, thanks!


-- 
Tom
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* [U-Boot]  Pull request: u-boot-riscv/master
@ 2019-08-26  8:25 uboot at andestech.com
  2019-08-27  0:17 ` Tom Rini
  0 siblings, 1 reply; 53+ messages in thread
From: uboot at andestech.com @ 2019-08-26  8:25 UTC (permalink / raw)
  To: u-boot

Hi Tom,

Please pull some riscv updates:

- Support SPL and OpenSBI (FW_DYNAMIC firmware) boot.
- Fix qemu kconfig build warning.

https://travis-ci.org/rickchen36/u-boot-riscv/builds/576608303

Thanks
Rick


The following changes since commit 50b4b80f597b9f59b98adbdbad691b1027bd501a:

  Merge tag 'u-boot-rockchip-20190823' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip (2019-08-24 08:33:27 -0400)

are available in the Git repository at:

  git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to 44016bc59870c8816fe2cd4721dc5ff11038dd98:

  riscv: qemu: Fix kconfig build warning (2019-08-26 16:09:02 +0800)

----------------------------------------------------------------
Bin Meng (1):
      riscv: qemu: Fix kconfig build warning

Lukas Auer (11):
      fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL
      Makefile: support building SPL FIT images without device trees
      spl: fit: use U-Boot device tree when FIT image has no device tree
      riscv: add run mode configuration for SPL
      spl: support booting via RISC-V OpenSBI
      riscv: add SPL support
      riscv: support SPL stack and global data relocation
      riscv: add a generic FIT generator script
      riscv: set default FIT generator script and build target for SPL builds
      riscv: qemu: add SPL configuration
      doc: update QEMU RISC-V documentation

 Kconfig                                 |   4 +++-
 Makefile                                |   8 ++++++--
 arch/Kconfig                            |   6 ++++++
 arch/riscv/Kconfig                      |  36 +++++++++++++++++++++++++++++++-----
 arch/riscv/cpu/ax25/Kconfig             |   6 +++---
 arch/riscv/cpu/cpu.c                    |   6 +++---
 arch/riscv/cpu/generic/Kconfig          |   5 ++++-
 arch/riscv/cpu/start.S                  |  62 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++----
 arch/riscv/cpu/u-boot-spl.lds           |  82 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/riscv/include/asm/encoding.h       |   2 +-
 arch/riscv/include/asm/spl.h            |  31 +++++++++++++++++++++++++++++++
 arch/riscv/lib/Makefile                 |   8 ++++++--
 arch/riscv/lib/mkimage_fit_opensbi.sh   | 100 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/riscv/lib/spl.c                    |  48 ++++++++++++++++++++++++++++++++++++++++++++++++
 board/emulation/qemu-riscv/Kconfig      |  11 +++++++++++
 board/emulation/qemu-riscv/MAINTAINERS  |   2 ++
 board/emulation/qemu-riscv/qemu-riscv.c |  17 +++++++++++++++++
 common/image.c                          |   1 +
 common/spl/Kconfig                      |  17 +++++++++++++++++
 common/spl/Makefile                     |   1 +
 common/spl/spl.c                        |   8 +++++++-
 common/spl/spl_fit.c                    |  37 ++++++++++++++++++++++++-------------
 common/spl/spl_opensbi.c                |  85 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 configs/qemu-riscv32_spl_defconfig      |  11 +++++++++++
 configs/qemu-riscv64_spl_defconfig      |  12 ++++++++++++
 doc/board/emulation/qemu-riscv.rst      |  60 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 include/configs/qemu-riscv.h            |  14 ++++++++++++++
 include/fdtdec.h                        |   2 +-
 include/image.h                         |   1 +
 include/opensbi.h                       |  40 ++++++++++++++++++++++++++++++++++++++++
 include/spl.h                           |   5 +++++
 lib/fdtdec.c                            |   6 ++----
 32 files changed, 692 insertions(+), 42 deletions(-)
 create mode 100644 arch/riscv/cpu/u-boot-spl.lds
 create mode 100644 arch/riscv/include/asm/spl.h
 create mode 100755 arch/riscv/lib/mkimage_fit_opensbi.sh
 create mode 100644 arch/riscv/lib/spl.c
 create mode 100644 common/spl/spl_opensbi.c
 create mode 100644 configs/qemu-riscv32_spl_defconfig
 create mode 100644 configs/qemu-riscv64_spl_defconfig
 create mode 100644 include/opensbi.h

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2019-08-20 21:11         ` Auer, Lukas
@ 2019-08-21  2:10           ` Rick Chen
  0 siblings, 0 replies; 53+ messages in thread
From: Rick Chen @ 2019-08-21  2:10 UTC (permalink / raw)
  To: u-boot

Hi Lukas

> Hi Rick,
>
> On Wed, 2019-08-14 at 20:15 +0000, Auer, Lukas wrote:
> > Hi Rick,
> >
> > On Wed, 2019-08-14 at 10:20 +0800, Rick Chen wrote:
> > > Hi Lukas
> > >
> > > > > From: Tom Rini [mailto:trini at konsulko.com]
> > > > > Sent: Wednesday, August 14, 2019 12:50 AM
> > > > > To: Open Source Project uboot
> > > > > Cc: u-boot at lists.denx.de; Rick Jian-Zhi Chen(陳建志)
> > > > > Subject: Re: [U-Boot] Pull request: u-boot-riscv/master
> > > > >
> > > > > On Mon, Aug 12, 2019 at 06:23:02PM +0800, uboot at andestech.com wrote:
> > > > >
> > > > > > Hi Tom,
> > > > > >
> > > > > > Please pull some riscv updates:
> > > > > >
> > > > > > - Fix sifive serial y-modem transfer.
> > > > > > - Access CSRs using CSR numbers.
> > > > > > - Update doc sifive-fu540
> > > > > > - Support big endian hosts and target.
> > > > > > - Support SPL and OpenSBI (FW_DYNAMIC firmware) boot.
> > > > > >
> > > > > > https://travis-ci.org/rickchen36/u-boot-riscv/builds/570682542
> > > > > >
> > > > > > Thanks
> > > > > > Rick
> > > > > >
> > > > > >
> > > > > > The following changes since commit
> > > > > feb5a02f869d5678190dfc915ef6c2781b4f7a6c:
> > > > > >   Merge branch 'master' of git://git.denx.de/u-boot-sh (2019-08-10
> > > > > > 17:57:58 -0400)
> > > > > >
> > > > > > are available in the Git repository at:
> > > > > >
> > > > > >   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> > > > > >
> > > > > > for you to fetch changes up to
> > > > > 30c150bae4e3a61f87a159579cd3784f4d64e79e:
> > > > > >   riscv: qemu: Fix kconfig build warning (2019-08-12 13:30:53 +0800)
> > > > > >
> > > > >
> > > > > There is some change in here that is reliably causing this job to fail, please
> > > > > investigate:
> > > > > https://gitlab.denx.de/u-boot/u-boot/-/jobs/5493
> > >
> > > Can you please check about this failure.
> > > I wonder it may cause from SPL relative patchs.
> > >
> >
> > I'll have a look. I am on vacation the rest of the week, so I will
> > check it out Sunday if I get the chance or early next week.
> >
>
> You are right, patch #2 of the SPL series caused this issue.
> Unfortunately Travis did not catch the problem, likely because the
> compiled device tree was still present from a previous build. I have
> sent the updated patch. Let me know if I should resend the entire
> series.

Thanks for solving this build fail issue.

But the [PATCH v3 10/11] riscv: qemu: add SPL configuration
seem to conflict with u-boot/master.

You shall rebase u-boot/master and send v5 again.
I will apply it ASAP.

Applying: fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL
Applying: Makefile: support building SPL FIT images without device trees
Applying: spl: fit: use U-Boot device tree when FIT image has no device tree
Applying: riscv: add run mode configuration for SPL
Applying: riscv: add SPL support
Applying: riscv: support SPL stack and global data relocation
Applying: riscv: add a generic FIT generator script
Applying: riscv: set default FIT generator script and build target for
SPL builds
Applying: riscv: qemu: add SPL configuration
error: patch failed: board/emulation/qemu-riscv/qemu-riscv.c:6
error: board/emulation/qemu-riscv/qemu-riscv.c: patch does not apply
Patch failed at 0009 riscv: qemu: add SPL configuration

Thanks,
Rick

>
> Thanks,
> Lukas

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2019-08-14 20:15       ` Auer, Lukas
@ 2019-08-20 21:11         ` Auer, Lukas
  2019-08-21  2:10           ` Rick Chen
  0 siblings, 1 reply; 53+ messages in thread
From: Auer, Lukas @ 2019-08-20 21:11 UTC (permalink / raw)
  To: u-boot

Hi Rick,

On Wed, 2019-08-14 at 20:15 +0000, Auer, Lukas wrote:
> Hi Rick,
> 
> On Wed, 2019-08-14 at 10:20 +0800, Rick Chen wrote:
> > Hi Lukas
> > 
> > > > From: Tom Rini [mailto:trini at konsulko.com]
> > > > Sent: Wednesday, August 14, 2019 12:50 AM
> > > > To: Open Source Project uboot
> > > > Cc: u-boot at lists.denx.de; Rick Jian-Zhi Chen(陳建志)
> > > > Subject: Re: [U-Boot] Pull request: u-boot-riscv/master
> > > > 
> > > > On Mon, Aug 12, 2019 at 06:23:02PM +0800, uboot at andestech.com wrote:
> > > > 
> > > > > Hi Tom,
> > > > > 
> > > > > Please pull some riscv updates:
> > > > > 
> > > > > - Fix sifive serial y-modem transfer.
> > > > > - Access CSRs using CSR numbers.
> > > > > - Update doc sifive-fu540
> > > > > - Support big endian hosts and target.
> > > > > - Support SPL and OpenSBI (FW_DYNAMIC firmware) boot.
> > > > > 
> > > > > https://travis-ci.org/rickchen36/u-boot-riscv/builds/570682542
> > > > > 
> > > > > Thanks
> > > > > Rick
> > > > > 
> > > > > 
> > > > > The following changes since commit
> > > > feb5a02f869d5678190dfc915ef6c2781b4f7a6c:
> > > > >   Merge branch 'master' of git://git.denx.de/u-boot-sh (2019-08-10
> > > > > 17:57:58 -0400)
> > > > > 
> > > > > are available in the Git repository at:
> > > > > 
> > > > >   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> > > > > 
> > > > > for you to fetch changes up to
> > > > 30c150bae4e3a61f87a159579cd3784f4d64e79e:
> > > > >   riscv: qemu: Fix kconfig build warning (2019-08-12 13:30:53 +0800)
> > > > > 
> > > > 
> > > > There is some change in here that is reliably causing this job to fail, please
> > > > investigate:
> > > > https://gitlab.denx.de/u-boot/u-boot/-/jobs/5493
> > 
> > Can you please check about this failure.
> > I wonder it may cause from SPL relative patchs.
> > 
> 
> I'll have a look. I am on vacation the rest of the week, so I will
> check it out Sunday if I get the chance or early next week.
> 

You are right, patch #2 of the SPL series caused this issue.
Unfortunately Travis did not catch the problem, likely because the
compiled device tree was still present from a previous build. I have
sent the updated patch. Let me know if I should resend the entire
series.

Thanks,
Lukas

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2019-08-16  5:19 uboot at andestech.com
@ 2019-08-17 17:47 ` Tom Rini
  0 siblings, 0 replies; 53+ messages in thread
From: Tom Rini @ 2019-08-17 17:47 UTC (permalink / raw)
  To: u-boot

On Fri, Aug 16, 2019 at 01:19:59PM +0800, uboot at andestech.com wrote:

> Hi Tom,
> 
> Please pull some riscv updates:
> 
> - Fix sifive serial y-modem transfer.
> - Access CSRs using CSR numbers.
> - Update doc sifive-fu540
> - Support big endian hosts and target.
> 
> https://travis-ci.org/rickchen36/u-boot-riscv/builds/572159567
> 
> Thanks
> Rick
> 
> 
> The following changes since commit df33f8646855e65b8e7232c7fd5739e1ae1eb58b:
> 
>   configs: Resync with savedefconfig (2019-08-14 08:11:27 -0400)
> 
> are available in the Git repository at:
> 
>   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> 
> for you to fetch changes up to 4539926a9c47638951f29f550f3a640e4c223032:
> 
>   riscv: tools: Add big endian target support to prelink-riscv (2019-08-15 13:42:28 +0800)
> 

Applied to u-boot/master, thanks!


-- 
Tom
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^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot]  Pull request: u-boot-riscv/master
@ 2019-08-16  5:19 uboot at andestech.com
  2019-08-17 17:47 ` Tom Rini
  0 siblings, 1 reply; 53+ messages in thread
From: uboot at andestech.com @ 2019-08-16  5:19 UTC (permalink / raw)
  To: u-boot

Hi Tom,

Please pull some riscv updates:

- Fix sifive serial y-modem transfer.
- Access CSRs using CSR numbers.
- Update doc sifive-fu540
- Support big endian hosts and target.

https://travis-ci.org/rickchen36/u-boot-riscv/builds/572159567

Thanks
Rick


The following changes since commit df33f8646855e65b8e7232c7fd5739e1ae1eb58b:

  configs: Resync with savedefconfig (2019-08-14 08:11:27 -0400)

are available in the Git repository at:

  git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to 4539926a9c47638951f29f550f3a640e4c223032:

  riscv: tools: Add big endian target support to prelink-riscv (2019-08-15 13:42:28 +0800)

----------------------------------------------------------------
Anup Patel (1):
      doc: sifive-fu540: Update README to explicitly load DTB for Linux

Bin Meng (2):
      riscv: Sync csr.h with Linux kernel v5.2
      riscv: Access CSRs using CSR numbers

Marcus Comstedt (2):
      riscv: tools: Fix prelink-riscv to work on big endian hosts
      riscv: tools: Add big endian target support to prelink-riscv

Sagar Shrikant Kadam (1):
      riscv : serial: use rx watermark to indicate rx data is present

 arch/riscv/cpu/cpu.c              |   9 ++-
 arch/riscv/cpu/start.S            |   3 +-
 arch/riscv/include/asm/asm.h      |  68 ++++++++++++++++++++
 arch/riscv/include/asm/csr.h      |  74 +++++++++++++++++-----
 arch/riscv/include/asm/encoding.h | 238 +--------------------------------------------------------------------
 doc/board/sifive/fu540.rst        | 396 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++---------------------------------------------------
 drivers/serial/serial_sifive.c    |  23 +++----
 tools/prelink-riscv.c             |  39 +++++++++---
 tools/prelink-riscv.inc           |  60 ++++++++++--------
 9 files changed, 426 insertions(+), 484 deletions(-)
 create mode 100644 arch/riscv/include/asm/asm.h

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2019-08-14  2:20     ` Rick Chen
@ 2019-08-14 20:15       ` Auer, Lukas
  2019-08-20 21:11         ` Auer, Lukas
  0 siblings, 1 reply; 53+ messages in thread
From: Auer, Lukas @ 2019-08-14 20:15 UTC (permalink / raw)
  To: u-boot

Hi Rick,

On Wed, 2019-08-14 at 10:20 +0800, Rick Chen wrote:
> Hi Lukas
> 
> > > From: Tom Rini [mailto:trini at konsulko.com]
> > > Sent: Wednesday, August 14, 2019 12:50 AM
> > > To: Open Source Project uboot
> > > Cc: u-boot at lists.denx.de; Rick Jian-Zhi Chen(陳建志)
> > > Subject: Re: [U-Boot] Pull request: u-boot-riscv/master
> > > 
> > > On Mon, Aug 12, 2019 at 06:23:02PM +0800, uboot at andestech.com wrote:
> > > 
> > > > Hi Tom,
> > > > 
> > > > Please pull some riscv updates:
> > > > 
> > > > - Fix sifive serial y-modem transfer.
> > > > - Access CSRs using CSR numbers.
> > > > - Update doc sifive-fu540
> > > > - Support big endian hosts and target.
> > > > - Support SPL and OpenSBI (FW_DYNAMIC firmware) boot.
> > > > 
> > > > https://travis-ci.org/rickchen36/u-boot-riscv/builds/570682542
> > > > 
> > > > Thanks
> > > > Rick
> > > > 
> > > > 
> > > > The following changes since commit
> > > feb5a02f869d5678190dfc915ef6c2781b4f7a6c:
> > > >   Merge branch 'master' of git://git.denx.de/u-boot-sh (2019-08-10
> > > > 17:57:58 -0400)
> > > > 
> > > > are available in the Git repository at:
> > > > 
> > > >   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> > > > 
> > > > for you to fetch changes up to
> > > 30c150bae4e3a61f87a159579cd3784f4d64e79e:
> > > >   riscv: qemu: Fix kconfig build warning (2019-08-12 13:30:53 +0800)
> > > > 
> > > 
> > > There is some change in here that is reliably causing this job to fail, please
> > > investigate:
> > > https://gitlab.denx.de/u-boot/u-boot/-/jobs/5493
> 
> Can you please check about this failure.
> I wonder it may cause from SPL relative patchs.
> 

I'll have a look. I am on vacation the rest of the week, so I will
check it out Sunday if I get the chance or early next week.

Thanks,
Lukas

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
       [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA40FF880@ATCPCS16.andestech.com>
@ 2019-08-14  2:20     ` Rick Chen
  2019-08-14 20:15       ` Auer, Lukas
  0 siblings, 1 reply; 53+ messages in thread
From: Rick Chen @ 2019-08-14  2:20 UTC (permalink / raw)
  To: u-boot

Hi Lukas

> > From: Tom Rini [mailto:trini at konsulko.com]
> > Sent: Wednesday, August 14, 2019 12:50 AM
> > To: Open Source Project uboot
> > Cc: u-boot at lists.denx.de; Rick Jian-Zhi Chen(陳建志)
> > Subject: Re: [U-Boot] Pull request: u-boot-riscv/master
> >
> > On Mon, Aug 12, 2019 at 06:23:02PM +0800, uboot at andestech.com wrote:
> >
> > > Hi Tom,
> > >
> > > Please pull some riscv updates:
> > >
> > > - Fix sifive serial y-modem transfer.
> > > - Access CSRs using CSR numbers.
> > > - Update doc sifive-fu540
> > > - Support big endian hosts and target.
> > > - Support SPL and OpenSBI (FW_DYNAMIC firmware) boot.
> > >
> > > https://travis-ci.org/rickchen36/u-boot-riscv/builds/570682542
> > >
> > > Thanks
> > > Rick
> > >
> > >
> > > The following changes since commit
> > feb5a02f869d5678190dfc915ef6c2781b4f7a6c:
> > >
> > >   Merge branch 'master' of git://git.denx.de/u-boot-sh (2019-08-10
> > > 17:57:58 -0400)
> > >
> > > are available in the Git repository at:
> > >
> > >   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> > >
> > > for you to fetch changes up to
> > 30c150bae4e3a61f87a159579cd3784f4d64e79e:
> > >
> > >   riscv: qemu: Fix kconfig build warning (2019-08-12 13:30:53 +0800)
> > >
> >
> > There is some change in here that is reliably causing this job to fail, please
> > investigate:
> > https://gitlab.denx.de/u-boot/u-boot/-/jobs/5493

Can you please check about this failure.
I wonder it may cause from SPL relative patchs.

Thanks
Rick

> >
> > --
> > Tom

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2019-08-12 10:23 uboot at andestech.com
@ 2019-08-13 16:50 ` Tom Rini
       [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA40FF880@ATCPCS16.andestech.com>
  0 siblings, 1 reply; 53+ messages in thread
From: Tom Rini @ 2019-08-13 16:50 UTC (permalink / raw)
  To: u-boot

On Mon, Aug 12, 2019 at 06:23:02PM +0800, uboot at andestech.com wrote:

> Hi Tom,
> 
> Please pull some riscv updates:
> 
> - Fix sifive serial y-modem transfer.
> - Access CSRs using CSR numbers.
> - Update doc sifive-fu540
> - Support big endian hosts and target.
> - Support SPL and OpenSBI (FW_DYNAMIC firmware) boot.
> 
> https://travis-ci.org/rickchen36/u-boot-riscv/builds/570682542
> 
> Thanks
> Rick
> 
> 
> The following changes since commit feb5a02f869d5678190dfc915ef6c2781b4f7a6c:
> 
>   Merge branch 'master' of git://git.denx.de/u-boot-sh (2019-08-10 17:57:58 -0400)
> 
> are available in the Git repository at:
> 
>   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> 
> for you to fetch changes up to 30c150bae4e3a61f87a159579cd3784f4d64e79e:
> 
>   riscv: qemu: Fix kconfig build warning (2019-08-12 13:30:53 +0800)
> 

There is some change in here that is reliably causing this job to fail,
please investigate:
https://gitlab.denx.de/u-boot/u-boot/-/jobs/5493

-- 
Tom
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^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot]  Pull request: u-boot-riscv/master
@ 2019-08-12 10:23 uboot at andestech.com
  2019-08-13 16:50 ` Tom Rini
  0 siblings, 1 reply; 53+ messages in thread
From: uboot at andestech.com @ 2019-08-12 10:23 UTC (permalink / raw)
  To: u-boot

Hi Tom,

Please pull some riscv updates:

- Fix sifive serial y-modem transfer.
- Access CSRs using CSR numbers.
- Update doc sifive-fu540
- Support big endian hosts and target.
- Support SPL and OpenSBI (FW_DYNAMIC firmware) boot.

https://travis-ci.org/rickchen36/u-boot-riscv/builds/570682542

Thanks
Rick


The following changes since commit feb5a02f869d5678190dfc915ef6c2781b4f7a6c:

  Merge branch 'master' of git://git.denx.de/u-boot-sh (2019-08-10 17:57:58 -0400)

are available in the Git repository at:

  git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to 30c150bae4e3a61f87a159579cd3784f4d64e79e:

  riscv: qemu: Fix kconfig build warning (2019-08-12 13:30:53 +0800)

----------------------------------------------------------------
Anup Patel (1):
      doc: sifive-fu540: Update README to explicitly load DTB for Linux

Bin Meng (3):
      riscv: Sync csr.h with Linux kernel v5.2
      riscv: Access CSRs using CSR numbers
      riscv: qemu: Fix kconfig build warning

Lukas Auer (10):
      fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL
      Makefile: support building SPL FIT images without device trees
      spl: fit: use U-Boot device tree when FIT image has no device tree
      riscv: add run mode configuration for SPL
      riscv: add SPL support
      riscv: support SPL stack and global data relocation
      riscv: add a generic FIT generator script
      riscv: set default FIT generator script and build target for SPL builds
      riscv: qemu: add SPL configuration
      doc: update QEMU RISC-V documentation

Marcus Comstedt (2):
      riscv: tools: Fix prelink-riscv to work on big endian hosts
      riscv: tools: Add big endian target support to prelink-riscv

Sagar Shrikant Kadam (1):
      riscv : serial: use rx watermark to indicate rx data is present

 Kconfig                                 |   4 +-
 Makefile                                |   8 ++-
 arch/Kconfig                            |   6 ++
 arch/riscv/Kconfig                      |  36 ++++++++--
 arch/riscv/cpu/ax25/Kconfig             |   6 +-
 arch/riscv/cpu/cpu.c                    |  15 ++---
 arch/riscv/cpu/generic/Kconfig          |   5 +-
 arch/riscv/cpu/start.S                  |  65 ++++++++++++++++--
 arch/riscv/cpu/u-boot-spl.lds           |  82 +++++++++++++++++++++++
 arch/riscv/include/asm/asm.h            |  68 +++++++++++++++++++
 arch/riscv/include/asm/csr.h            |  74 ++++++++++++++++-----
 arch/riscv/include/asm/encoding.h       | 240 +-----------------------------------------------------------------
 arch/riscv/include/asm/spl.h            |  31 +++++++++
 arch/riscv/lib/Makefile                 |   8 ++-
 arch/riscv/lib/mkimage_fit_opensbi.sh   | 100 ++++++++++++++++++++++++++++
 arch/riscv/lib/spl.c                    |  48 ++++++++++++++
 board/emulation/qemu-riscv/Kconfig      |  11 ++++
 board/emulation/qemu-riscv/MAINTAINERS  |   2 +
 board/emulation/qemu-riscv/qemu-riscv.c |  17 +++++
 common/spl/spl.c                        |   2 +-
 common/spl/spl_fit.c                    |  37 +++++++----
 configs/qemu-riscv32_spl_defconfig      |  11 ++++
 configs/qemu-riscv64_spl_defconfig      |  12 ++++
 doc/board/emulation/qemu-riscv.rst      |  60 ++++++++++++++++-
 doc/board/sifive/fu540.rst              | 396 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++------------------------------------------------
 drivers/serial/serial_sifive.c          |  23 ++-----
 include/configs/qemu-riscv.h            |  14 ++++
 include/fdtdec.h                        |   2 +-
 lib/fdtdec.c                            |   6 +-
 tools/prelink-riscv.c                   |  39 ++++++++---
 tools/prelink-riscv.inc                 |  60 +++++++++--------
 31 files changed, 962 insertions(+), 526 deletions(-)
 create mode 100644 arch/riscv/cpu/u-boot-spl.lds
 create mode 100644 arch/riscv/include/asm/asm.h
 create mode 100644 arch/riscv/include/asm/spl.h
 create mode 100755 arch/riscv/lib/mkimage_fit_opensbi.sh
 create mode 100644 arch/riscv/lib/spl.c
 create mode 100644 configs/qemu-riscv32_spl_defconfig
 create mode 100644 configs/qemu-riscv64_spl_defconfig

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2019-07-19  7:06 uboot at andestech.com
@ 2019-07-23 13:46 ` Tom Rini
  0 siblings, 0 replies; 53+ messages in thread
From: Tom Rini @ 2019-07-23 13:46 UTC (permalink / raw)
  To: u-boot

On Fri, Jul 19, 2019 at 03:06:24PM +0800, uboot at andestech.com wrote:

> Hi Tom,
> 
> Please pull some riscv updates:
> 
> - Update SiFive Unleashed clock driver.
> - Enables SiFive SPI driver and MMC SPI driver for SiFive Unleashed board
> 
> https://travis-ci.org/rickchen36/u-boot-riscv/builds/560423274
> 
> Thanks
> Rick
> 
> 
> The following changes since commit 0de815356474912ef5bef9a69f0327a5a93bb2c2:
> 
>   Merge branch '2019-07-17-master-imports' (2019-07-18 11:31:37 -0400)
> 
> are available in the Git repository at:
> 
>   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> 
> for you to fetch changes up to 8911a22aee1e2a176af93ebf502477f2df2fc912:
> 
>   doc: sifive-fu540: Update README for SiFive SPI and MMC SPI drivers (2019-07-19 14:25:06 +0800)
> 

Applied to u-boot/master, thanks!


-- 
Tom
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* [U-Boot]  Pull request: u-boot-riscv/master
@ 2019-07-19  7:06 uboot at andestech.com
  2019-07-23 13:46 ` Tom Rini
  0 siblings, 1 reply; 53+ messages in thread
From: uboot at andestech.com @ 2019-07-19  7:06 UTC (permalink / raw)
  To: u-boot

Hi Tom,

Please pull some riscv updates:

- Update SiFive Unleashed clock driver.
- Enables SiFive SPI driver and MMC SPI driver for SiFive Unleashed board

https://travis-ci.org/rickchen36/u-boot-riscv/builds/560423274

Thanks
Rick


The following changes since commit 0de815356474912ef5bef9a69f0327a5a93bb2c2:

  Merge branch '2019-07-17-master-imports' (2019-07-18 11:31:37 -0400)

are available in the Git repository at:

  git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to 8911a22aee1e2a176af93ebf502477f2df2fc912:

  doc: sifive-fu540: Update README for SiFive SPI and MMC SPI drivers (2019-07-19 14:25:06 +0800)

----------------------------------------------------------------
Anup Patel (8):
      clk: sifive: Factor-out PLL library as separate module
      clk: sifive: Sync-up WRPLL library with upstream Linux
      clk: sifive: Sync-up DT bindings header with upstream Linux
      clk: sifive: Sync-up main driver with upstream Linux
      clk: sifive: Drop GEMGXL clock driver
      riscv: sifive: fu540: Setup ethaddr env variable using OTP
      doc: sifive-fu540: Update README for steps to create FW_PAYLOAD
      doc: sifive-fu540: Update README for SiFive SPI and MMC SPI drivers

Bhargav Shah (1):
      riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers

 board/sifive/fu540/Kconfig                                            |   7 +-
 board/sifive/fu540/fu540.c                                            | 122 +++++++++++++++++++++++++++
 configs/sifive_fu540_defconfig                                        |   1 +
 doc/README.sifive-fu540                                               | 356 ++++++++++++++++++++++++++++++++++++-------------------------------------------
 drivers/clk/Kconfig                                                   |   1 +
 drivers/clk/Makefile                                                  |   1 +
 drivers/clk/analogbits/Kconfig                                        |   4 +
 drivers/clk/analogbits/Makefile                                       |   3 +
 drivers/clk/{sifive => analogbits}/wrpll-cln28hpc.c                   | 168 ++++++++++++++++---------------------
 drivers/clk/sifive/Kconfig                                            |  10 ---
 drivers/clk/sifive/Makefile                                           |   4 -
 drivers/clk/sifive/fu540-prci.c                                       | 123 ++++++++++++++++-----------
 drivers/clk/sifive/gemgxl-mgmt.c                                      |  60 --------------
 include/dt-bindings/clk/sifive-fu540-prci.h                           |  29 -------
 include/dt-bindings/clock/sifive-fu540-prci.h                         |  18 ++++
 {drivers/clk/sifive => include/linux/clk}/analogbits-wrpll-cln28hpc.h |  70 ++++++----------
 16 files changed, 487 insertions(+), 490 deletions(-)
 create mode 100644 drivers/clk/analogbits/Kconfig
 create mode 100644 drivers/clk/analogbits/Makefile
 rename drivers/clk/{sifive => analogbits}/wrpll-cln28hpc.c (69%)
 delete mode 100644 drivers/clk/sifive/gemgxl-mgmt.c
 delete mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h
 create mode 100644 include/dt-bindings/clock/sifive-fu540-prci.h
 rename {drivers/clk/sifive => include/linux/clk}/analogbits-wrpll-cln28hpc.h (52%)

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2019-06-05 10:27 uboot at andestech.com
@ 2019-06-05 14:24 ` Tom Rini
  0 siblings, 0 replies; 53+ messages in thread
From: Tom Rini @ 2019-06-05 14:24 UTC (permalink / raw)
  To: u-boot

On Wed, Jun 05, 2019 at 06:27:38PM +0800, uboot at andestech.com wrote:

> Hi Tom,
> 
> Please pull some riscv updates:
> 
> - Support Microchip MPFS Icicle board.
> - Enable e1000 and nvme support for qemu.
> - Enable PCI host ECAM generic driver for qemu.
> - Increase the environment size to 128kB for qemu.
> 
> https://travis-ci.org/rickchen36/u-boot-riscv/builds/541565696
> 
> Thanks
> Rick
> 
> 
> The following changes since commit 38c2a8a00132b4dcc6a0bb5baf5146b9eb9eb2d2:
> 
>   Merge tag 'efi-2019-07-rc4' of git://git.denx.de/u-boot-efi (2019-06-02 18:19:45 -0400)
> 
> are available in the Git repository at:
> 
>   git://git.denx.de/u-boot-riscv.git
> 
> for you to fetch changes up to 39494822e3a639c8b5d60538d1dcae17bcf3c5f6:
> 
>   riscv: Add Microchip MPFS Icicle board support (2019-06-05 13:19:24 +0800)
> 

Applied to u-boot/master, thanks!


-- 
Tom
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* [U-Boot]  Pull request: u-boot-riscv/master
@ 2019-06-05 10:27 uboot at andestech.com
  2019-06-05 14:24 ` Tom Rini
  0 siblings, 1 reply; 53+ messages in thread
From: uboot at andestech.com @ 2019-06-05 10:27 UTC (permalink / raw)
  To: u-boot

Hi Tom,

Please pull some riscv updates:

- Support Microchip MPFS Icicle board.
- Enable e1000 and nvme support for qemu.
- Enable PCI host ECAM generic driver for qemu.
- Increase the environment size to 128kB for qemu.

https://travis-ci.org/rickchen36/u-boot-riscv/builds/541565696

Thanks
Rick


The following changes since commit 38c2a8a00132b4dcc6a0bb5baf5146b9eb9eb2d2:

  Merge tag 'efi-2019-07-rc4' of git://git.denx.de/u-boot-efi (2019-06-02 18:19:45 -0400)

are available in the Git repository at:

  git://git.denx.de/u-boot-riscv.git

for you to fetch changes up to 39494822e3a639c8b5d60538d1dcae17bcf3c5f6:

  riscv: Add Microchip MPFS Icicle board support (2019-06-05 13:19:24 +0800)

----------------------------------------------------------------
Bin Meng (2):
      riscv: qemu: Enable PCI host ECAM generic driver
      riscv: qemu: Enable e1000 and nvme support

Karsten Merker (1):
      riscv: increase the environment size for the qemu-riscv platform to 128kB

Padmarao Begari (1):
      riscv: Add Microchip MPFS Icicle board support

 arch/riscv/Kconfig                        |  4 ++++
 board/emulation/qemu-riscv/Kconfig        |  6 ++++++
 board/microchip/mpfs_icicle/Kconfig       | 26 ++++++++++++++++++++++++++
 board/microchip/mpfs_icicle/MAINTAINERS   |  7 +++++++
 board/microchip/mpfs_icicle/Makefile      |  7 +++++++
 board/microchip/mpfs_icicle/mpfs_icicle.c | 30 ++++++++++++++++++++++++++++++
 configs/microchip_mpfs_icicle_defconfig   |  8 ++++++++
 include/configs/microchip_mpfs_icicle.h   | 63 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 include/configs/qemu-riscv.h              |  2 +-
 9 files changed, 152 insertions(+), 1 deletion(-)
 create mode 100644 board/microchip/mpfs_icicle/Kconfig
 create mode 100644 board/microchip/mpfs_icicle/MAINTAINERS
 create mode 100644 board/microchip/mpfs_icicle/Makefile
 create mode 100644 board/microchip/mpfs_icicle/mpfs_icicle.c
 create mode 100644 configs/microchip_mpfs_icicle_defconfig
 create mode 100644 include/configs/microchip_mpfs_icicle.h

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2019-05-09  9:08 uboot at andestech.com
@ 2019-05-09 22:25 ` Tom Rini
  0 siblings, 0 replies; 53+ messages in thread
From: Tom Rini @ 2019-05-09 22:25 UTC (permalink / raw)
  To: u-boot

On Thu, May 09, 2019 at 05:08:08PM +0800, uboot at andestech.com wrote:

> Hi Tom,
> 
> Please pull some riscv updates:
> 
> - Correct SYS_TEXT_BASE for qemu.
> - Support booti.
> - Increase SYSBOOTM_LEN for Fedora/RISCV kernel.
> - Support SMP booting from flash.
> 
> https://travis-ci.org/rickchen36/u-boot-riscv/builds/530082266
> 
> Thanks
> Rick
> 
> 
> The following changes since commit 504bf790da08db9b4a443566cf6ef577f9c7996a:
> 
>   Merge branch 'master' of git://git.denx.de/u-boot-sunxi (2019-05-08 16:21:43 -0400)
> 
> are available in the Git repository at:
> 
>   git://git.denx.de/u-boot-riscv.git
> 
> for you to fetch changes up to 3cedc97479ff44cdc00485de7517a833e3dfb630:
> 
>   RISCV: image: Add booti support (2019-05-09 16:47:52 +0800)
> 

Applied to u-boot/master, thanks!


-- 
Tom
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* [U-Boot]  Pull request: u-boot-riscv/master
@ 2019-05-09  9:08 uboot at andestech.com
  2019-05-09 22:25 ` Tom Rini
  0 siblings, 1 reply; 53+ messages in thread
From: uboot at andestech.com @ 2019-05-09  9:08 UTC (permalink / raw)
  To: u-boot

Hi Tom,

Please pull some riscv updates:

- Correct SYS_TEXT_BASE for qemu.
- Support booti.
- Increase SYSBOOTM_LEN for Fedora/RISCV kernel.
- Support SMP booting from flash.

https://travis-ci.org/rickchen36/u-boot-riscv/builds/530082266

Thanks
Rick


The following changes since commit 504bf790da08db9b4a443566cf6ef577f9c7996a:

  Merge branch 'master' of git://git.denx.de/u-boot-sunxi (2019-05-08 16:21:43 -0400)

are available in the Git repository at:

  git://git.denx.de/u-boot-riscv.git

for you to fetch changes up to 3cedc97479ff44cdc00485de7517a833e3dfb630:

  RISCV: image: Add booti support (2019-05-09 16:47:52 +0800)

----------------------------------------------------------------
Anup Patel (1):
      riscv: qemu: Use correct SYS_TEXT_BASE for S-mode on 32bit system

Atish Patra (1):
      RISCV: image: Add booti support

David Abdurachmanov (2):
      riscv: set CONFIG_SYS_BOOTM_LEN to SZ_64M
      riscv: qemu-riscv.h: define CONFIG_PREBOOT (enables extlinux)

Rick Chen (5):
      riscv: Introduce CONFIG_XIP to support booting from flash
      riscv: configs: Support AE350 SMP booting from flash flow
      riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled
      riscv: configs: AE350 will use CONFIG_OF_PRIOR_STAGE when boots from ram
      riscv: configs: AE350 will use CONFIG_OF_SEPARATE when boots from flash

 arch/riscv/Kconfig                      |  7 +++++++
 arch/riscv/cpu/cpu.c                    |  4 ++++
 arch/riscv/cpu/start.S                  |  8 ++++++++
 arch/riscv/include/asm/global_data.h    |  2 ++
 arch/riscv/lib/Makefile                 |  1 +
 arch/riscv/lib/asm-offsets.c            |  2 ++
 arch/riscv/lib/image.c                  | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/riscv/lib/smp.c                    |  2 ++
 board/AndesTech/ax25-ae350/MAINTAINERS  |  2 ++
 board/AndesTech/ax25-ae350/ax25-ae350.c |  4 ----
 board/emulation/qemu-riscv/Kconfig      |  3 ++-
 cmd/Kconfig                             |  2 +-
 cmd/booti.c                             |  8 ++++++--
 configs/ae350_rv32_defconfig            |  2 +-
 configs/ae350_rv32_xip_defconfig        | 37 +++++++++++++++++++++++++++++++++++++
 configs/ae350_rv64_defconfig            |  2 +-
 configs/ae350_rv64_xip_defconfig        | 38 ++++++++++++++++++++++++++++++++++++++
 include/configs/ax25-ae350.h            |  2 +-
 include/configs/qemu-riscv.h            | 16 ++++++++++------
 19 files changed, 180 insertions(+), 17 deletions(-)
 create mode 100644 arch/riscv/lib/image.c
 create mode 100644 configs/ae350_rv32_xip_defconfig
 create mode 100644 configs/ae350_rv64_xip_defconfig

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2019-04-08  6:46 uboot at andestech.com
@ 2019-04-09 16:10 ` Tom Rini
  0 siblings, 0 replies; 53+ messages in thread
From: Tom Rini @ 2019-04-09 16:10 UTC (permalink / raw)
  To: u-boot

On Mon, Apr 08, 2019 at 02:46:54PM +0800, uboot at andestech.com wrote:

> Hi Tom,
> 
> Please pull some riscv updates:
> 
> 1. RISC-V arch support SMP.
> 2. Support Andestech's PLIC and PLMT.
> 2. qemu, fu54e, ae350 boards enable SMP by default.
> 3. Fix CONFIG_DEFAULT_DEVICE_TREE failure.
> 
> https://travis-ci.org/rickchen36/u-boot-riscv/builds/517045091
> 
> Thanks
> Rick
> 
> 
> The following changes since commit 0e62d5b2abb69ddc9e58215e2d8dfa5d33996b8a:
> 
>   Merge tag 'u-boot-imx-20190405' of git://git.denx.de/u-boot-imx (2019-04-05 09:09:56 -0400)
> 
> are available in the Git repository at:
> 
>   git://git.denx.de/u-boot-riscv.git
> 
> for you to fetch changes up to 48b90d9db5d32e587901c4f33175488dd20fe0a5:
> 
>   riscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failure (2019-04-08 09:46:00 +0800)
> 

Applied to u-boot/master, thanks!


-- 
Tom
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* [U-Boot]  Pull request: u-boot-riscv/master
@ 2019-04-08  6:46 uboot at andestech.com
  2019-04-09 16:10 ` Tom Rini
  0 siblings, 1 reply; 53+ messages in thread
From: uboot at andestech.com @ 2019-04-08  6:46 UTC (permalink / raw)
  To: u-boot

Hi Tom,

Please pull some riscv updates:

1. RISC-V arch support SMP.
2. Support Andestech's PLIC and PLMT.
2. qemu, fu54e, ae350 boards enable SMP by default.
3. Fix CONFIG_DEFAULT_DEVICE_TREE failure.

https://travis-ci.org/rickchen36/u-boot-riscv/builds/517045091

Thanks
Rick


The following changes since commit 0e62d5b2abb69ddc9e58215e2d8dfa5d33996b8a:

  Merge tag 'u-boot-imx-20190405' of git://git.denx.de/u-boot-imx (2019-04-05 09:09:56 -0400)

are available in the Git repository at:

  git://git.denx.de/u-boot-riscv.git

for you to fetch changes up to 48b90d9db5d32e587901c4f33175488dd20fe0a5:

  riscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failure (2019-04-08 09:46:00 +0800)

----------------------------------------------------------------
Lukas Auer (11):
      riscv: add infrastructure for calling functions on other harts
      riscv: import the supervisor binary interface header file
      riscv: implement IPI platform functions using SBI
      riscv: delay initialization of caches and debug UART
      riscv: save hart ID in register tp instead of s0
      riscv: add support for multi-hart systems
      riscv: boot images passed to bootm on all harts
      riscv: do not rely on hart ID passed by previous boot stage
      riscv: hang if relocation of secondary harts fails
      riscv: fu540: enable SMP
      riscv: qemu: enable SMP

Rick Chen (7):
      riscv: Add a SYSCON driver for Andestech's PLIC
      riscv: Add a SYSCON driver for Andestech's PLMT
      riscv: ax25: Add platform-specific Kconfig options
      riscv: ax25: Andes specific cache shall only support in M-mode
      riscv: dts: ae350 support SMP
      riscv: ae350: enable SMP
      riscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failure

 arch/riscv/Kconfig                   |  46 +++++++++++++++++++++++++++++++
 arch/riscv/cpu/ax25/Kconfig          |   7 +++++
 arch/riscv/cpu/cpu.c                 |   9 +++++-
 arch/riscv/cpu/start.S               | 167 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------
 arch/riscv/dts/Makefile              |   2 ++
 arch/riscv/dts/ae350_32.dts          |  81 +++++++++++++++++++++++++++++++++++++++---------------
 arch/riscv/dts/ae350_64.dts          |  81 +++++++++++++++++++++++++++++++++++++++---------------
 arch/riscv/include/asm/csr.h         |   1 +
 arch/riscv/include/asm/global_data.h |  12 ++++++++
 arch/riscv/include/asm/sbi.h         |  94 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/riscv/include/asm/smp.h         |  53 ++++++++++++++++++++++++++++++++++++
 arch/riscv/include/asm/syscon.h      |   4 +--
 arch/riscv/lib/Makefile              |   4 +++
 arch/riscv/lib/andes_plic.c          | 113 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/riscv/lib/andes_plmt.c          |  53 ++++++++++++++++++++++++++++++++++++
 arch/riscv/lib/asm-offsets.c         |   1 +
 arch/riscv/lib/bootm.c               |  13 ++++++++-
 arch/riscv/lib/sbi_ipi.c             |  25 +++++++++++++++++
 arch/riscv/lib/smp.c                 | 118 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 board/AndesTech/ax25-ae350/Kconfig   |   1 +
 board/emulation/qemu-riscv/Kconfig   |   1 +
 board/sifive/fu540/Kconfig           |   1 +
 configs/ae350_rv32_defconfig         |   1 -
 configs/ae350_rv64_defconfig         |   1 -
 24 files changed, 829 insertions(+), 60 deletions(-)
 create mode 100644 arch/riscv/include/asm/sbi.h
 create mode 100644 arch/riscv/include/asm/smp.h
 create mode 100644 arch/riscv/lib/andes_plic.c
 create mode 100644 arch/riscv/lib/andes_plmt.c
 create mode 100644 arch/riscv/lib/sbi_ipi.c
 create mode 100644 arch/riscv/lib/smp.c

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2019-02-27  5:39 uboot at andestech.com
@ 2019-02-28  3:59 ` Tom Rini
  0 siblings, 0 replies; 53+ messages in thread
From: Tom Rini @ 2019-02-28  3:59 UTC (permalink / raw)
  To: u-boot

On Wed, Feb 27, 2019 at 01:39:44PM +0800, uboot at andestech.com wrote:

> Hi Tom,
> 
> Please pull some riscv updates:
> 
> SiFive FU540 Support
> 
> https://travis-ci.org/rickchen36/u-boot-riscv/builds/499037971
> 
> Thanks
> Rick
> 
> 
> The following changes since commit b3820ba997f004a376efc5446683101ff42b05af:
> 
>   Merge tag 'efi-2019-04-rc3' of https://github.com/xypron2/u-boot (2019-02-26 08:45:08 -0500)
> 
> are available in the Git repository at:
> 
>   git://git.denx.de/u-boot-riscv.git
> 
> for you to fetch changes up to 98a66ffa3aafd20d38f357d624e470e20fbb1839:
> 
>   riscv: Enable CONFIG_SYS_BOOT_RAMDISK_HIGH for using initrd (2019-02-27 09:12:34 +0800)
> 

Applied to u-boot/master, thanks!

-- 
Tom
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* [U-Boot]  Pull request: u-boot-riscv/master
@ 2019-02-27  5:39 uboot at andestech.com
  2019-02-28  3:59 ` Tom Rini
  0 siblings, 1 reply; 53+ messages in thread
From: uboot at andestech.com @ 2019-02-27  5:39 UTC (permalink / raw)
  To: u-boot

Hi Tom,

Please pull some riscv updates:

SiFive FU540 Support

https://travis-ci.org/rickchen36/u-boot-riscv/builds/499037971

Thanks
Rick


The following changes since commit b3820ba997f004a376efc5446683101ff42b05af:

  Merge tag 'efi-2019-04-rc3' of https://github.com/xypron2/u-boot (2019-02-26 08:45:08 -0500)

are available in the Git repository at:

  git://git.denx.de/u-boot-riscv.git

for you to fetch changes up to 98a66ffa3aafd20d38f357d624e470e20fbb1839:

  riscv: Enable CONFIG_SYS_BOOT_RAMDISK_HIGH for using initrd (2019-02-27 09:12:34 +0800)

----------------------------------------------------------------
Anup Patel (10):
      riscv: Enable create symlink using kconfig
      riscv: Rename cpu/qemu to cpu/generic
      riscv: Add asm/dma-mapping.h for DMA mappings
      riscv: Add place-holder asm/arch/clk.h for driver compilation
      riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems
      net: macb: Fix clk API usage for RISC-V systems
      clk: Add SiFive FU540 PRCI clock driver
      clk: Add fixed-factor clock driver
      riscv: Add SiFive FU540 board support
      riscv: Enable CONFIG_SYS_BOOT_RAMDISK_HIGH for using initrd

Atish Patra (5):
      net: macb: Fix GEM hardware detection
      drivers: serial_sifive: Fix baud rate calculation
      drivers: serial_sifive: Skip baudrate config if no input clock
      cpu: Bind timer driver for boot hart
      doc: Add a readme guide for SiFive FU540

 arch/Kconfig                                          |   1 +
 arch/riscv/Kconfig                                    |   6 +-
 arch/riscv/cpu/{qemu => generic}/Kconfig              |   2 +-
 arch/riscv/cpu/{qemu => generic}/Makefile             |   0
 arch/riscv/cpu/{qemu => generic}/cpu.c                |   0
 arch/riscv/cpu/generic/dram.c                         |  37 ++++++
 arch/riscv/cpu/qemu/dram.c                            |  17 ---
 arch/riscv/include/asm/arch-generic/clk.h             |  14 +++
 arch/riscv/include/asm/config.h                       |   1 +
 arch/riscv/include/asm/dma-mapping.h                  |  38 ++++++
 arch/sandbox/dts/test.dts                             |   8 ++
 board/emulation/qemu-riscv/Kconfig                    |   4 +-
 board/sifive/fu540/Kconfig                            |  42 +++++++
 board/sifive/fu540/MAINTAINERS                        |   9 ++
 board/sifive/fu540/Makefile                           |   5 +
 board/sifive/fu540/fu540.c                            |  17 +++
 configs/sifive_fu540_defconfig                        |  11 ++
 doc/README.sifive-fu540                               | 303 ++++++++++++++++++++++++++++++++++++++++++++++++
 doc/device-tree-bindings/clock/fixed-factor-clock.txt |  24 ++++
 drivers/clk/Kconfig                                   |   1 +
 drivers/clk/Makefile                                  |   5 +-
 drivers/clk/clk_fixed_factor.c                        |  74 ++++++++++++
 drivers/clk/sifive/Kconfig                            |  19 +++
 drivers/clk/sifive/Makefile                           |   5 +
 drivers/clk/sifive/analogbits-wrpll-cln28hpc.h        | 101 ++++++++++++++++
 drivers/clk/sifive/fu540-prci.c                       | 604 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/sifive/wrpll-cln28hpc.c                   | 390 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/cpu/riscv_cpu.c                               |   7 +-
 drivers/net/macb.c                                    |  11 +-
 drivers/serial/serial_sifive.c                        |  60 +++++++---
 include/configs/sifive-fu540.h                        |  43 +++++++
 include/dt-bindings/clk/sifive-fu540-prci.h           |  29 +++++
 test/dm/clk.c                                         |   5 +-
 33 files changed, 1843 insertions(+), 50 deletions(-)
 rename arch/riscv/cpu/{qemu => generic}/Kconfig (91%)
 rename arch/riscv/cpu/{qemu => generic}/Makefile (100%)
 rename arch/riscv/cpu/{qemu => generic}/cpu.c (100%)
 create mode 100644 arch/riscv/cpu/generic/dram.c
 delete mode 100644 arch/riscv/cpu/qemu/dram.c
 create mode 100644 arch/riscv/include/asm/arch-generic/clk.h
 create mode 100644 arch/riscv/include/asm/dma-mapping.h
 create mode 100644 board/sifive/fu540/Kconfig
 create mode 100644 board/sifive/fu540/MAINTAINERS
 create mode 100644 board/sifive/fu540/Makefile
 create mode 100644 board/sifive/fu540/fu540.c
 create mode 100644 configs/sifive_fu540_defconfig
 create mode 100644 doc/README.sifive-fu540
 create mode 100644 doc/device-tree-bindings/clock/fixed-factor-clock.txt
 create mode 100644 drivers/clk/clk_fixed_factor.c
 create mode 100644 drivers/clk/sifive/Kconfig
 create mode 100644 drivers/clk/sifive/Makefile
 create mode 100644 drivers/clk/sifive/analogbits-wrpll-cln28hpc.h
 create mode 100644 drivers/clk/sifive/fu540-prci.c
 create mode 100644 drivers/clk/sifive/wrpll-cln28hpc.c
 create mode 100644 include/configs/sifive-fu540.h
 create mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot] Pull request: u-boot-riscv/master
  2019-01-15  7:16 uboot at andestech.com
@ 2019-01-16 17:11 ` Tom Rini
  0 siblings, 0 replies; 53+ messages in thread
From: Tom Rini @ 2019-01-16 17:11 UTC (permalink / raw)
  To: u-boot

On Tue, Jan 15, 2019 at 03:16:39PM +0800, uboot at andestech.com wrote:

> Hi Tom,
> 
> Please pull some riscv updates:
> 1. Improve cache implementation.
> 2. Fix and improve standalone applications
> 
> https://travis-ci.org/rickchen36/u-boot-riscv/builds/479684449
> 
> Thanks
> 
> Rick
> 
> 
> The following changes since commit d3689267f92c5956e09cc7d1baa4700141662bff:
> 
>   Prepare v2019.01 (2019-01-14 17:02:36 -0500)
> 
> are available in the Git repository at:
> 
>   git://git.denx.de/u-boot-riscv.git
> 
> for you to fetch changes up to 91882c472d8c0aef4db699d3f2de55bf43d4ae4b:
> 
>   riscv: qemu: define standalone load address (2019-01-15 09:36:31 +0800)
> 

Applied to u-boot/master, thanks!

-- 
Tom
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^ permalink raw reply	[flat|nested] 53+ messages in thread

* [U-Boot]  Pull request: u-boot-riscv/master
@ 2019-01-15  7:16 uboot at andestech.com
  2019-01-16 17:11 ` Tom Rini
  0 siblings, 1 reply; 53+ messages in thread
From: uboot at andestech.com @ 2019-01-15  7:16 UTC (permalink / raw)
  To: u-boot

Hi Tom,

Please pull some riscv updates:
1. Improve cache implementation.
2. Fix and improve standalone applications

https://travis-ci.org/rickchen36/u-boot-riscv/builds/479684449

Thanks

Rick


The following changes since commit d3689267f92c5956e09cc7d1baa4700141662bff:

  Prepare v2019.01 (2019-01-14 17:02:36 -0500)

are available in the Git repository at:

  git://git.denx.de/u-boot-riscv.git

for you to fetch changes up to 91882c472d8c0aef4db699d3f2de55bf43d4ae4b:

  riscv: qemu: define standalone load address (2019-01-15 09:36:31 +0800)

----------------------------------------------------------------
Lukas Auer (7):
      riscv: clarify error message on undefined exceptions
      riscv: move the AX25-specific implementation of flush_dcache_all
      riscv: use invalidate/flush_*cache_range functions in cache.c
      riscv: remove RISC-V standalone linker script
      riscv: replace use of callee-saved register in standalone
      riscv: support standalone applications on RV64I systems
      riscv: qemu: define standalone load address

 arch/riscv/config.mk          |  3 +--
 arch/riscv/cpu/ax25/cache.c   | 22 ++++++++++++++++++++++
 arch/riscv/lib/cache.c        | 14 ++++++--------
 arch/riscv/lib/interrupts.c   |  3 ++-
 examples/standalone/riscv.lds | 40 ----------------------------------------
 examples/standalone/stubs.c   | 21 ++++++++++++++++-----
 include/configs/qemu-riscv.h  |  2 ++
 7 files changed, 49 insertions(+), 56 deletions(-)
 delete mode 100644 examples/standalone/riscv.lds

^ permalink raw reply	[flat|nested] 53+ messages in thread

end of thread, other threads:[~2020-07-03  6:52 UTC | newest]

Thread overview: 53+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-25  8:01 [U-Boot] Pull request: u-boot-riscv/master uboot at andestech.com
2020-05-25 15:40 ` Tom Rini
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA470F21C@ATCPCS16.andestech.com>
2020-05-26  7:41     ` Rick Chen
2020-06-22  6:03     ` Rick Chen
2020-06-23  0:45       ` Tom Rini
2020-06-23  2:05         ` Rick Chen
2020-06-24  1:31         ` Rick Chen
2020-06-24  3:37           ` Sean Anderson
  -- strict thread matches above, loose matches on Subject: below --
2020-07-02  2:51 uboot at andestech.com
2020-07-02 13:53 ` Tom Rini
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA47207DF@ATCPCS16.andestech.com>
2020-07-03  6:01     ` Rick Chen
2020-07-03  6:52       ` Bin Meng
2020-06-24  2:30 uboot at andestech.com
2020-06-24  2:57 ` Bin Meng
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA471C57A@ATCPCS16.andestech.com>
2020-06-24  3:13     ` Rick Chen
2020-06-04  2:18 uboot at andestech.com
2020-06-04 18:47 ` Tom Rini
2020-05-26  8:31 uboot at andestech.com
2020-05-26 19:55 ` Tom Rini
2020-04-23  8:25 uboot at andestech.com
2020-04-23 20:50 ` Tom Rini
2020-03-17  8:03 uboot at andestech.com
2020-03-18 13:56 ` Tom Rini
2020-02-10  7:29 uboot at andestech.com
2020-02-10 13:09 ` Tom Rini
2019-12-10  1:05 uboot at andestech.com
2019-12-10  4:01 ` Tom Rini
2019-10-18  7:00 uboot at andestech.com
2019-10-19 14:24 ` Tom Rini
2019-09-03  2:15 uboot at andestech.com
2019-09-04  0:58 ` Tom Rini
2019-08-26  8:25 uboot at andestech.com
2019-08-27  0:17 ` Tom Rini
2019-08-16  5:19 uboot at andestech.com
2019-08-17 17:47 ` Tom Rini
2019-08-12 10:23 uboot at andestech.com
2019-08-13 16:50 ` Tom Rini
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA40FF880@ATCPCS16.andestech.com>
2019-08-14  2:20     ` Rick Chen
2019-08-14 20:15       ` Auer, Lukas
2019-08-20 21:11         ` Auer, Lukas
2019-08-21  2:10           ` Rick Chen
2019-07-19  7:06 uboot at andestech.com
2019-07-23 13:46 ` Tom Rini
2019-06-05 10:27 uboot at andestech.com
2019-06-05 14:24 ` Tom Rini
2019-05-09  9:08 uboot at andestech.com
2019-05-09 22:25 ` Tom Rini
2019-04-08  6:46 uboot at andestech.com
2019-04-09 16:10 ` Tom Rini
2019-02-27  5:39 uboot at andestech.com
2019-02-28  3:59 ` Tom Rini
2019-01-15  7:16 uboot at andestech.com
2019-01-16 17:11 ` Tom Rini

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