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From: Richard Henderson <richard.henderson@linaro.org>
To: Yifei Jiang <jiangyifei@huawei.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: zhang.zhanghailiang@huawei.com, sagark@eecs.berkeley.edu,
	kbastian@mail.uni-paderborn.de, victor.zhangxiaofeng@huawei.com,
	Alistair.Francis@wdc.com, yinyipeng1@huawei.com,
	palmer@dabbelt.com, wu.wubin@huawei.com, dengkai1@huawei.com
Subject: Re: [PATCH 3/5] target/riscv: Add H extention state description
Date: Thu, 1 Oct 2020 12:28:21 -0500	[thread overview]
Message-ID: <2e725e26-3952-dbd2-c4aa-d9e933406220@linaro.org> (raw)
In-Reply-To: <20200929020337.1559-4-jiangyifei@huawei.com>

On 9/28/20 9:03 PM, Yifei Jiang wrote:
> +        VMSTATE_UINTTL(env.vsstatus, RISCVCPU),
> +        VMSTATE_UINTTL(env.vstvec, RISCVCPU),
> +        VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
> +        VMSTATE_UINTTL(env.vsepc, RISCVCPU),
> +        VMSTATE_UINTTL(env.vscause, RISCVCPU),
> +        VMSTATE_UINTTL(env.vstval, RISCVCPU),
> +        VMSTATE_UINTTL(env.vsatp, RISCVCPU),

So... if I understand things correctly, this is synthetic state, internal to
QEMU.  It is generally better to only serialize architectural state, so that if
qemu internals are rearranged, it is easy to decide on the correct sequence of
operations.

It seems like this should be re-generated with a post_load hook, calling some
of the code currently in riscv_cpu_swap_hypervisor_regs().  Note that some
minor rearrangement would be needed to call that code from this new context.


r~


  reply	other threads:[~2020-10-01 17:58 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-29  2:03 [PATCH 0/5] Support RISC-V migration Yifei Jiang
2020-09-29  2:03 ` Yifei Jiang
2020-09-29  2:03 ` [PATCH 1/5] target/riscv: Add basic vmstate description of CPU Yifei Jiang
2020-09-29  2:03   ` Yifei Jiang
2020-10-01 17:23   ` Richard Henderson
2020-10-09  8:11     ` Jiangyifei
2020-10-09  8:11       ` Jiangyifei
2020-09-29  2:03 ` [PATCH 2/5] target/riscv: Add PMP state description Yifei Jiang
2020-09-29  2:03   ` Yifei Jiang
2020-10-05 22:10   ` Alistair Francis
2020-10-05 22:10     ` Alistair Francis
2020-10-09  8:33     ` Jiangyifei
2020-10-09  8:33       ` Jiangyifei
2020-09-29  2:03 ` [PATCH 3/5] target/riscv: Add H extention " Yifei Jiang
2020-09-29  2:03   ` Yifei Jiang
2020-10-01 17:28   ` Richard Henderson [this message]
2020-10-05 22:09     ` Alistair Francis
2020-10-05 22:09       ` Alistair Francis
2020-10-09  8:29     ` Jiangyifei
2020-10-09  8:29       ` Jiangyifei
2020-09-29  2:03 ` [PATCH 4/5] target/riscv: Add V " Yifei Jiang
2020-09-29  2:03   ` Yifei Jiang
2020-10-01 17:30   ` Richard Henderson
2020-09-29  2:03 ` [PATCH 5/5] target/riscv: Add sifive_plic vmstate Yifei Jiang
2020-09-29  2:03   ` Yifei Jiang

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