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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?AaNddRHYtjDLi402jCoOxaCuWN98150ra6yHAfiRHbj3JkMFhuPIM5JZ8Eqf?= =?us-ascii?Q?gwzJD75zawlCsTxGg+r7Z670L4ykf8nmyy3NW0gUpY1OFISd7wIHG77cH7YH?= =?us-ascii?Q?dcygXpydv3gXcwIsOEKjJiYIES3dHOlsau3Y6mVXs0wa4HCbs1+yZ3AkgXpR?= =?us-ascii?Q?k/+P2lynKUvEmcX7BpK8hPP9b/nRAm0YKesmMxnzPVJ0WHZpKCb7RecOxhzI?= =?us-ascii?Q?caQfcffcf7OxbMkgGSIODneUax+75PsOQ82rHvy+gHtw1bDS0XYlMYl3cPA/?= =?us-ascii?Q?Yn2DZbpZq+R5JNPCjMd9n7PnM5KII0ERFG4auBOQXv/7sdMI1Fz+gTAORN0w?= =?us-ascii?Q?C+tOduLjgiJJYbxR2s3eRrWhQM0sHRo0dqb3OP/0tSpITnUBxJbAnTGQLmd0?= =?us-ascii?Q?jSJvru97o4WMh6T/dCj8pHTwZbr3m/Mdm2yRMtjuoo5Or/aXv/Ohizh7nm2n?= =?us-ascii?Q?V+ileUTUM/4wG1MrePxGjIeS4Mc+RCeN9CHg7Geu9ieES2JHivTt6H358vZE?= =?us-ascii?Q?rMRkI0l7oC+TP78YWvdwQBNoOw5OUd37X2s7wB8cCUVxWuTMwt4NJQENAL7F?= =?us-ascii?Q?koObvwB1TUSgJwS8xfs6s/lYr+y77lzQ2+Q5U6UvR4TXslF3fzpnRl3aarnS?= =?us-ascii?Q?KHqV1b3Mkaem3kMC5/vQAcmoaJuSMTY6VKjas9n9zC8M5Z0ME/BLvsEJ9QOQ?= =?us-ascii?Q?4WrfLYeeFk/TC1XXSPG4t3NBXI6fXmegkBdhqaM39HifP1MoIySOmKI/wHWb?= =?us-ascii?Q?uNISDnKaZRcabVWyqVpWqMbZhijG6LFBgN3YBQQtJL0UudXo2NgVEkX1THKH?= =?us-ascii?Q?/vLfCi7VY0S6vzP4wSwnXME2TpFawZu7Prf0j8/cRGG1z00pxSvP+oEMawtd?= =?us-ascii?Q?aMx+sO8e5eRoYIpQDxEm2wSCNVKKjajlFNMoBS5WjMf3JXxPt0bkSLVLIo0y?= =?us-ascii?Q?3o8r2YAYsZqvZCu8RvKRuc6GHPLG8imx5iRYbXrVhx9OQDEdhMAwnszcTsXB?= =?us-ascii?Q?/DeKirg6PDahHHkx3Uo91NLPo/00xpi6svaIeqlMePxqv7i01/YMvmMECixP?= =?us-ascii?Q?6UKtH1UTILqUQu/NKWTh4McXiwaP/VpP/TqThvQtxi8iAq9LhHMgyUYdpGGS?= =?us-ascii?Q?OlkS7mxvPs5ZSuFbLXVlmMjToNIMX/jbjmXENkrzOqRIflZQQ9zJ8VmKB7xr?= =?us-ascii?Q?NVR+1wiq3PIWovYJudiqpif7IxeR8oKb8SAiH2DjKcvaEVGy3x2STpPomn8/?= =?us-ascii?Q?QeQ3vWoa6LW6TEVuj2AxTJctxES1G733ofH3PdfhKAooCb8K3almrNR8IP2D?= =?us-ascii?Q?YU465cywLlrkgi+koevJkLA937nD0sViFKWLTsjEWmMewb7USzfndMZ4TZXy?= =?us-ascii?Q?EttXs5GeM5OVq7VBOtXD8iqmqMKgbeFNH/YxhAwE8XsIZyEGxkgGKxobYebl?= =?us-ascii?Q?kLGTDxPyWmR6N7KqiQDBHoziG0rg7k2WQiRmUGQK6G+WsqsNrS9m7mG3hbb2?= =?us-ascii?Q?8O1iEO2qQxtxZlI1igHjNh9itKNn4QgA4BbwiqvHDhnrIbQOOegBWg31CHWS?= =?us-ascii?Q?+cOYcjZFVSzm0EBdjV46Fjr2idK/x1Y9zne3KDQkEl9c1lrVlhxKTJp0xKkd?= =?us-ascii?Q?v8PYVRMNtH4NnQFQqBBVKuZJy81hNlg+UUhTEUFGk9fw9tzOwo4oHgmZnIiX?= =?us-ascii?Q?v5iuSQp45sJSAVpZakskCwMh0Efp9Bn08a8fonMRa0oouHH7kXKjRrtImtHB?= =?us-ascii?Q?V2H/HOEJDw=3D=3D?= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: 28ab3a3a-1f2c-420d-a058-08da485c1f01 X-MS-Exchange-CrossTenant-AuthSource: VE1PR04MB6560.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2022 08:02:52.1831 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: xCSxbwWEFFQCeG7xSMFU2cGd6AwXUfzif9WWAnP/gY79OCWHNQNFANuhkSW+sz3HsHVDBnlZLcV410ctfk0H2A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB7735 On 03.06.2022 16:53, Roger Pau Monn=C3=A9 wrote: > On Fri, Jun 03, 2022 at 03:19:34PM +0200, Jan Beulich wrote: >> On 21.04.2022 15:21, Roger Pau Monne wrote: >>> Allow disabling (masking) IO-APIC pins set to edge trigger mode. This >>> is required in order to safely migrate such interrupts between CPUs, >>> as the write to update the IO-APIC RTE (or the IRTE) is not done >>> atomically, >> >> For IRTE on VT-d we use cmpxchg16b if available (i.e. virtually always). >> >>> so there's a window where there's a mismatch between the >>> destination CPU and the vector: >>> >>> (XEN) CPU1: No irq handler for vector b5 (IRQ -11, LAPIC) >>> (XEN) IRQ10 a=3D0002[0002,0008] v=3Dbd[b5] t=3DIO-APIC-edge s=3D0000003= 0 >> >> I think this needs some further explanation, as we generally move >> edge IRQs only when an un-acked interrupt is in flight (and hence >> no further one can arrive). >=20 > A further one can arrive as soon as you modify either the vector or > the destination fields of the IO-APIC RTE, as then the non-EOI'ed > lapic vector is no longer there (because you have moved to a different > destination or vector). Right - this is what I'm asking you to spell out in the description. Jan > This is the issue with updating the IO-APIC RTE using two separate > writes: even when using interrupt remapping the IRTE cannot be > atomically updated and there's a window where the interrupt is not > masked, but the destination and vector fields are not in sync, because > they reside in different parts of the RTE (destination is in the high > 32bits, vector in the low 32bits part of the RTE). >=20 > Thanks, Roger. >=20