[PATCH v2 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n)

[PATCH v2 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n)

[Fabiano Rosas]

Changes from v1:

- Restored the 'sc 1' support to avoid breaking the pegasos2 machine.

I tested this version in the G4 with the following OSes:

- Linux 5.15 (5.16 seems to be broken, even with master)
- FreeBSD 13
- Mac OS 9.2
- Mac OS Darwin 6.0
- Mac OS X 10.4
- MorphOS 3.15 (-M pegasos2 and -M mac99,via=pmu)

Based on legoater/ppc-7.0

v1:
https://lore.kernel.org/r/20220126164200.1048677-1-farosas@linux.ibm.com

Fabiano Rosas (8):
  target/ppc: Introduce powerpc_excp_74xx
  target/ppc: Simplify powerpc_excp_74xx
  target/ppc: 74xx: Machine Check exception cleanup
  target/ppc: 74xx: External interrupt cleanup
  target/ppc: 74xx: Program exception cleanup
  target/ppc: 74xx: System Call exception cleanup
  target/ppc: 74xx: System Reset interrupt cleanup
  target/ppc: 74xx: Set SRRs directly in exception code

 target/ppc/excp_helper.c | 197 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 197 insertions(+)

-- 
2.34.1

[PATCH v2 1/8] target/ppc: Introduce powerpc_excp_74xx

[Fabiano Rosas]

Introduce a new powerpc_excp function specific for PowerPC 74xx
CPUs. This commit copies powerpc_excp_legacy verbatim so the next one
has a clean diff.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
 target/ppc/excp_helper.c | 474 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 474 insertions(+)

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 0e84cecc68..0e3d3ffcf4 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -551,6 +551,477 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
     powerpc_set_excp_state(cpu, vector, new_msr);
 }
 
+static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
+{
+    CPUState *cs = CPU(cpu);
+    CPUPPCState *env = &cpu->env;
+    int excp_model = env->excp_model;
+    target_ulong msr, new_msr, vector;
+    int srr0, srr1, lev = -1;
+
+    if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
+        cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+    }
+
+    qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
+                  " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
+                  excp, env->error_code);
+
+    /* new srr1 value excluding must-be-zero bits */
+    if (excp_model == POWERPC_EXCP_BOOKE) {
+        msr = env->msr;
+    } else {
+        msr = env->msr & ~0x783f0000ULL;
+    }
+
+    /*
+     * new interrupt handler msr preserves existing HV and ME unless
+     * explicitly overriden
+     */
+    new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
+
+    /* target registers */
+    srr0 = SPR_SRR0;
+    srr1 = SPR_SRR1;
+
+    /*
+     * check for special resume at 0x100 from doze/nap/sleep/winkle on
+     * P7/P8/P9
+     */
+    if (env->resume_as_sreset) {
+        excp = powerpc_reset_wakeup(cs, env, excp, &msr);
+    }
+
+    /*
+     * Hypervisor emulation assistance interrupt only exists on server
+     * arch 2.05 server or later. We also don't want to generate it if
+     * we don't have HVB in msr_mask (PAPR mode).
+     */
+    if (excp == POWERPC_EXCP_HV_EMU
+#if defined(TARGET_PPC64)
+        && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
+#endif /* defined(TARGET_PPC64) */
+
+    ) {
+        excp = POWERPC_EXCP_PROGRAM;
+    }
+
+#ifdef TARGET_PPC64
+    /*
+     * SPEU and VPU share the same IVOR but they exist in different
+     * processors. SPEU is e500v1/2 only and VPU is e6500 only.
+     */
+    if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
+        excp = POWERPC_EXCP_SPEU;
+    }
+#endif
+
+    vector = env->excp_vectors[excp];
+    if (vector == (target_ulong)-1ULL) {
+        cpu_abort(cs, "Raised an exception without defined vector %d\n",
+                  excp);
+    }
+
+    vector |= env->excp_prefix;
+
+    switch (excp) {
+    case POWERPC_EXCP_CRITICAL:    /* Critical input                         */
+        switch (excp_model) {
+        case POWERPC_EXCP_40x:
+            srr0 = SPR_40x_SRR2;
+            srr1 = SPR_40x_SRR3;
+            break;
+        case POWERPC_EXCP_BOOKE:
+            srr0 = SPR_BOOKE_CSRR0;
+            srr1 = SPR_BOOKE_CSRR1;
+            break;
+        case POWERPC_EXCP_G2:
+            break;
+        default:
+            goto excp_invalid;
+        }
+        break;
+    case POWERPC_EXCP_MCHECK:    /* Machine check exception                  */
+        if (msr_me == 0) {
+            /*
+             * Machine check exception is not enabled.  Enter
+             * checkstop state.
+             */
+            fprintf(stderr, "Machine check while not allowed. "
+                    "Entering checkstop state\n");
+            if (qemu_log_separate()) {
+                qemu_log("Machine check while not allowed. "
+                        "Entering checkstop state\n");
+            }
+            cs->halted = 1;
+            cpu_interrupt_exittb(cs);
+        }
+        if (env->msr_mask & MSR_HVB) {
+            /*
+             * ISA specifies HV, but can be delivered to guest with HV
+             * clear (e.g., see FWNMI in PAPR).
+             */
+            new_msr |= (target_ulong)MSR_HVB;
+        }
+
+        /* machine check exceptions don't have ME set */
+        new_msr &= ~((target_ulong)1 << MSR_ME);
+
+        /* XXX: should also have something loaded in DAR / DSISR */
+        switch (excp_model) {
+        case POWERPC_EXCP_40x:
+            srr0 = SPR_40x_SRR2;
+            srr1 = SPR_40x_SRR3;
+            break;
+        case POWERPC_EXCP_BOOKE:
+            /* FIXME: choose one or the other based on CPU type */
+            srr0 = SPR_BOOKE_MCSRR0;
+            srr1 = SPR_BOOKE_MCSRR1;
+
+            env->spr[SPR_BOOKE_CSRR0] = env->nip;
+            env->spr[SPR_BOOKE_CSRR1] = msr;
+            break;
+        default:
+            break;
+        }
+        break;
+    case POWERPC_EXCP_DSI:       /* Data storage exception                   */
+        trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
+        break;
+    case POWERPC_EXCP_ISI:       /* Instruction storage exception            */
+        trace_ppc_excp_isi(msr, env->nip);
+        msr |= env->error_code;
+        break;
+    case POWERPC_EXCP_EXTERNAL:  /* External input                           */
+    {
+        bool lpes0;
+
+        cs = CPU(cpu);
+
+        /*
+         * Exception targeting modifiers
+         *
+         * LPES0 is supported on POWER7/8/9
+         * LPES1 is not supported (old iSeries mode)
+         *
+         * On anything else, we behave as if LPES0 is 1
+         * (externals don't alter MSR:HV)
+         */
+#if defined(TARGET_PPC64)
+        if (excp_model == POWERPC_EXCP_POWER7 ||
+            excp_model == POWERPC_EXCP_POWER8 ||
+            excp_model == POWERPC_EXCP_POWER9 ||
+            excp_model == POWERPC_EXCP_POWER10) {
+            lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
+        } else
+#endif /* defined(TARGET_PPC64) */
+        {
+            lpes0 = true;
+        }
+
+        if (!lpes0) {
+            new_msr |= (target_ulong)MSR_HVB;
+            new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+            srr0 = SPR_HSRR0;
+            srr1 = SPR_HSRR1;
+        }
+        if (env->mpic_proxy) {
+            /* IACK the IRQ on delivery */
+            env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
+        }
+        break;
+    }
+    case POWERPC_EXCP_ALIGN:     /* Alignment exception                      */
+        /* Get rS/rD and rA from faulting opcode */
+        /*
+         * Note: the opcode fields will not be set properly for a
+         * direct store load/store, but nobody cares as nobody
+         * actually uses direct store segments.
+         */
+        env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
+        break;
+    case POWERPC_EXCP_PROGRAM:   /* Program exception                        */
+        switch (env->error_code & ~0xF) {
+        case POWERPC_EXCP_FP:
+            if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
+                trace_ppc_excp_fp_ignore();
+                cs->exception_index = POWERPC_EXCP_NONE;
+                env->error_code = 0;
+                return;
+            }
+
+            /*
+             * FP exceptions always have NIP pointing to the faulting
+             * instruction, so always use store_next and claim we are
+             * precise in the MSR.
+             */
+            msr |= 0x00100000;
+            env->spr[SPR_BOOKE_ESR] = ESR_FP;
+            break;
+        case POWERPC_EXCP_INVAL:
+            trace_ppc_excp_inval(env->nip);
+            msr |= 0x00080000;
+            env->spr[SPR_BOOKE_ESR] = ESR_PIL;
+            break;
+        case POWERPC_EXCP_PRIV:
+            msr |= 0x00040000;
+            env->spr[SPR_BOOKE_ESR] = ESR_PPR;
+            break;
+        case POWERPC_EXCP_TRAP:
+            msr |= 0x00020000;
+            env->spr[SPR_BOOKE_ESR] = ESR_PTR;
+            break;
+        default:
+            /* Should never occur */
+            cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+                      env->error_code);
+            break;
+        }
+        break;
+    case POWERPC_EXCP_SYSCALL:   /* System call exception                    */
+        lev = env->error_code;
+
+        if ((lev == 1) && cpu->vhyp) {
+            dump_hcall(env);
+        } else {
+            dump_syscall(env);
+        }
+
+        /*
+         * We need to correct the NIP which in this case is supposed
+         * to point to the next instruction
+         */
+        env->nip += 4;
+
+        /* "PAPR mode" built-in hypercall emulation */
+        if ((lev == 1) && cpu->vhyp) {
+            PPCVirtualHypervisorClass *vhc =
+                PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+            vhc->hypercall(cpu->vhyp, cpu);
+            return;
+        }
+        if (lev == 1) {
+            new_msr |= (target_ulong)MSR_HVB;
+        }
+        break;
+    case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception                     */
+        lev = env->error_code;
+        dump_syscall(env);
+        env->nip += 4;
+        new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
+        new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+
+        vector += lev * 0x20;
+
+        env->lr = env->nip;
+        env->ctr = msr;
+        break;
+    case POWERPC_EXCP_FPU:       /* Floating-point unavailable exception     */
+    case POWERPC_EXCP_APU:       /* Auxiliary processor unavailable          */
+    case POWERPC_EXCP_DECR:      /* Decrementer exception                    */
+        break;
+    case POWERPC_EXCP_FIT:       /* Fixed-interval timer interrupt           */
+        /* FIT on 4xx */
+        trace_ppc_excp_print("FIT");
+        break;
+    case POWERPC_EXCP_WDT:       /* Watchdog timer interrupt                 */
+        trace_ppc_excp_print("WDT");
+        switch (excp_model) {
+        case POWERPC_EXCP_BOOKE:
+            srr0 = SPR_BOOKE_CSRR0;
+            srr1 = SPR_BOOKE_CSRR1;
+            break;
+        default:
+            break;
+        }
+        break;
+    case POWERPC_EXCP_DTLB:      /* Data TLB error                           */
+    case POWERPC_EXCP_ITLB:      /* Instruction TLB error                    */
+        break;
+    case POWERPC_EXCP_DEBUG:     /* Debug interrupt                          */
+        if (env->flags & POWERPC_FLAG_DE) {
+            /* FIXME: choose one or the other based on CPU type */
+            srr0 = SPR_BOOKE_DSRR0;
+            srr1 = SPR_BOOKE_DSRR1;
+
+            env->spr[SPR_BOOKE_CSRR0] = env->nip;
+            env->spr[SPR_BOOKE_CSRR1] = msr;
+
+            /* DBSR already modified by caller */
+        } else {
+            cpu_abort(cs, "Debug exception triggered on unsupported model\n");
+        }
+        break;
+    case POWERPC_EXCP_SPEU:   /* SPE/embedded floating-point unavailable/VPU  */
+        env->spr[SPR_BOOKE_ESR] = ESR_SPV;
+        break;
+    case POWERPC_EXCP_DOORI:     /* Embedded doorbell interrupt              */
+        break;
+    case POWERPC_EXCP_DOORCI:    /* Embedded doorbell critical interrupt     */
+        srr0 = SPR_BOOKE_CSRR0;
+        srr1 = SPR_BOOKE_CSRR1;
+        break;
+    case POWERPC_EXCP_RESET:     /* System reset exception                   */
+        /* A power-saving exception sets ME, otherwise it is unchanged */
+        if (msr_pow) {
+            /* indicate that we resumed from power save mode */
+            msr |= 0x10000;
+            new_msr |= ((target_ulong)1 << MSR_ME);
+        }
+        if (env->msr_mask & MSR_HVB) {
+            /*
+             * ISA specifies HV, but can be delivered to guest with HV
+             * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
+             */
+            new_msr |= (target_ulong)MSR_HVB;
+        } else {
+            if (msr_pow) {
+                cpu_abort(cs, "Trying to deliver power-saving system reset "
+                          "exception %d with no HV support\n", excp);
+            }
+        }
+        break;
+    case POWERPC_EXCP_DSEG:      /* Data segment exception                   */
+    case POWERPC_EXCP_ISEG:      /* Instruction segment exception            */
+    case POWERPC_EXCP_TRACE:     /* Trace exception                          */
+        break;
+    case POWERPC_EXCP_HISI:      /* Hypervisor instruction storage exception */
+        msr |= env->error_code;
+        /* fall through */
+    case POWERPC_EXCP_HDECR:     /* Hypervisor decrementer exception         */
+    case POWERPC_EXCP_HDSI:      /* Hypervisor data storage exception        */
+    case POWERPC_EXCP_HDSEG:     /* Hypervisor data segment exception        */
+    case POWERPC_EXCP_HISEG:     /* Hypervisor instruction segment exception */
+    case POWERPC_EXCP_SDOOR_HV:  /* Hypervisor Doorbell interrupt            */
+    case POWERPC_EXCP_HV_EMU:
+    case POWERPC_EXCP_HVIRT:     /* Hypervisor virtualization                */
+        srr0 = SPR_HSRR0;
+        srr1 = SPR_HSRR1;
+        new_msr |= (target_ulong)MSR_HVB;
+        new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+        break;
+    case POWERPC_EXCP_VPU:       /* Vector unavailable exception             */
+    case POWERPC_EXCP_VSXU:       /* VSX unavailable exception               */
+    case POWERPC_EXCP_FU:         /* Facility unavailable exception          */
+#ifdef TARGET_PPC64
+        env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
+#endif
+        break;
+    case POWERPC_EXCP_HV_FU:     /* Hypervisor Facility Unavailable Exception */
+#ifdef TARGET_PPC64
+        env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
+        srr0 = SPR_HSRR0;
+        srr1 = SPR_HSRR1;
+        new_msr |= (target_ulong)MSR_HVB;
+        new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+#endif
+        break;
+    case POWERPC_EXCP_PIT:       /* Programmable interval timer interrupt    */
+        trace_ppc_excp_print("PIT");
+        break;
+    case POWERPC_EXCP_IFTLB:     /* Instruction fetch TLB error              */
+    case POWERPC_EXCP_DLTLB:     /* Data load TLB miss                       */
+    case POWERPC_EXCP_DSTLB:     /* Data store TLB miss                      */
+        switch (excp_model) {
+        case POWERPC_EXCP_602:
+        case POWERPC_EXCP_603:
+        case POWERPC_EXCP_G2:
+            /* Swap temporary saved registers with GPRs */
+            if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
+                new_msr |= (target_ulong)1 << MSR_TGPR;
+                hreg_swap_gpr_tgpr(env);
+            }
+            /* fall through */
+        case POWERPC_EXCP_7x5:
+            ppc_excp_debug_sw_tlb(env, excp);
+
+            msr |= env->crf[0] << 28;
+            msr |= env->error_code; /* key, D/I, S/L bits */
+            /* Set way using a LRU mechanism */
+            msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
+            break;
+        default:
+            cpu_abort(cs, "Invalid TLB miss exception\n");
+            break;
+        }
+        break;
+    case POWERPC_EXCP_EFPDI:     /* Embedded floating-point data interrupt   */
+    case POWERPC_EXCP_EFPRI:     /* Embedded floating-point round interrupt  */
+    case POWERPC_EXCP_EPERFM:    /* Embedded performance monitor interrupt   */
+    case POWERPC_EXCP_IO:        /* IO error exception                       */
+    case POWERPC_EXCP_RUNM:      /* Run mode exception                       */
+    case POWERPC_EXCP_EMUL:      /* Emulation trap exception                 */
+    case POWERPC_EXCP_FPA:       /* Floating-point assist exception          */
+    case POWERPC_EXCP_DABR:      /* Data address breakpoint                  */
+    case POWERPC_EXCP_IABR:      /* Instruction address breakpoint           */
+    case POWERPC_EXCP_SMI:       /* System management interrupt              */
+    case POWERPC_EXCP_THERM:     /* Thermal interrupt                        */
+    case POWERPC_EXCP_PERFM:     /* Embedded performance monitor interrupt   */
+    case POWERPC_EXCP_VPUA:      /* Vector assist exception                  */
+    case POWERPC_EXCP_SOFTP:     /* Soft patch exception                     */
+    case POWERPC_EXCP_MAINT:     /* Maintenance exception                    */
+    case POWERPC_EXCP_MEXTBR:    /* Maskable external breakpoint             */
+    case POWERPC_EXCP_NMEXTBR:   /* Non maskable external breakpoint         */
+        cpu_abort(cs, "%s exception not implemented\n",
+                  powerpc_excp_name(excp));
+        break;
+    default:
+    excp_invalid:
+        cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+        break;
+    }
+
+    /* Sanity check */
+    if (!(env->msr_mask & MSR_HVB)) {
+        if (new_msr & MSR_HVB) {
+            cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
+                      "no HV support\n", excp);
+        }
+        if (srr0 == SPR_HSRR0) {
+            cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
+                      "no HV support\n", excp);
+        }
+    }
+
+    /*
+     * Sort out endianness of interrupt, this differs depending on the
+     * CPU, the HV mode, etc...
+     */
+    if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
+        new_msr |= (target_ulong)1 << MSR_LE;
+    }
+
+#if defined(TARGET_PPC64)
+    if (excp_model == POWERPC_EXCP_BOOKE) {
+        if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
+            /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
+            new_msr |= (target_ulong)1 << MSR_CM;
+        } else {
+            vector = (uint32_t)vector;
+        }
+    } else {
+        if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
+            vector = (uint32_t)vector;
+        } else {
+            new_msr |= (target_ulong)1 << MSR_SF;
+        }
+    }
+#endif
+
+    if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
+        /* Save PC */
+        env->spr[srr0] = env->nip;
+
+        /* Save MSR */
+        env->spr[srr1] = msr;
+    }
+
+    /* This can update new_msr and vector if AIL applies */
+    ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
+
+    powerpc_set_excp_state(cpu, vector, new_msr);
+}
+
 #ifdef TARGET_PPC64
 static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
 {
@@ -1335,6 +1806,9 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp)
     case POWERPC_EXCP_40x:
         powerpc_excp_40x(cpu, excp);
         break;
+    case POWERPC_EXCP_74xx:
+        powerpc_excp_74xx(cpu, excp);
+        break;
     case POWERPC_EXCP_970:
     case POWERPC_EXCP_POWER7:
     case POWERPC_EXCP_POWER8:
-- 
2.34.1

[PATCH v2 2/8] target/ppc: Simplify powerpc_excp_74xx

[Fabiano Rosas]

Differences from the generic powerpc_excp code:

- Not BookE, so some MSR bits are cleared at interrupt dispatch;
- No MSR_HV;
- No power saving states;
- No Hypervisor Emulation Assistance;
- Not 64 bits;
- No System call vectored;
- No Alternate Interrupt Location.

Exceptions used:

POWERPC_EXCP_ALIGN
POWERPC_EXCP_DECR
POWERPC_EXCP_DSI
POWERPC_EXCP_EXTERNAL
POWERPC_EXCP_FPU
POWERPC_EXCP_IABR
POWERPC_EXCP_ISI
POWERPC_EXCP_MCHECK
POWERPC_EXCP_PERFM
POWERPC_EXCP_PROGRAM
POWERPC_EXCP_RESET
POWERPC_EXCP_SMI
POWERPC_EXCP_SYSCALL
POWERPC_EXCP_THERM
POWERPC_EXCP_TRACE
POWERPC_EXCP_VPU
POWERPC_EXCP_VPUA

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
 target/ppc/excp_helper.c | 211 ++-------------------------------------
 1 file changed, 9 insertions(+), 202 deletions(-)

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 0e3d3ffcf4..13e5cb3ddc 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -568,54 +568,26 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
                   excp, env->error_code);
 
     /* new srr1 value excluding must-be-zero bits */
-    if (excp_model == POWERPC_EXCP_BOOKE) {
-        msr = env->msr;
-    } else {
-        msr = env->msr & ~0x783f0000ULL;
-    }
+    msr = env->msr & ~0x783f0000ULL;
 
     /*
-     * new interrupt handler msr preserves existing HV and ME unless
+     * new interrupt handler msr preserves existing ME unless
      * explicitly overriden
      */
-    new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
+    new_msr = env->msr & ((target_ulong)1 << MSR_ME);
 
     /* target registers */
     srr0 = SPR_SRR0;
     srr1 = SPR_SRR1;
 
-    /*
-     * check for special resume at 0x100 from doze/nap/sleep/winkle on
-     * P7/P8/P9
-     */
-    if (env->resume_as_sreset) {
-        excp = powerpc_reset_wakeup(cs, env, excp, &msr);
-    }
-
     /*
      * Hypervisor emulation assistance interrupt only exists on server
-     * arch 2.05 server or later. We also don't want to generate it if
-     * we don't have HVB in msr_mask (PAPR mode).
+     * arch 2.05 server or later.
      */
-    if (excp == POWERPC_EXCP_HV_EMU
-#if defined(TARGET_PPC64)
-        && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
-#endif /* defined(TARGET_PPC64) */
-
-    ) {
+    if (excp == POWERPC_EXCP_HV_EMU) {
         excp = POWERPC_EXCP_PROGRAM;
     }
 
-#ifdef TARGET_PPC64
-    /*
-     * SPEU and VPU share the same IVOR but they exist in different
-     * processors. SPEU is e500v1/2 only and VPU is e6500 only.
-     */
-    if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
-        excp = POWERPC_EXCP_SPEU;
-    }
-#endif
-
     vector = env->excp_vectors[excp];
     if (vector == (target_ulong)-1ULL) {
         cpu_abort(cs, "Raised an exception without defined vector %d\n",
@@ -625,22 +597,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
     vector |= env->excp_prefix;
 
     switch (excp) {
-    case POWERPC_EXCP_CRITICAL:    /* Critical input                         */
-        switch (excp_model) {
-        case POWERPC_EXCP_40x:
-            srr0 = SPR_40x_SRR2;
-            srr1 = SPR_40x_SRR3;
-            break;
-        case POWERPC_EXCP_BOOKE:
-            srr0 = SPR_BOOKE_CSRR0;
-            srr1 = SPR_BOOKE_CSRR1;
-            break;
-        case POWERPC_EXCP_G2:
-            break;
-        default:
-            goto excp_invalid;
-        }
-        break;
     case POWERPC_EXCP_MCHECK:    /* Machine check exception                  */
         if (msr_me == 0) {
             /*
@@ -804,63 +760,9 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
             new_msr |= (target_ulong)MSR_HVB;
         }
         break;
-    case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception                     */
-        lev = env->error_code;
-        dump_syscall(env);
-        env->nip += 4;
-        new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
-        new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
-
-        vector += lev * 0x20;
-
-        env->lr = env->nip;
-        env->ctr = msr;
-        break;
     case POWERPC_EXCP_FPU:       /* Floating-point unavailable exception     */
-    case POWERPC_EXCP_APU:       /* Auxiliary processor unavailable          */
     case POWERPC_EXCP_DECR:      /* Decrementer exception                    */
         break;
-    case POWERPC_EXCP_FIT:       /* Fixed-interval timer interrupt           */
-        /* FIT on 4xx */
-        trace_ppc_excp_print("FIT");
-        break;
-    case POWERPC_EXCP_WDT:       /* Watchdog timer interrupt                 */
-        trace_ppc_excp_print("WDT");
-        switch (excp_model) {
-        case POWERPC_EXCP_BOOKE:
-            srr0 = SPR_BOOKE_CSRR0;
-            srr1 = SPR_BOOKE_CSRR1;
-            break;
-        default:
-            break;
-        }
-        break;
-    case POWERPC_EXCP_DTLB:      /* Data TLB error                           */
-    case POWERPC_EXCP_ITLB:      /* Instruction TLB error                    */
-        break;
-    case POWERPC_EXCP_DEBUG:     /* Debug interrupt                          */
-        if (env->flags & POWERPC_FLAG_DE) {
-            /* FIXME: choose one or the other based on CPU type */
-            srr0 = SPR_BOOKE_DSRR0;
-            srr1 = SPR_BOOKE_DSRR1;
-
-            env->spr[SPR_BOOKE_CSRR0] = env->nip;
-            env->spr[SPR_BOOKE_CSRR1] = msr;
-
-            /* DBSR already modified by caller */
-        } else {
-            cpu_abort(cs, "Debug exception triggered on unsupported model\n");
-        }
-        break;
-    case POWERPC_EXCP_SPEU:   /* SPE/embedded floating-point unavailable/VPU  */
-        env->spr[SPR_BOOKE_ESR] = ESR_SPV;
-        break;
-    case POWERPC_EXCP_DOORI:     /* Embedded doorbell interrupt              */
-        break;
-    case POWERPC_EXCP_DOORCI:    /* Embedded doorbell critical interrupt     */
-        srr0 = SPR_BOOKE_CSRR0;
-        srr1 = SPR_BOOKE_CSRR1;
-        break;
     case POWERPC_EXCP_RESET:     /* System reset exception                   */
         /* A power-saving exception sets ME, otherwise it is unchanged */
         if (msr_pow) {
@@ -881,92 +783,19 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
             }
         }
         break;
-    case POWERPC_EXCP_DSEG:      /* Data segment exception                   */
-    case POWERPC_EXCP_ISEG:      /* Instruction segment exception            */
     case POWERPC_EXCP_TRACE:     /* Trace exception                          */
         break;
-    case POWERPC_EXCP_HISI:      /* Hypervisor instruction storage exception */
-        msr |= env->error_code;
-        /* fall through */
-    case POWERPC_EXCP_HDECR:     /* Hypervisor decrementer exception         */
-    case POWERPC_EXCP_HDSI:      /* Hypervisor data storage exception        */
-    case POWERPC_EXCP_HDSEG:     /* Hypervisor data segment exception        */
-    case POWERPC_EXCP_HISEG:     /* Hypervisor instruction segment exception */
-    case POWERPC_EXCP_SDOOR_HV:  /* Hypervisor Doorbell interrupt            */
-    case POWERPC_EXCP_HV_EMU:
-    case POWERPC_EXCP_HVIRT:     /* Hypervisor virtualization                */
-        srr0 = SPR_HSRR0;
-        srr1 = SPR_HSRR1;
-        new_msr |= (target_ulong)MSR_HVB;
-        new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
-        break;
     case POWERPC_EXCP_VPU:       /* Vector unavailable exception             */
-    case POWERPC_EXCP_VSXU:       /* VSX unavailable exception               */
-    case POWERPC_EXCP_FU:         /* Facility unavailable exception          */
-#ifdef TARGET_PPC64
-        env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
-#endif
         break;
-    case POWERPC_EXCP_HV_FU:     /* Hypervisor Facility Unavailable Exception */
-#ifdef TARGET_PPC64
-        env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
-        srr0 = SPR_HSRR0;
-        srr1 = SPR_HSRR1;
-        new_msr |= (target_ulong)MSR_HVB;
-        new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
-#endif
-        break;
-    case POWERPC_EXCP_PIT:       /* Programmable interval timer interrupt    */
-        trace_ppc_excp_print("PIT");
-        break;
-    case POWERPC_EXCP_IFTLB:     /* Instruction fetch TLB error              */
-    case POWERPC_EXCP_DLTLB:     /* Data load TLB miss                       */
-    case POWERPC_EXCP_DSTLB:     /* Data store TLB miss                      */
-        switch (excp_model) {
-        case POWERPC_EXCP_602:
-        case POWERPC_EXCP_603:
-        case POWERPC_EXCP_G2:
-            /* Swap temporary saved registers with GPRs */
-            if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
-                new_msr |= (target_ulong)1 << MSR_TGPR;
-                hreg_swap_gpr_tgpr(env);
-            }
-            /* fall through */
-        case POWERPC_EXCP_7x5:
-            ppc_excp_debug_sw_tlb(env, excp);
-
-            msr |= env->crf[0] << 28;
-            msr |= env->error_code; /* key, D/I, S/L bits */
-            /* Set way using a LRU mechanism */
-            msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
-            break;
-        default:
-            cpu_abort(cs, "Invalid TLB miss exception\n");
-            break;
-        }
-        break;
-    case POWERPC_EXCP_EFPDI:     /* Embedded floating-point data interrupt   */
-    case POWERPC_EXCP_EFPRI:     /* Embedded floating-point round interrupt  */
-    case POWERPC_EXCP_EPERFM:    /* Embedded performance monitor interrupt   */
-    case POWERPC_EXCP_IO:        /* IO error exception                       */
-    case POWERPC_EXCP_RUNM:      /* Run mode exception                       */
-    case POWERPC_EXCP_EMUL:      /* Emulation trap exception                 */
-    case POWERPC_EXCP_FPA:       /* Floating-point assist exception          */
-    case POWERPC_EXCP_DABR:      /* Data address breakpoint                  */
     case POWERPC_EXCP_IABR:      /* Instruction address breakpoint           */
     case POWERPC_EXCP_SMI:       /* System management interrupt              */
     case POWERPC_EXCP_THERM:     /* Thermal interrupt                        */
     case POWERPC_EXCP_PERFM:     /* Embedded performance monitor interrupt   */
     case POWERPC_EXCP_VPUA:      /* Vector assist exception                  */
-    case POWERPC_EXCP_SOFTP:     /* Soft patch exception                     */
-    case POWERPC_EXCP_MAINT:     /* Maintenance exception                    */
-    case POWERPC_EXCP_MEXTBR:    /* Maskable external breakpoint             */
-    case POWERPC_EXCP_NMEXTBR:   /* Non maskable external breakpoint         */
         cpu_abort(cs, "%s exception not implemented\n",
                   powerpc_excp_name(excp));
         break;
     default:
-    excp_invalid:
         cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
         break;
     }
@@ -991,33 +820,11 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
         new_msr |= (target_ulong)1 << MSR_LE;
     }
 
-#if defined(TARGET_PPC64)
-    if (excp_model == POWERPC_EXCP_BOOKE) {
-        if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
-            /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
-            new_msr |= (target_ulong)1 << MSR_CM;
-        } else {
-            vector = (uint32_t)vector;
-        }
-    } else {
-        if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
-            vector = (uint32_t)vector;
-        } else {
-            new_msr |= (target_ulong)1 << MSR_SF;
-        }
-    }
-#endif
+    /* Save PC */
+    env->spr[srr0] = env->nip;
 
-    if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
-        /* Save PC */
-        env->spr[srr0] = env->nip;
-
-        /* Save MSR */
-        env->spr[srr1] = msr;
-    }
-
-    /* This can update new_msr and vector if AIL applies */
-    ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
+    /* Save MSR */
+    env->spr[srr1] = msr;
 
     powerpc_set_excp_state(cpu, vector, new_msr);
 }
-- 
2.34.1

[PATCH v2 3/8] target/ppc: 74xx: Machine Check exception cleanup

[Fabiano Rosas]

The 74xx don't have an MSR_HV.

Also remove 40x and BookE code.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
 target/ppc/excp_helper.c | 24 ------------------------
 1 file changed, 24 deletions(-)

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 13e5cb3ddc..0d8c66b98f 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -612,34 +612,10 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
             cs->halted = 1;
             cpu_interrupt_exittb(cs);
         }
-        if (env->msr_mask & MSR_HVB) {
-            /*
-             * ISA specifies HV, but can be delivered to guest with HV
-             * clear (e.g., see FWNMI in PAPR).
-             */
-            new_msr |= (target_ulong)MSR_HVB;
-        }
 
         /* machine check exceptions don't have ME set */
         new_msr &= ~((target_ulong)1 << MSR_ME);
 
-        /* XXX: should also have something loaded in DAR / DSISR */
-        switch (excp_model) {
-        case POWERPC_EXCP_40x:
-            srr0 = SPR_40x_SRR2;
-            srr1 = SPR_40x_SRR3;
-            break;
-        case POWERPC_EXCP_BOOKE:
-            /* FIXME: choose one or the other based on CPU type */
-            srr0 = SPR_BOOKE_MCSRR0;
-            srr1 = SPR_BOOKE_MCSRR1;
-
-            env->spr[SPR_BOOKE_CSRR0] = env->nip;
-            env->spr[SPR_BOOKE_CSRR1] = msr;
-            break;
-        default:
-            break;
-        }
         break;
     case POWERPC_EXCP_DSI:       /* Data storage exception                   */
         trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
-- 
2.34.1

[PATCH v2 4/8] target/ppc: 74xx: External interrupt cleanup

[Fabiano Rosas]

The 74xx don't have MSR_HV so all the LPES0 logic can be removed.

Also remove the BookE IRQ code.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
 target/ppc/excp_helper.c | 38 --------------------------------------
 1 file changed, 38 deletions(-)

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 0d8c66b98f..b9a1d7ae7e 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -555,7 +555,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
 {
     CPUState *cs = CPU(cpu);
     CPUPPCState *env = &cpu->env;
-    int excp_model = env->excp_model;
     target_ulong msr, new_msr, vector;
     int srr0, srr1, lev = -1;
 
@@ -625,44 +624,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
         msr |= env->error_code;
         break;
     case POWERPC_EXCP_EXTERNAL:  /* External input                           */
-    {
-        bool lpes0;
-
-        cs = CPU(cpu);
-
-        /*
-         * Exception targeting modifiers
-         *
-         * LPES0 is supported on POWER7/8/9
-         * LPES1 is not supported (old iSeries mode)
-         *
-         * On anything else, we behave as if LPES0 is 1
-         * (externals don't alter MSR:HV)
-         */
-#if defined(TARGET_PPC64)
-        if (excp_model == POWERPC_EXCP_POWER7 ||
-            excp_model == POWERPC_EXCP_POWER8 ||
-            excp_model == POWERPC_EXCP_POWER9 ||
-            excp_model == POWERPC_EXCP_POWER10) {
-            lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
-        } else
-#endif /* defined(TARGET_PPC64) */
-        {
-            lpes0 = true;
-        }
-
-        if (!lpes0) {
-            new_msr |= (target_ulong)MSR_HVB;
-            new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
-            srr0 = SPR_HSRR0;
-            srr1 = SPR_HSRR1;
-        }
-        if (env->mpic_proxy) {
-            /* IACK the IRQ on delivery */
-            env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
-        }
         break;
-    }
     case POWERPC_EXCP_ALIGN:     /* Alignment exception                      */
         /* Get rS/rD and rA from faulting opcode */
         /*
-- 
2.34.1

[PATCH v2 5/8] target/ppc: 74xx: Program exception cleanup

[Fabiano Rosas]

Remove the BookE ESR setting.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
 target/ppc/excp_helper.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index b9a1d7ae7e..bb17b65dc0 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -650,20 +650,16 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
              * precise in the MSR.
              */
             msr |= 0x00100000;
-            env->spr[SPR_BOOKE_ESR] = ESR_FP;
             break;
         case POWERPC_EXCP_INVAL:
             trace_ppc_excp_inval(env->nip);
             msr |= 0x00080000;
-            env->spr[SPR_BOOKE_ESR] = ESR_PIL;
             break;
         case POWERPC_EXCP_PRIV:
             msr |= 0x00040000;
-            env->spr[SPR_BOOKE_ESR] = ESR_PPR;
             break;
         case POWERPC_EXCP_TRAP:
             msr |= 0x00020000;
-            env->spr[SPR_BOOKE_ESR] = ESR_PTR;
             break;
         default:
             /* Should never occur */
-- 
2.34.1

[PATCH v2 6/8] target/ppc: 74xx: System Call exception cleanup

[Fabiano Rosas]

Remove the BookE code and add a comment explaining why we need to keep
hypercall support even though this CPU does not have a hypervisor
mode.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
 target/ppc/excp_helper.c | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index bb17b65dc0..396e25ed35 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -556,7 +556,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
     CPUState *cs = CPU(cpu);
     CPUPPCState *env = &cpu->env;
     target_ulong msr, new_msr, vector;
-    int srr0, srr1, lev = -1;
+    int srr0, srr1;
 
     if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
         cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
@@ -669,7 +669,8 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
         }
         break;
     case POWERPC_EXCP_SYSCALL:   /* System call exception                    */
-        lev = env->error_code;
+    {
+        int lev = env->error_code;
 
         if ((lev == 1) && cpu->vhyp) {
             dump_hcall(env);
@@ -683,17 +684,21 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
          */
         env->nip += 4;
 
-        /* "PAPR mode" built-in hypercall emulation */
+        /*
+         * The Virtual Open Firmware (VOF) relies on the 'sc 1'
+         * instruction to communicate with QEMU. The pegasos2 machine
+         * uses VOF and the 74xx CPUs, so although the 74xx don't have
+         * HV mode, we need to keep hypercall support.
+         */
         if ((lev == 1) && cpu->vhyp) {
             PPCVirtualHypervisorClass *vhc =
                 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
             vhc->hypercall(cpu->vhyp, cpu);
             return;
         }
-        if (lev == 1) {
-            new_msr |= (target_ulong)MSR_HVB;
-        }
+
         break;
+    }
     case POWERPC_EXCP_FPU:       /* Floating-point unavailable exception     */
     case POWERPC_EXCP_DECR:      /* Decrementer exception                    */
         break;
-- 
2.34.1

[PATCH v2 7/8] target/ppc: 74xx: System Reset interrupt cleanup

[Fabiano Rosas]

The whole power saving states logic seems to be dependent on HV mode,
which don't exist for 74xx so I'm removing it all and leaving the
abort message.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
 target/ppc/excp_helper.c | 18 ++----------------
 1 file changed, 2 insertions(+), 16 deletions(-)

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 396e25ed35..b7921c0956 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -703,23 +703,9 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
     case POWERPC_EXCP_DECR:      /* Decrementer exception                    */
         break;
     case POWERPC_EXCP_RESET:     /* System reset exception                   */
-        /* A power-saving exception sets ME, otherwise it is unchanged */
         if (msr_pow) {
-            /* indicate that we resumed from power save mode */
-            msr |= 0x10000;
-            new_msr |= ((target_ulong)1 << MSR_ME);
-        }
-        if (env->msr_mask & MSR_HVB) {
-            /*
-             * ISA specifies HV, but can be delivered to guest with HV
-             * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
-             */
-            new_msr |= (target_ulong)MSR_HVB;
-        } else {
-            if (msr_pow) {
-                cpu_abort(cs, "Trying to deliver power-saving system reset "
-                          "exception %d with no HV support\n", excp);
-            }
+            cpu_abort(cs, "Trying to deliver power-saving system reset "
+                      "exception %d with no HV support\n", excp);
         }
         break;
     case POWERPC_EXCP_TRACE:     /* Trace exception                          */
-- 
2.34.1

[PATCH v2 8/8] target/ppc: 74xx: Set SRRs directly in exception code

[Fabiano Rosas]

The 74xx does not have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
 target/ppc/excp_helper.c | 13 ++-----------
 1 file changed, 2 insertions(+), 11 deletions(-)

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index b7921c0956..4e6bb87b70 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -556,7 +556,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
     CPUState *cs = CPU(cpu);
     CPUPPCState *env = &cpu->env;
     target_ulong msr, new_msr, vector;
-    int srr0, srr1;
 
     if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
         cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
@@ -575,10 +574,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
      */
     new_msr = env->msr & ((target_ulong)1 << MSR_ME);
 
-    /* target registers */
-    srr0 = SPR_SRR0;
-    srr1 = SPR_SRR1;
-
     /*
      * Hypervisor emulation assistance interrupt only exists on server
      * arch 2.05 server or later.
@@ -731,10 +726,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
             cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
                       "no HV support\n", excp);
         }
-        if (srr0 == SPR_HSRR0) {
-            cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
-                      "no HV support\n", excp);
-        }
     }
 
     /*
@@ -746,10 +737,10 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
     }
 
     /* Save PC */
-    env->spr[srr0] = env->nip;
+    env->spr[SPR_SRR0] = env->nip;
 
     /* Save MSR */
-    env->spr[srr1] = msr;
+    env->spr[SPR_SRR1] = msr;
 
     powerpc_set_excp_state(cpu, vector, new_msr);
 }
-- 
2.34.1

Re: [PATCH v2 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n)

[Mark Cave-Ayland]

On 27/01/2022 20:11, Fabiano Rosas wrote:

> Changes from v1:
> 
> - Restored the 'sc 1' support to avoid breaking the pegasos2 machine.
> 
> I tested this version in the G4 with the following OSes:
> 
> - Linux 5.15 (5.16 seems to be broken, even with master)
> - FreeBSD 13
> - Mac OS 9.2
> - Mac OS Darwin 6.0
> - Mac OS X 10.4
> - MorphOS 3.15 (-M pegasos2 and -M mac99,via=pmu)
> 
> Based on legoater/ppc-7.0
> 
> v1:
> https://lore.kernel.org/r/20220126164200.1048677-1-farosas@linux.ibm.com
> 
> Fabiano Rosas (8):
>    target/ppc: Introduce powerpc_excp_74xx
>    target/ppc: Simplify powerpc_excp_74xx
>    target/ppc: 74xx: Machine Check exception cleanup
>    target/ppc: 74xx: External interrupt cleanup
>    target/ppc: 74xx: Program exception cleanup
>    target/ppc: 74xx: System Call exception cleanup
>    target/ppc: 74xx: System Reset interrupt cleanup
>    target/ppc: 74xx: Set SRRs directly in exception code
> 
>   target/ppc/excp_helper.c | 197 +++++++++++++++++++++++++++++++++++++++
>   1 file changed, 197 insertions(+)

That certainly covers a good range MacOS images so I'm happy to give:

Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>

Just out of curiosity have you tried booting MacOS 9.2 under KVM-PR? Last time I 
tried on my G4 Mac Mini here, OS X worked fine but 9.2 failed early after jumping 
into the 68k emulator. Unfortunately due to the split real mode (see 
https://github.com/torvalds/linux/commit/c01e3f66cd5cdc1f727f4c7b0c10b3e3bdb91ba7 
where MSR_IR != MSR_DR) I can't step through with QEMU's gdbstub to see what is going 
wrong...


ATB,

Mark.

Re: [PATCH v2 6/8] target/ppc: 74xx: System Call exception cleanup

[BALATON Zoltan]

On Thu, 27 Jan 2022, Fabiano Rosas wrote:
> Remove the BookE code and add a comment explaining why we need to keep
> hypercall support even though this CPU does not have a hypervisor
> mode.

Thanks, this should do it. Just some small comments below.

> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
> ---
> target/ppc/excp_helper.c | 17 +++++++++++------
> 1 file changed, 11 insertions(+), 6 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index bb17b65dc0..396e25ed35 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -556,7 +556,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
>     CPUState *cs = CPU(cpu);
>     CPUPPCState *env = &cpu->env;
>     target_ulong msr, new_msr, vector;
> -    int srr0, srr1, lev = -1;
> +    int srr0, srr1;
>
>     if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
>         cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> @@ -669,7 +669,8 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
>         }
>         break;
>     case POWERPC_EXCP_SYSCALL:   /* System call exception                    */
> -        lev = env->error_code;
> +    {
> +        int lev = env->error_code;
>
>         if ((lev == 1) && cpu->vhyp) {

In case you'll have another version, maybe drop the extra parenthesis 
around lev == here and below...

>             dump_hcall(env);
> @@ -683,17 +684,21 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
>          */
>         env->nip += 4;
>
> -        /* "PAPR mode" built-in hypercall emulation */
> +        /*
> +         * The Virtual Open Firmware (VOF) relies on the 'sc 1'
> +         * instruction to communicate with QEMU. The pegasos2 machine
> +         * uses VOF and the 74xx CPUs, so although the 74xx don't have
> +         * HV mode, we need to keep hypercall support.
> +         */
>         if ((lev == 1) && cpu->vhyp) {

...here. Or maybe even drop the lev local variable and just use 
env->error_code in the ifs directly? Only apprears twice now so could do 
without copying it to a local. But not a big deal so it's not worth a 
respin only for this.

Regards,
BALATON Zoltan

>             PPCVirtualHypervisorClass *vhc =
>                 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
>             vhc->hypercall(cpu->vhyp, cpu);
>             return;
>         }
> -        if (lev == 1) {
> -            new_msr |= (target_ulong)MSR_HVB;
> -        }
> +
>         break;
> +    }
>     case POWERPC_EXCP_FPU:       /* Floating-point unavailable exception     */
>     case POWERPC_EXCP_DECR:      /* Decrementer exception                    */
>         break;
>

Re: [PATCH v2 8/8] target/ppc: 74xx: Set SRRs directly in exception code

[BALATON Zoltan]

On Thu, 27 Jan 2022, Fabiano Rosas wrote:
> The 74xx does not have alternate/hypervisor Save and Restore
> Registers, so we can set SRR0 and SRR1 directly.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
> ---
> target/ppc/excp_helper.c | 13 ++-----------
> 1 file changed, 2 insertions(+), 11 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index b7921c0956..4e6bb87b70 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -556,7 +556,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
>     CPUState *cs = CPU(cpu);
>     CPUPPCState *env = &cpu->env;
>     target_ulong msr, new_msr, vector;
> -    int srr0, srr1;
>
>     if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
>         cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> @@ -575,10 +574,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
>      */
>     new_msr = env->msr & ((target_ulong)1 << MSR_ME);
>
> -    /* target registers */
> -    srr0 = SPR_SRR0;
> -    srr1 = SPR_SRR1;
> -
>     /*
>      * Hypervisor emulation assistance interrupt only exists on server
>      * arch 2.05 server or later.
> @@ -731,10 +726,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
>             cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
>                       "no HV support\n", excp);
>         }

If we have ho MSR_HVB why is this still here? Shouldn't it have been gone 
in patch 2? Or is this still reachable?

Regards,
BALATON Zoltan

> -        if (srr0 == SPR_HSRR0) {
> -            cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
> -                      "no HV support\n", excp);
> -        }
>     }
>
>     /*
> @@ -746,10 +737,10 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
>     }
>
>     /* Save PC */
> -    env->spr[srr0] = env->nip;
> +    env->spr[SPR_SRR0] = env->nip;
>
>     /* Save MSR */
> -    env->spr[srr1] = msr;
> +    env->spr[SPR_SRR1] = msr;
>
>     powerpc_set_excp_state(cpu, vector, new_msr);
> }
>

Re: [PATCH v2 8/8] target/ppc: 74xx: Set SRRs directly in exception code

[BALATON Zoltan]

On Thu, 27 Jan 2022, BALATON Zoltan wrote:
> On Thu, 27 Jan 2022, Fabiano Rosas wrote:
>> The 74xx does not have alternate/hypervisor Save and Restore
>> Registers, so we can set SRR0 and SRR1 directly.
>> 
>> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
>> ---
>> target/ppc/excp_helper.c | 13 ++-----------
>> 1 file changed, 2 insertions(+), 11 deletions(-)
>> 
>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>> index b7921c0956..4e6bb87b70 100644
>> --- a/target/ppc/excp_helper.c
>> +++ b/target/ppc/excp_helper.c
>> @@ -556,7 +556,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int 
>> excp)
>>     CPUState *cs = CPU(cpu);
>>     CPUPPCState *env = &cpu->env;
>>     target_ulong msr, new_msr, vector;
>> -    int srr0, srr1;
>>
>>     if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
>>         cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
>> @@ -575,10 +574,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int 
>> excp)
>>      */
>>     new_msr = env->msr & ((target_ulong)1 << MSR_ME);
>> 
>> -    /* target registers */
>> -    srr0 = SPR_SRR0;
>> -    srr1 = SPR_SRR1;
>> -
>>     /*
>>      * Hypervisor emulation assistance interrupt only exists on server
>>      * arch 2.05 server or later.
>> @@ -731,10 +726,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int 
>> excp)
>>             cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
>>                       "no HV support\n", excp);
>>         }
>
> If we have ho MSR_HVB why is this still here? Shouldn't it have been gone in 
> patch 2? Or is this still reachable?

Additionally if it's still needed then the two ifs could be collapsed into 
one with && now that the other branch below is removed.

Regards,
BALATON Zoltan
>
>> -        if (srr0 == SPR_HSRR0) {
>> -            cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
>> -                      "no HV support\n", excp);
>> -        }
>>     }
>>
>>     /*
>> @@ -746,10 +737,10 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int 
>> excp)
>>     }
>>
>>     /* Save PC */
>> -    env->spr[srr0] = env->nip;
>> +    env->spr[SPR_SRR0] = env->nip;
>>
>>     /* Save MSR */
>> -    env->spr[srr1] = msr;
>> +    env->spr[SPR_SRR1] = msr;
>>
>>     powerpc_set_excp_state(cpu, vector, new_msr);
>> }
>> 
>
>

Re: [PATCH v2 8/8] target/ppc: 74xx: Set SRRs directly in exception code

[Fabiano Rosas]

BALATON Zoltan <balaton@eik.bme.hu> writes:

> On Thu, 27 Jan 2022, Fabiano Rosas wrote:
>> The 74xx does not have alternate/hypervisor Save and Restore
>> Registers, so we can set SRR0 and SRR1 directly.
>>
>> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
>> ---
>> target/ppc/excp_helper.c | 13 ++-----------
>> 1 file changed, 2 insertions(+), 11 deletions(-)
>>
>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>> index b7921c0956..4e6bb87b70 100644
>> --- a/target/ppc/excp_helper.c
>> +++ b/target/ppc/excp_helper.c
>> @@ -556,7 +556,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
>>     CPUState *cs = CPU(cpu);
>>     CPUPPCState *env = &cpu->env;
>>     target_ulong msr, new_msr, vector;
>> -    int srr0, srr1;
>>
>>     if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
>>         cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
>> @@ -575,10 +574,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
>>      */
>>     new_msr = env->msr & ((target_ulong)1 << MSR_ME);
>>
>> -    /* target registers */
>> -    srr0 = SPR_SRR0;
>> -    srr1 = SPR_SRR1;
>> -
>>     /*
>>      * Hypervisor emulation assistance interrupt only exists on server
>>      * arch 2.05 server or later.
>> @@ -731,10 +726,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
>>             cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
>>                       "no HV support\n", excp);
>>         }
>
> If we have ho MSR_HVB why is this still here? Shouldn't it have been gone 
> in patch 2? Or is this still reachable?

It is still reachable. Any of the individual exceptions above could set
the wrong bit. I have been keeping this block for all CPUs because I
intend to extract this sanity check to an outer function after I move
all CPU families.

In the long run I think we should validate MSR against the whole
msr_mask instead of just checking this single bit. But I am not
confident that today all the bits that are set are also present in the
corresponding location in the msr_mask.

>> -        If (srr0 == SPR_HSRR0) {
>> -            cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
>> -                      "no HV support\n", excp);
>> -        }
>>     }
>>
>>     /*
>> @@ -746,10 +737,10 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
>>     }
>>
>>     /* Save PC */
>> -    env->spr[srr0] = env->nip;
>> +    env->spr[SPR_SRR0] = env->nip;
>>
>>     /* Save MSR */
>> -    env->spr[srr1] = msr;
>> +    env->spr[SPR_SRR1] = msr;
>>
>>     powerpc_set_excp_state(cpu, vector, new_msr);
>> }
>>

Re: [PATCH v2 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n)

[BALATON Zoltan]

On Thu, 27 Jan 2022, Mark Cave-Ayland wrote:
> On 27/01/2022 20:11, Fabiano Rosas wrote:
>
>> Changes from v1:
>> 
>> - Restored the 'sc 1' support to avoid breaking the pegasos2 machine.
>> 
>> I tested this version in the G4 with the following OSes:
>> 
>> - Linux 5.15 (5.16 seems to be broken, even with master)
>> - FreeBSD 13
>> - Mac OS 9.2
>> - Mac OS Darwin 6.0
>> - Mac OS X 10.4
>> - MorphOS 3.15 (-M pegasos2 and -M mac99,via=pmu)
>> 
>> Based on legoater/ppc-7.0
>> 
>> v1:
>> https://lore.kernel.org/r/20220126164200.1048677-1-farosas@linux.ibm.com
>> 
>> Fabiano Rosas (8):
>>    target/ppc: Introduce powerpc_excp_74xx
>>    target/ppc: Simplify powerpc_excp_74xx
>>    target/ppc: 74xx: Machine Check exception cleanup
>>    target/ppc: 74xx: External interrupt cleanup
>>    target/ppc: 74xx: Program exception cleanup
>>    target/ppc: 74xx: System Call exception cleanup
>>    target/ppc: 74xx: System Reset interrupt cleanup
>>    target/ppc: 74xx: Set SRRs directly in exception code
>>
>>   target/ppc/excp_helper.c | 197 +++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 197 insertions(+)
>
> That certainly covers a good range MacOS images so I'm happy to give:
>
> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>
> Just out of curiosity have you tried booting MacOS 9.2 under KVM-PR? Last 
> time I tried on my G4 Mac Mini here, OS X worked fine but 9.2 failed early 
> after jumping into the 68k emulator. Unfortunately due to the split real mode 
> (see 
> https://github.com/torvalds/linux/commit/c01e3f66cd5cdc1f727f4c7b0c10b3e3bdb91ba7 
> where MSR_IR != MSR_DR) I can't step through with QEMU's gdbstub to see what 
> is going wrong...

Can't comment on that as I don't have PPC hardware but in case you don't 
know it yet, check out this blog entry (and its part 2):

https://www.talospace.com/2018/08/making-your-talos-ii-into-power-mac.html

which talks about running KVM-PR on POWER9 and why MacOS may not work at 
least with newer POWER CPUs. But if you run G4 code on G4 it may be a 
different problem but still an interesting article and may give you some 
ideas.

Regards,
BALATON Zoltan

Re: [PATCH v2 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n)

[Fabiano Rosas]

Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> writes:

> On 27/01/2022 20:11, Fabiano Rosas wrote:
>
>> Changes from v1:
>> 
>> - Restored the 'sc 1' support to avoid breaking the pegasos2 machine.
>> 
>> I tested this version in the G4 with the following OSes:
>> 
>> - Linux 5.15 (5.16 seems to be broken, even with master)
>> - FreeBSD 13
>> - Mac OS 9.2
>> - Mac OS Darwin 6.0
>> - Mac OS X 10.4
>> - MorphOS 3.15 (-M pegasos2 and -M mac99,via=pmu)
>> 
>> Based on legoater/ppc-7.0
>> 
>> v1:
>> https://lore.kernel.org/r/20220126164200.1048677-1-farosas@linux.ibm.com
>> 
>> Fabiano Rosas (8):
>>    target/ppc: Introduce powerpc_excp_74xx
>>    target/ppc: Simplify powerpc_excp_74xx
>>    target/ppc: 74xx: Machine Check exception cleanup
>>    target/ppc: 74xx: External interrupt cleanup
>>    target/ppc: 74xx: Program exception cleanup
>>    target/ppc: 74xx: System Call exception cleanup
>>    target/ppc: 74xx: System Reset interrupt cleanup
>>    target/ppc: 74xx: Set SRRs directly in exception code
>> 
>>   target/ppc/excp_helper.c | 197 +++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 197 insertions(+)
>
> That certainly covers a good range MacOS images so I'm happy to give:
>
> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>
> Just out of curiosity have you tried booting MacOS 9.2 under KVM-PR? Last time I 
> tried on my G4 Mac Mini here, OS X worked fine but 9.2 failed early after jumping 
> into the 68k emulator. Unfortunately due to the split real mode (see 
> https://github.com/torvalds/linux/commit/c01e3f66cd5cdc1f727f4c7b0c10b3e3bdb91ba7 
> where MSR_IR != MSR_DR) I can't step through with QEMU's gdbstub to see what is going 
> wrong...

Never crossed my mind actually. =)

I don't immediately see why the step wouldn't work due to split
mode. Let me understand that patch first. KVM-PR is full of surprises.

>
>
> ATB,
>
> Mark.

Re: [PATCH v2 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n)

[Mark Cave-Ayland]

On 27/01/2022 23:08, Fabiano Rosas wrote:

> Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> writes:
> 
>> On 27/01/2022 20:11, Fabiano Rosas wrote:
>>
>>> Changes from v1:
>>>
>>> - Restored the 'sc 1' support to avoid breaking the pegasos2 machine.
>>>
>>> I tested this version in the G4 with the following OSes:
>>>
>>> - Linux 5.15 (5.16 seems to be broken, even with master)
>>> - FreeBSD 13
>>> - Mac OS 9.2
>>> - Mac OS Darwin 6.0
>>> - Mac OS X 10.4
>>> - MorphOS 3.15 (-M pegasos2 and -M mac99,via=pmu)
>>>
>>> Based on legoater/ppc-7.0
>>>
>>> v1:
>>> https://lore.kernel.org/r/20220126164200.1048677-1-farosas@linux.ibm.com
>>>
>>> Fabiano Rosas (8):
>>>     target/ppc: Introduce powerpc_excp_74xx
>>>     target/ppc: Simplify powerpc_excp_74xx
>>>     target/ppc: 74xx: Machine Check exception cleanup
>>>     target/ppc: 74xx: External interrupt cleanup
>>>     target/ppc: 74xx: Program exception cleanup
>>>     target/ppc: 74xx: System Call exception cleanup
>>>     target/ppc: 74xx: System Reset interrupt cleanup
>>>     target/ppc: 74xx: Set SRRs directly in exception code
>>>
>>>    target/ppc/excp_helper.c | 197 +++++++++++++++++++++++++++++++++++++++
>>>    1 file changed, 197 insertions(+)
>>
>> That certainly covers a good range MacOS images so I'm happy to give:
>>
>> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>>
>> Just out of curiosity have you tried booting MacOS 9.2 under KVM-PR? Last time I
>> tried on my G4 Mac Mini here, OS X worked fine but 9.2 failed early after jumping
>> into the 68k emulator. Unfortunately due to the split real mode (see
>> https://github.com/torvalds/linux/commit/c01e3f66cd5cdc1f727f4c7b0c10b3e3bdb91ba7
>> where MSR_IR != MSR_DR) I can't step through with QEMU's gdbstub to see what is going
>> wrong...
> 
> Never crossed my mind actually. =)
> 
> I don't immediately see why the step wouldn't work due to split
> mode. Let me understand that patch first. KVM-PR is full of surprises.

IIRC from a debugging point of view the problem was that the QEMU *_debug() functions 
can't translate correctly in split mode, so if gdbstub is enabled with KVM all you 
end up seeing in gdb is junk :(


ATB,

Mark.

Re: [PATCH v2 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n)

[Cédric Le Goater]

On 1/27/22 21:11, Fabiano Rosas wrote:
> Changes from v1:
> 
> - Restored the 'sc 1' support to avoid breaking the pegasos2 machine.
> 
> I tested this version in the G4 with the following OSes:
> 
> - Linux 5.15 (5.16 seems to be broken, even with master)


Have you tried pmac32 defconfig plus these configs :

CONFIG_SERIAL_PMACZILOG=y
CONFIG_SERIAL_PMACZILOG_TTYS=y
CONFIG_SERIAL_PMACZILOG_CONSOLE=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y

5.17-rc1 looks fine with your patchset.

Thanks,

C.


> - FreeBSD 13
> - Mac OS 9.2
> - Mac OS Darwin 6.0
> - Mac OS X 10.4
> - MorphOS 3.15 (-M pegasos2 and -M mac99,via=pmu)
> 
> Based on legoater/ppc-7.0
> 
> v1:
> https://lore.kernel.org/r/20220126164200.1048677-1-farosas@linux.ibm.com
> 
> Fabiano Rosas (8):
>    target/ppc: Introduce powerpc_excp_74xx
>    target/ppc: Simplify powerpc_excp_74xx
>    target/ppc: 74xx: Machine Check exception cleanup
>    target/ppc: 74xx: External interrupt cleanup
>    target/ppc: 74xx: Program exception cleanup
>    target/ppc: 74xx: System Call exception cleanup
>    target/ppc: 74xx: System Reset interrupt cleanup
>    target/ppc: 74xx: Set SRRs directly in exception code
> 
>   target/ppc/excp_helper.c | 197 +++++++++++++++++++++++++++++++++++++++
>   1 file changed, 197 insertions(+)
>