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Wed, 18 Aug 2021 10:50:55 -0700 (PDT) Received: from [192.168.3.43] ([173.197.107.15]) by smtp.gmail.com with ESMTPSA id q26sm384894pff.174.2021.08.18.10.50.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Aug 2021 10:50:54 -0700 (PDT) Subject: Re: [PATCH v2 34/55] accel/tcg: Add cpu_{ld,st}*_mmu interfaces To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org, Peter Maydell References: <20210803041443.55452-1-richard.henderson@linaro.org> <20210803041443.55452-35-richard.henderson@linaro.org> <8feb6f2d-1c20-8f2f-d387-5e1d77be007e@amsat.org> From: Richard Henderson Message-ID: <2eb3c5a7-01b1-eb03-1800-20a01d48fa94@linaro.org> Date: Wed, 18 Aug 2021 07:50:51 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <8feb6f2d-1c20-8f2f-d387-5e1d77be007e@amsat.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.961, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/17/21 11:01 PM, Philippe Mathieu-Daudé wrote: > On 8/3/21 6:14 AM, Richard Henderson wrote: >> These functions are much closer to the softmmu helper >> functions, in that they take the complete MemOpIdx, >> and from that they may enforce required alignment. >> >> The previous cpu_ldst.h functions did not have alignment info, >> and so did not enforce it. Retain this by adding MO_UNALN to >> the MemOp that we create in calling the new functions. >> >> Signed-off-by: Richard Henderson >> --- >> docs/devel/loads-stores.rst | 52 ++++- >> include/exec/cpu_ldst.h | 245 ++++++++-------------- >> accel/tcg/cputlb.c | 392 ++++++++++++------------------------ >> accel/tcg/user-exec.c | 390 +++++++++++++++-------------------- >> accel/tcg/ldst_common.c.inc | 307 ++++++++++++++++++++++++++++ >> 5 files changed, 722 insertions(+), 664 deletions(-) >> create mode 100644 accel/tcg/ldst_common.c.inc > >> Function names follow the pattern: >> >> +load: ``cpu_ld{size}{end}_mmu(env, ptr, oi, retaddr)`` >> + >> +store: ``cpu_st{size}{end}_mmu(env, ptr, val, oi, retaddr)`` >> + >> +``size`` >> + - ``b`` : 8 bits >> + - ``w`` : 16 bits >> + - ``l`` : 32 bits >> + - ``q`` : 64 bits > > kinda unrelated to this patch, but what would be the pattern > for 128 bits? ``o`` for octoword? Yeah, that's what we've done for the 128-bit atomics. r~