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From: "Christian König" <ckoenig.leichtzumerken@gmail.com>
To: James Zhu <James.Zhu@amd.com>, amd-gfx@lists.freedesktop.org
Cc: jamesz@amd.com
Subject: Re: [PATCH v3 3/5] drm/amdgpu/vcn: add test for dec vcn software ring
Date: Thu, 19 Nov 2020 09:03:10 +0100	[thread overview]
Message-ID: <2efd5e78-cdfb-f66c-2a50-bb8aab60d8de@gmail.com> (raw)
In-Reply-To: <1605716641-22176-4-git-send-email-James.Zhu@amd.com>

Am 18.11.20 um 17:23 schrieb James Zhu:
> Add vcn software ring decode ring test and decode ib test.
>
> Signed-off-by: James Zhu <James.Zhu@amd.com>
> Reviewed-by: Leo Liu <leo.liu@amd.com>

Reviewed-by: Christian König <christian.koenig@amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 121 ++++++++++++++++++++++++++++++++
>   1 file changed, 121 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index 32251db..1c97244 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -456,6 +456,37 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
>   	return r;
>   }
>   
> +int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring)
> +{
> +	struct amdgpu_device *adev = ring->adev;
> +	uint32_t rptr;
> +	unsigned int i;
> +	int r;
> +
> +	if (amdgpu_sriov_vf(adev))
> +		return 0;
> +
> +	r = amdgpu_ring_alloc(ring, 16);
> +	if (r)
> +		return r;
> +
> +	rptr = amdgpu_ring_get_rptr(ring);
> +
> +	amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
> +	amdgpu_ring_commit(ring);
> +
> +	for (i = 0; i < adev->usec_timeout; i++) {
> +		if (amdgpu_ring_get_rptr(ring) != rptr)
> +			break;
> +		udelay(1);
> +	}
> +
> +	if (i >= adev->usec_timeout)
> +		r = -ETIMEDOUT;
> +
> +	return r;
> +}
> +
>   static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
>   				   struct amdgpu_bo *bo,
>   				   struct dma_fence **fence)
> @@ -601,6 +632,96 @@ int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
>   	return r;
>   }
>   
> +static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
> +				   struct amdgpu_bo *bo,
> +				   struct dma_fence **fence)
> +{
> +	struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
> +	const unsigned int ib_size_dw = 64;
> +	struct amdgpu_device *adev = ring->adev;
> +	struct dma_fence *f = NULL;
> +	struct amdgpu_job *job;
> +	struct amdgpu_ib *ib;
> +	uint64_t addr;
> +	int i, r;
> +
> +	r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4,
> +				AMDGPU_IB_POOL_DIRECT, &job);
> +	if (r)
> +		goto err;
> +
> +	ib = &job->ibs[0];
> +	addr = amdgpu_bo_gpu_offset(bo);
> +	ib->length_dw = 0;
> +
> +	ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8;
> +	ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER);
> +	decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]);
> +	ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4;
> +	memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer));
> +
> +	decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER);
> +	decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32);
> +	decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr);
> +
> +	for (i = ib->length_dw; i < ib_size_dw; ++i)
> +		ib->ptr[i] = 0x0;
> +
> +	r = amdgpu_job_submit_direct(job, ring, &f);
> +	if (r)
> +		goto err_free;
> +
> +	amdgpu_bo_fence(bo, f, false);
> +	amdgpu_bo_unreserve(bo);
> +	amdgpu_bo_unref(&bo);
> +
> +	if (fence)
> +		*fence = dma_fence_get(f);
> +	dma_fence_put(f);
> +
> +	return 0;
> +
> +err_free:
> +	amdgpu_job_free(job);
> +
> +err:
> +	amdgpu_bo_unreserve(bo);
> +	amdgpu_bo_unref(&bo);
> +	return r;
> +}
> +
> +int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout)
> +{
> +	struct dma_fence *fence = NULL;
> +	struct amdgpu_bo *bo;
> +	long r;
> +
> +	r = amdgpu_vcn_dec_get_create_msg(ring, 1, &bo);
> +	if (r)
> +		goto error;
> +
> +	r = amdgpu_vcn_dec_sw_send_msg(ring, bo, NULL);
> +	if (r)
> +		goto error;
> +	r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &bo);
> +	if (r)
> +		goto error;
> +
> +	r = amdgpu_vcn_dec_sw_send_msg(ring, bo, &fence);
> +	if (r)
> +		goto error;
> +
> +	r = dma_fence_wait_timeout(fence, false, timeout);
> +	if (r == 0)
> +		r = -ETIMEDOUT;
> +	else if (r > 0)
> +		r = 0;
> +
> +	dma_fence_put(fence);
> +error:
> +	return r;
> +}
> +
>   int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;

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  reply	other threads:[~2020-11-19  8:03 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-18 16:23 [PATCH v3 0/5] drm/amdgpu/vcn: support dec software ring James Zhu
2020-11-18 16:23 ` [PATCH v3 1/5] drm/amdgpu/vcn: refactor dec message functions James Zhu
2020-11-19  7:59   ` Christian König
2020-11-19 14:52     ` James Zhu
2020-11-19 14:58       ` Christian König
2020-11-19 15:37         ` James Zhu
2020-11-19 19:51           ` Christian König
2020-11-18 16:23 ` [PATCH v3 2/5] drm/amdgpu/vcn: update header to support dec vcn software ring James Zhu
2020-11-18 16:47   ` Luben Tuikov
2020-11-18 17:08     ` James Zhu
2020-11-18 16:23 ` [PATCH v3 3/5] drm/amdgpu/vcn: add test for " James Zhu
2020-11-19  8:03   ` Christian König [this message]
2020-11-18 16:24 ` [PATCH v3 4/5] drm/amdgpu/vcn3.0: add dec software ring vm functions to support James Zhu
2020-11-18 16:24 ` [PATCH v3 5/5] drm/amdgpu/vcn3.0: add software ring share memory support James Zhu

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