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[83.50.83.154]) by smtp.gmail.com with ESMTPSA id w19sm22220275pfu.47.2022.02.09.14.33.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 09 Feb 2022 14:33:47 -0800 (PST) Message-ID: <2f53c9a2-5716-5b92-a4f7-0b8495e24403@amsat.org> Date: Wed, 9 Feb 2022 23:33:43 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.5.1 Subject: Re: [PATCH 11/15] target: Use ArchCPU as interface to target CPU Content-Language: en-US To: qemu-devel@nongnu.org, Richard Henderson Cc: Paolo Bonzini , Thomas Huth References: <20220209215446.58402-1-f4bug@amsat.org> <20220209215446.58402-12-f4bug@amsat.org> In-Reply-To: <20220209215446.58402-12-f4bug@amsat.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::632 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, NICE_REPLY_A=-0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= via On 9/2/22 22:54, Philippe Mathieu-Daudé wrote: > ArchCPU is our interface with target-specific code. Use it as > a forward-declared opaque pointer (abstract type), having its > structure defined by each target. > > Signed-off-by: Philippe Mathieu-Daudé > --- > include/qemu/typedefs.h | 1 + > target/alpha/cpu-qom.h | 4 +++- > target/alpha/cpu.h | 4 +--- > target/arm/cpu-qom.h | 4 +++- > target/arm/cpu.h | 2 -- > target/avr/cpu-qom.h | 4 +++- > target/avr/cpu.h | 6 ++---- > target/cris/cpu-qom.h | 4 +++- > target/cris/cpu.h | 4 +--- > target/hexagon/cpu.h | 2 +- > target/hppa/cpu-qom.h | 4 +++- > target/hppa/cpu.h | 4 +--- > target/i386/cpu-qom.h | 4 +++- > target/i386/cpu.h | 4 +--- > target/m68k/cpu-qom.h | 4 +++- > target/m68k/cpu.h | 4 +--- > target/microblaze/cpu-qom.h | 4 +++- > target/microblaze/cpu.h | 6 +++--- > target/mips/cpu-qom.h | 4 +++- > target/mips/cpu.h | 4 +--- > target/nios2/cpu.h | 4 ++-- > target/openrisc/cpu.h | 11 ++++------- > target/ppc/cpu-qom.h | 4 +++- > target/ppc/cpu.h | 4 +--- > target/riscv/cpu.h | 5 ++--- > target/rx/cpu-qom.h | 4 +++- > target/rx/cpu.h | 4 +--- > target/s390x/cpu-qom.h | 4 +++- > target/s390x/cpu.h | 4 +--- > target/sh4/cpu-qom.h | 4 +++- > target/sh4/cpu.h | 4 +--- > target/sparc/cpu-qom.h | 4 +++- > target/sparc/cpu.h | 4 +--- > target/tricore/cpu-qom.h | 4 +++- > target/tricore/cpu.h | 4 +--- > target/xtensa/cpu-qom.h | 4 +++- > target/xtensa/cpu.h | 4 +--- > 37 files changed, 76 insertions(+), 77 deletions(-) ... > diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h > index a22bd506d0..b0a0724e8c 100644 > --- a/target/arm/cpu-qom.h > +++ b/target/arm/cpu-qom.h > @@ -27,7 +27,9 @@ struct arm_boot_info; > > #define TYPE_ARM_CPU "arm-cpu" > > -OBJECT_DECLARE_TYPE(ARMCPU, ARMCPUClass, > +typedef struct ArchCPU ARMCPU; > + > +OBJECT_DECLARE_TYPE(ArchCPU, ARMCPUClass, > ARM_CPU) > > #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index a95a070647..a137c564c4 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -3410,8 +3410,6 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) > } > } > > -typedef ARMCPU ArchCPU; > - > #include "exec/cpu-all.h" > > /* ... > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 79144ddc24..5981be47d9 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -285,7 +285,7 @@ struct CPUArchState { > uint64_t kvm_timer_frequency; > }; > > -OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, > +OBJECT_DECLARE_TYPE(ArchCPU, RISCVCPUClass, > RISCV_CPU) > > /** > @@ -309,7 +309,7 @@ struct RISCVCPUClass { > * > * A RISCV CPU. > */ > -struct RISCVCPU { > +struct ArchCPU { > /*< private >*/ > CPUState parent_obj; > /*< public >*/ > @@ -430,7 +430,6 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); > #define TB_FLAGS_MSTATUS_FS MSTATUS_FS > #define TB_FLAGS_MSTATUS_VS MSTATUS_VS > > -typedef RISCVCPU ArchCPU; > #include "exec/cpu-all.h" > > FIELD(TB_FLAGS, MEM_IDX, 0, 3) Sorry I messed while rebasing, this hunk is missing: -- >8 -- diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a137c564c4..a4bbca1812 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -774,7 +774,7 @@ typedef struct ARMISARegisters ARMISARegisters; * * An ARM CPU core. */ -struct ARMCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 05def159b1..6a243cfc06 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -171,7 +171,7 @@ struct CPUArchState { * * A Nios2 CPU. */ -struct ArchCPU { +typedef struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ @@ -188,7 +188,7 @@ struct ArchCPU { uint32_t reset_addr; uint32_t exception_addr; uint32_t fast_tlb_miss_addr; -}; +} Nios2CPU; void nios2_tcg_init(void); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5981be47d9..d8fefcbc4e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -309,7 +309,7 @@ struct RISCVCPUClass { * * A RISCV CPU. */ -struct ArchCPU { +typedef struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ @@ -357,7 +357,7 @@ struct ArchCPU { bool epmp; uint64_t resetvec; } cfg; -}; +} RISCVCPU; static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) { ---