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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id l1sm1882661ooi.48.2020.12.11.08.57.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 11 Dec 2020 08:57:52 -0800 (PST) Subject: Re: [PATCH v11 15/25] cpu: Introduce TCGCpuOperations struct From: Richard Henderson To: Claudio Fontana , Paolo Bonzini , Thomas Huth , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= References: <20201211083143.14350-1-cfontana@suse.de> <20201211083143.14350-16-cfontana@suse.de> <40394142-58e8-a1b3-0e6f-921518ea83b0@linaro.org> Message-ID: <2f667761-aa12-0a82-3d72-f31f43a184f0@linaro.org> Date: Fri, 11 Dec 2020 10:57:49 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <40394142-58e8-a1b3-0e6f-921518ea83b0@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::343; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x343.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?Q?Alex_Benn=c3=a9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Colin Xu , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/11/20 10:55 AM, Richard Henderson wrote: > On 12/11/20 2:31 AM, Claudio Fontana wrote: >> --- a/cpu.c >> +++ b/cpu.c >> @@ -174,14 +174,18 @@ void cpu_exec_initfn(CPUState *cpu) >> void cpu_exec_realizefn(CPUState *cpu, Error **errp) >> { >> CPUClass *cc = CPU_GET_CLASS(cpu); >> +#ifdef CONFIG_TCG >> static bool tcg_target_initialized; >> +#endif /* CONFIG_TCG */ >> >> cpu_list_add(cpu); >> >> +#ifdef CONFIG_TCG >> if (tcg_enabled() && !tcg_target_initialized) { >> tcg_target_initialized = true; >> - cc->tcg_initialize(); >> + cc->tcg_ops.initialize(); >> } >> +#endif /* CONFIG_TCG */ > > Not a big fan of the extra ifdefs. Are we expecting that there won't be any > more of these, that other references to cc->tcg_ops will be completely within > accel/tcg/? > > We can at least combine these two, > > #ifdef CONFIG_TCG > if (tcg_enabled()) { > static bool tcg_target_initialized; > if (!tcg_target_initialized) { > tcg_target_initialized = true; > cc->tcg_ops.initialize(); > } > } > #endif Nevermind, I now see this is cleaned up further in patch 17. Reviewed-by: Richard Henderson r~