From: Florian Fainelli <f.fainelli@gmail.com>
To: Kamal Dasu <kdasu.kdev@gmail.com>,
broonie@kernel.org, linux-spi@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: bcm-kernel-feedback-list@broadcom.com,
yendapally.reddy@broadcom.com, Kamal Dasu <kdasu@broadcom.com>
Subject: Re: [PATCH 1/3] spi: bcm-qspi: Add mspi spcr3 32/64-bits xfer mode
Date: Sun, 10 Oct 2021 19:54:05 -0700 [thread overview]
Message-ID: <30442a99-ede7-6251-ddca-8ecc577632ec@gmail.com> (raw)
In-Reply-To: <20211008203603.40915-2-kdasu.kdev@gmail.com>
On 10/8/2021 1:36 PM, Kamal Dasu wrote:
> From: Kamal Dasu <kdasu@broadcom.com>
>
> Adding 32-bits and 64-bits per transfer modes using the SPCR3
> register settings provided in MSPI controller ver >= 1.5
>
> Signed-off-by: Kamal Dasu <kdasu@broadcom.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
--
Florian
next prev parent reply other threads:[~2021-10-11 2:54 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-08 20:36 [PATCH 0/3] spi-bcm-qspi spcr3 enahancements Kamal Dasu
2021-10-08 20:36 ` [PATCH 1/3] spi: bcm-qspi: Add mspi spcr3 32/64-bits xfer mode Kamal Dasu
2021-10-11 2:54 ` Florian Fainelli [this message]
2021-10-08 20:36 ` [PATCH 2/3] spi: bcm-qspi: clear MSPI spifie interrupt during probe Kamal Dasu
2021-10-11 2:53 ` Florian Fainelli
2021-10-11 12:15 ` Mark Brown
2021-10-08 20:36 ` [PATCH 3/3] spi: bcm-qspi: add support for 3-wire mode for half duplex transfer Kamal Dasu
2021-10-11 2:54 ` Florian Fainelli
2021-10-11 17:01 ` [PATCH 0/3] spi-bcm-qspi spcr3 enahancements Mark Brown
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