[U-Boot] [PATCH 0/8] ARM: socfpga: arria10: Cleanup devicetree and

[U-Boot] [PATCH 0/8] ARM: socfpga: arria10: Cleanup devicetree and

[Dalon Westergreen]

From: Dalon Westergreen <dalon.westergreen@intel.com>

This series sync the arria10 devicetree to the kernel devicetree
and cleans up the inclusion of u-boot specific requirements.  It
also adds a new qts-filter-a10.sh script to allow for generation
of project specific settings required for configuration of the
device clocks, PLLs, and pinmux.

Dalon Westergreen (8):
  ARM: socfpga: arria10: Add qts-filter for arria10 socfpga
  ARM: socfpga: arria10: Sync A10 SoCDK devicetrees
  ARM: socfpga: arria10: Add common u-boot devicetree include
  ARM: socfpga: arria10: Add generic handoff devicetree include
  ARM: socfpga: arria10: Add handoff header for A10 SoCDK SDMMC
  ARM: socfpga: arria10: Add u-boot include for A10 SoCDK SDMMC
    devicetree
  ARM: socfpga: arria10: Remove old A10 SoCDK Handoff dtsi
  ARM: socfpga: Update README.socfpga to add qts-filter-a10

 .../dts/socfpga_arria10-common-u-boot.dtsi    | 206 +++++++++++
 arch/arm/dts/socfpga_arria10.dtsi             | 104 +++---
 .../dts/socfpga_arria10_handoff_u-boot.dtsi   | 232 +++++++++++-
 arch/arm/dts/socfpga_arria10_socdk.dtsi       |  75 ++--
 .../socfpga_arria10_socdk_sdmmc-u-boot.dtsi   |  34 ++
 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts  |  53 +--
 .../socfpga_arria10_socdk_sdmmc_handoff.dtsi  | 329 ------------------
 .../dts/socfpga_arria10_socdk_sdmmc_handoff.h | 305 ++++++++++++++++
 arch/arm/mach-socfpga/qts-filter-a10.sh       | 141 ++++++++
 doc/README.socfpga                            |  37 +-
 10 files changed, 1035 insertions(+), 481 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
 delete mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h
 create mode 100755 arch/arm/mach-socfpga/qts-filter-a10.sh

-- 
2.21.0

[U-Boot] [PATCH 1/8] ARM: socfpga: arria10: Add qts-filter for arria10 socfpga

[Dalon Westergreen]

From: Dalon Westergreen <dalon.westergreen@intel.com>

Add a script to process hps handoff data and generate a header
for inclusion in u-boot specific devicetree addons.  The header
should be included in the top level u-boot.dtsi.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
---
 arch/arm/mach-socfpga/qts-filter-a10.sh | 141 ++++++++++++++++++++++++
 1 file changed, 141 insertions(+)
 create mode 100755 arch/arm/mach-socfpga/qts-filter-a10.sh

diff --git a/arch/arm/mach-socfpga/qts-filter-a10.sh b/arch/arm/mach-socfpga/qts-filter-a10.sh
new file mode 100755
index 0000000000..ddb0d0a6f3
--- /dev/null
+++ b/arch/arm/mach-socfpga/qts-filter-a10.sh
@@ -0,0 +1,141 @@
+#!/bin/bash
+
+#
+# helper function to convert from DOS to Unix, if necessary, and handle
+# lines ending in '\'.
+#
+fix_newlines_in_macros() {
+	sed -n ':next;s/\r$//;/[^\\]\\$/ {N;s/\\\n//;b next};p' $1
+}
+
+#filter out only what we need from a10 hps.xml
+grep_a10_hps_config() {
+	egrep "clk_hz|i_clk_mgr|i_io48_pin_mux|AXI_SLAVE|AXI_MASTER"
+}
+
+#
+# Process hps.xml
+# $1:	hps.xml
+# $2:	Output File
+#
+process_a10_hps_config() {
+	hps_xml="$1"
+	outfile="$2"
+
+	(cat << EOF
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera Arria10 SoCFPGA configuration
+ */
+
+#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
+#define __SOCFPGA_ARRIA10_CONFIG_H__
+
+EOF
+
+	echo "/* Clocks */"
+	fix_newlines_in_macros \
+		${hps_xml} | egrep "clk_hz" |
+			awk -F"'" '{ gsub("\\.","_",$2) ; \
+				print "#define" " " toupper($2) " " $4}' |
+			sed 's/\.[0-9]//' |
+			sed 's/I_CLK_MGR_//' |
+			sort
+	fix_newlines_in_macros \
+		${hps_xml} | egrep "i_clk_mgr_mainpll" |
+			awk -F"'" '{ gsub("\\.","_",$2) ; \
+				print "#define" " " toupper($2) " " $4}' |
+			sed 's/\.[0-9]//' |
+			sed 's/I_CLK_MGR_//' |
+			sort
+	fix_newlines_in_macros \
+		${hps_xml} | egrep "i_clk_mgr_perpll" |
+			awk -F"'" '{ gsub("\\.","_",$2) ; \
+				print "#define" " " toupper($2) " " $4}' |
+			sed 's/\.[0-9]//' |
+			sed 's/I_CLK_MGR_//' |
+			sort
+	fix_newlines_in_macros \
+		${hps_xml} | egrep "i_clk_mgr_clkmgr" |
+			awk -F"'" '{ gsub("\\.","_",$2) ; \
+				print "#define" " " toupper($2) " " $4}' |
+			sed 's/\.[0-9]//' |
+			sed 's/I_CLK_MGR_//' |
+			sort
+	fix_newlines_in_macros \
+		${hps_xml} | egrep "i_clk_mgr_alteragrp" |
+			awk -F"'" '{ gsub("\\.","_",$2) ; \
+				print "#define" " " toupper($2) " " $4}' |
+			sed 's/\.[0-9]//' |
+			sed 's/I_CLK_MGR_//' |
+			sort
+	echo "#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \\"
+	echo "	(ALTERAGRP_MPUCLK_MAINCNT))"
+	echo "#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \\"
+	echo "	(ALTERAGRP_NOCCLK_MAINCNT))"
+
+	echo
+	echo "/* Pin Mux Configuration */"
+	fix_newlines_in_macros \
+		${hps_xml} | egrep "i_io48_pin_mux" |
+			awk -F"'" '{ gsub("\\.","_",$2) ; \
+				print "#define" " " toupper($2) " " $4}' |
+			sed 's/I_IO48_PIN_MUX_//' |
+			sed 's/SHARED_3V_IO_GRP_//' |
+			sed 's/FPGA_INTERFACE_GRP_//' |
+			sed 's/DEDICATED_IO_GRP_//' |
+			sed 's/CONFIGURATION_DEDICATED/CONFIG/' |
+			sort
+
+	echo
+	echo "/* Bridge Configuration */"
+	fix_newlines_in_macros \
+		${hps_xml} | egrep "AXI_SLAVE|AXI_MASTER" |
+			awk -F"'" '{ gsub("\\.","_",$2) ; \
+				print "#define" " " toupper($2) " " $4}' |
+			sed 's/true/1/' |
+			sed 's/false/0/' |
+			sort
+
+	echo
+	echo "/* Voltage Select for Config IO */"
+	echo "#define CONFIG_IO_BANK_VSEL \\"
+	echo "	(((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \\"
+	echo "	(CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))"
+
+	echo
+	echo "/* Macro for Config IO bit mapping */"
+	echo -n "#define CONFIG_IO_MACRO(NAME) "
+	echo "(((NAME ## _RTRIM & 0xff) << 19) | \\"
+	echo "	((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \\"
+	echo "	((NAME ## _WK_PU_EN & 0x1) << 16) | \\"
+	echo "	((NAME ## _PU_SLW_RT & 0x1) << 13) | \\"
+	echo "	((NAME ## _PU_DRV_STRG & 0xf) << 8) | \\"
+	echo "	((NAME ## _PD_SLW_RT & 0x1) << 5) | \\"
+	echo "	(NAME ## _PD_DRV_STRG & 0x1f))"
+
+	cat << EOF
+
+#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */
+EOF
+	) > "${outfile}"
+}
+
+usage() {
+	echo "$0 [hps_xml] [output_file]"
+	echo "Process QTS-generated hps.xml into devicetree header."
+	echo ""
+	echo "  hps_xml      - hps.xml file from hps_isw_handoff"
+	echo "  output_file  - Output header file for dtsi include"
+	echo ""
+}
+
+hps_xml="$1"
+outfile="$2"
+
+if [ "$#" -ne 2 ] ; then
+	usage
+	exit 1
+fi
+
+process_a10_hps_config "${hps_xml}" "${outfile}"
-- 
2.21.0

[U-Boot] [PATCH 2/8] ARM: socfpga: arria10: Sync A10 SoCDK devicetrees

[Dalon Westergreen]

From: Dalon Westergreen <dalon.westergreen@intel.com>

Sync devicetree from 5.2 kernel.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
---
 arch/arm/dts/socfpga_arria10.dtsi            | 104 ++++++++++---------
 arch/arm/dts/socfpga_arria10_socdk.dtsi      |  75 +++++++------
 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts |  53 +---------
 3 files changed, 100 insertions(+), 132 deletions(-)

diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index c11a5c0cc1..b175e05735 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -1,17 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright Altera Corporation (C) 2014. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -21,11 +10,6 @@
 	#address-cells = <1>;
 	#size-cells = <1>;
 
-	chosen {
-		tick-timer = &timer2;
-		u-boot,dm-pre-reloc;
-	};
-
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -60,7 +44,6 @@
 		device_type = "soc";
 		interrupt-parent = <&intc>;
 		ranges;
-		u-boot,dm-pre-reloc;
 
 		amba {
 			compatible = "simple-bus";
@@ -85,6 +68,7 @@
 				#dma-requests = <32>;
 				clocks = <&l4_main_clk>;
 				clock-names = "apb_pclk";
+				microcode-cached;
 			};
 		};
 
@@ -99,35 +83,29 @@
 		clkmgr at ffd04000 {
 				compatible = "altr,clk-mgr";
 				reg = <0xffd04000 0x1000>;
-				u-boot,dm-pre-reloc;
 
 				clocks {
 					#address-cells = <1>;
 					#size-cells = <0>;
-					u-boot,dm-pre-reloc;
 
 					cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
 						#clock-cells = <0>;
 						compatible = "fixed-clock";
-						u-boot,dm-pre-reloc;
 					};
 
 					cb_intosc_ls_clk: cb_intosc_ls_clk {
 						#clock-cells = <0>;
 						compatible = "fixed-clock";
-						u-boot,dm-pre-reloc;
 					};
 
 					f2s_free_clk: f2s_free_clk {
 						#clock-cells = <0>;
 						compatible = "fixed-clock";
-						u-boot,dm-pre-reloc;
 					};
 
 					osc1: osc1 {
 						#clock-cells = <0>;
 						compatible = "fixed-clock";
-						u-boot,dm-pre-reloc;
 					};
 
 					main_pll: main_pll at 40 {
@@ -138,7 +116,6 @@
 						clocks = <&osc1>, <&cb_intosc_ls_clk>,
 							 <&f2s_free_clk>;
 						reg = <0x40>;
-						u-boot,dm-pre-reloc;
 
 						main_mpu_base_clk: main_mpu_base_clk {
 							#clock-cells = <0>;
@@ -152,7 +129,6 @@
 							compatible = "altr,socfpga-a10-perip-clk";
 							clocks = <&main_pll>;
 							div-reg = <0x144 0 11>;
-							u-boot,dm-pre-reloc;
 						};
 
 						main_emaca_clk: main_emaca_clk at 68 {
@@ -228,7 +204,6 @@
 						clocks = <&osc1>, <&cb_intosc_ls_clk>,
 							 <&f2s_free_clk>, <&main_periph_ref_clk>;
 						reg = <0xC0>;
-						u-boot,dm-pre-reloc;
 
 						peri_mpu_base_clk: peri_mpu_base_clk {
 							#clock-cells = <0>;
@@ -242,7 +217,6 @@
 							compatible = "altr,socfpga-a10-perip-clk";
 							clocks = <&periph_pll>;
 							div-reg = <0x144 16 11>;
-							u-boot,dm-pre-reloc;
 						};
 
 						peri_emaca_clk: peri_emaca_clk at e8 {
@@ -318,7 +292,6 @@
 							 <&osc1>, <&cb_intosc_hs_div2_clk>,
 							 <&f2s_free_clk>;
 						reg = <0x64>;
-						u-boot,dm-pre-reloc;
 					};
 
 					s2f_user1_free_clk: s2f_user1_free_clk at 104 {
@@ -345,7 +318,6 @@
 						compatible = "altr,socfpga-a10-perip-clk";
 						clocks = <&noc_free_clk>;
 						fixed-divider = <4>;
-						u-boot,dm-pre-reloc;
 					};
 
 					l4_main_clk: l4_main_clk {
@@ -395,13 +367,28 @@
 						clk-gate = <0xC8 11>;
 					};
 
-					nand_clk: nand_clk {
+					nand_x_clk: nand_x_clk {
 						#clock-cells = <0>;
 						compatible = "altr,socfpga-a10-gate-clk";
 						clocks = <&l4_mp_clk>;
 						clk-gate = <0xC8 10>;
 					};
 
+					nand_ecc_clk: nand_ecc_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-a10-gate-clk";
+						clocks = <&nand_x_clk>;
+						clk-gate = <0xC8 10>;
+					};
+
+					nand_clk: nand_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-a10-gate-clk";
+						clocks = <&nand_x_clk>;
+						fixed-divider = <4>;
+						clk-gate = <0xC8 10>;
+					};
+
 					spi_m_clk: spi_m_clk {
 						#clock-cells = <0>;
 						compatible = "altr,socfpga-a10-gate-clk";
@@ -496,11 +483,11 @@
 			#size-cells = <0>;
 			compatible = "snps,dw-apb-gpio";
 			reg = <0xffc02900 0x100>;
+			resets = <&rst GPIO0_RESET>;
 			status = "disabled";
 
 			porta: gpio-controller at 0 {
 				compatible = "snps,dw-apb-gpio-port";
-				bank-name = "porta";
 				gpio-controller;
 				#gpio-cells = <2>;
 				snps,nr-gpios = <29>;
@@ -516,11 +503,11 @@
 			#size-cells = <0>;
 			compatible = "snps,dw-apb-gpio";
 			reg = <0xffc02a00 0x100>;
+			resets = <&rst GPIO1_RESET>;
 			status = "disabled";
 
 			portb: gpio-controller at 0 {
 				compatible = "snps,dw-apb-gpio-port";
-				bank-name = "portb";
 				gpio-controller;
 				#gpio-cells = <2>;
 				snps,nr-gpios = <29>;
@@ -536,11 +523,11 @@
 			#size-cells = <0>;
 			compatible = "snps,dw-apb-gpio";
 			reg = <0xffc02b00 0x100>;
+			resets = <&rst GPIO2_RESET>;
 			status = "disabled";
 
 			portc: gpio-controller at 0 {
 				compatible = "snps,dw-apb-gpio-port";
-				bank-name = "portc";
 				gpio-controller;
 				#gpio-cells = <2>;
 				snps,nr-gpios = <27>;
@@ -568,7 +555,6 @@
 			interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&l4_sp_clk>;
 			resets = <&rst I2C0_RESET>;
-			reset-names = "i2c";
 			status = "disabled";
 		};
 
@@ -580,7 +566,6 @@
 			interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&l4_sp_clk>;
 			resets = <&rst I2C1_RESET>;
-			reset-names = "i2c";
 			status = "disabled";
 		};
 
@@ -592,7 +577,6 @@
 			interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&l4_sp_clk>;
 			resets = <&rst I2C2_RESET>;
-			reset-names = "i2c";
 			status = "disabled";
 		};
 
@@ -604,7 +588,6 @@
 			interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&l4_sp_clk>;
 			resets = <&rst I2C3_RESET>;
-			reset-names = "i2c";
 			status = "disabled";
 		};
 
@@ -616,7 +599,19 @@
 			interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&l4_sp_clk>;
 			resets = <&rst I2C4_RESET>;
-			reset-names = "i2c";
+			status = "disabled";
+		};
+
+		spi0: spi at ffda4000 {
+			compatible = "snps,dw-apb-ssi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xffda4000 0x100>;
+			interrupts = <0 101 4>;
+			num-cs = <4>;
+			/*32bit_access;*/
+			clocks = <&spi_m_clk>;
+			resets = <&rst SPIM0_RESET>;
 			status = "disabled";
 		};
 
@@ -626,16 +621,16 @@
 			#size-cells = <0>;
 			reg = <0xffda5000 0x100>;
 			interrupts = <0 102 4>;
-			num-chipselect = <4>;
-			bus-num = <0>;
+			num-cs = <4>;
 			/*32bit_access;*/
 			tx-dma-channel = <&pdma 16>;
 			rx-dma-channel = <&pdma 17>;
 			clocks = <&spi_m_clk>;
+			resets = <&rst SPIM1_RESET>;
 			status = "disabled";
 		};
 
-		sdr: sdr at ffc25000 {
+		sdr: sdr at ffcfb100 {
 			compatible = "altr,sdr-ctl", "syscon";
 			reg = <0xffcfb100 0x80>;
 		};
@@ -667,13 +662,13 @@
 		nand: nand at ffb90000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
-			compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
-			reg = <0xffb90000 0x20>,
-			      <0xffb80000 0x1000>;
+			compatible = "altr,socfpga-denali-nand";
+			reg = <0xffb90000 0x72000>,
+			      <0xffb80000 0x10000>;
 			reg-names = "nand_data", "denali_reg";
 			interrupts = <0 99 4>;
-			dma-mask = <0xffffffff>;
-			clocks = <&nand_clk>;
+			clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
+			clock-names = "nand", "nand_x", "ecc";
 			resets = <&rst NAND_RESET>;
 			status = "disabled";
 		};
@@ -759,6 +754,7 @@
 			cdns,fifo-width = <4>;
 			cdns,trigger-address = <0x00000000>;
 			clocks = <&qspi_clk>;
+			resets = <&rst QSPI_RESET>;
 			status = "disabled";
 		};
 
@@ -767,7 +763,6 @@
 			compatible = "altr,rst-mgr";
 			reg = <0xffd05000 0x100>;
 			altr,modrst-offset = <0x20>;
-			u-boot,dm-pre-reloc;
 		};
 
 		scu: snoop-control-unit at ffffc000 {
@@ -785,7 +780,7 @@
 		timer at ffffc600 {
 			compatible = "arm,cortex-a9-twd-timer";
 			reg = <0xffffc600 0x100>;
-			interrupts = <1 13 0xf04>;
+			interrupts = <1 13 0xf01>;
 			clocks = <&mpu_periph_clk>;
 		};
 
@@ -795,6 +790,8 @@
 			reg = <0xffc02700 0x100>;
 			clocks = <&l4_sp_clk>;
 			clock-names = "timer";
+			resets = <&rst SPTIMER0_RESET>;
+			reset-names = "timer";
 		};
 
 		timer1: timer1 at ffc02800 {
@@ -803,6 +800,8 @@
 			reg = <0xffc02800 0x100>;
 			clocks = <&l4_sp_clk>;
 			clock-names = "timer";
+			resets = <&rst SPTIMER1_RESET>;
+			reset-names = "timer";
 		};
 
 		timer2: timer2 at ffd00000 {
@@ -811,7 +810,8 @@
 			reg = <0xffd00000 0x100>;
 			clocks = <&l4_sys_free_clk>;
 			clock-names = "timer";
-			u-boot,dm-pre-reloc;
+			resets = <&rst L4SYSTIMER0_RESET>;
+			reset-names = "timer";
 		};
 
 		timer3: timer3 at ffd00100 {
@@ -820,6 +820,8 @@
 			reg = <0xffd01000 0x100>;
 			clocks = <&l4_sys_free_clk>;
 			clock-names = "timer";
+			resets = <&rst L4SYSTIMER1_RESET>;
+			reset-names = "timer";
 		};
 
 		uart0: serial0 at ffc02000 {
@@ -881,6 +883,7 @@
 			reg = <0xffd00200 0x100>;
 			interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&l4_sys_free_clk>;
+			resets = <&rst L4WD0_RESET>;
 			status = "disabled";
 		};
 
@@ -889,6 +892,7 @@
 			reg = <0xffd00300 0x100>;
 			interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&l4_sys_free_clk>;
+			resets = <&rst L4WD1_RESET>;
 			status = "disabled";
 		};
 	};
diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi
index 6e5578d7bd..1ff37b89b1 100644
--- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
@@ -1,20 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2015 Altera Corporation <www.altera.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
-
 #include "socfpga_arria10.dtsi"
 
 / {
@@ -24,7 +11,6 @@
 	aliases {
 		ethernet0 = &gmac0;
 		serial0 = &uart1;
-		i2c0 = &i2c1;
 	};
 
 	chosen {
@@ -36,7 +22,6 @@
 		name = "memory";
 		device_type = "memory";
 		reg = <0x0 0x40000000>; /* 1GB */
-		u-boot,dm-pre-reloc;
 	};
 
 	a10leds {
@@ -63,8 +48,21 @@
 		};
 	};
 
+	ref_033v: 033-v-ref {
+		compatible = "regulator-fixed";
+		regulator-name = "0.33V";
+		regulator-min-microvolt = <330000>;
+		regulator-max-microvolt = <330000>;
+	};
+
 	soc {
-		u-boot,dm-pre-reloc;
+		clkmgr at ffd04000 {
+			clocks {
+				osc1 {
+					clock-frequency = <25000000>;
+				};
+			};
+		};
 	};
 };
 
@@ -123,6 +121,10 @@
 			compatible = "altr,a10sr-reset";
 			#reset-cells = <1>;
 		};
+
+		ps_alarm {
+			compatible = "altr,a10sr-hwmon";
+		};
 	};
 };
 
@@ -137,6 +139,26 @@
 	i2c-sda-falling-time-ns = <6000>;
 	i2c-scl-falling-time-ns = <6000>;
 
+	adc at 14 {
+		compatible = "lltc,ltc2497";
+		reg = <0x14>;
+		vref-supply = <&ref_033v>;
+	};
+
+	adc at 16 {
+		compatible = "lltc,ltc2497";
+		reg = <0x16>;
+		vref-supply = <&ref_033v>;
+	};
+
+	lcd: lcd at 28 {
+		compatible = "newhaven,nhd-0216k3z-nsw-bbw";
+		reg = <0x28>;
+		height = <2>;
+		width = <16>;
+		brightness = <8>;
+	};
+
 	eeprom at 51 {
 		compatible = "atmel,24c32";
 		reg = <0x51>;
@@ -148,6 +170,11 @@
 		reg = <0x68>;
 	};
 
+	max at 4c {
+		compatible = "max1619";
+		reg = <0x4c>;
+	};
+
 	ltc at 5c {
 		compatible = "ltc2977";
 		reg = <0x5c>;
@@ -155,7 +182,6 @@
 };
 
 &uart1 {
-	u-boot,dm-pre-reloc;
 	status = "okay";
 };
 
@@ -167,16 +193,3 @@
 &watchdog1 {
 	status = "okay";
 };
-
-/* Clock available early */
-&main_periph_ref_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&l4_mp_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&l4_sp_clk {
-	u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
index d6b6c2ddc0..64dc0799f3 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -1,47 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 /dts-v1/;
 #include "socfpga_arria10_socdk.dtsi"
-#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
-#include "socfpga_arria10_handoff_u-boot.dtsi"
-
-/ {
-	chosen {
-		firmware-loader = <&fs_loader0>;
-	};
-
-	fs_loader0: fs-loader {
-		u-boot,dm-pre-reloc;
-		compatible = "u-boot,fs-loader";
-		phandlepart = <&mmc 1>;
-	};
-};
-
-&fpga_mgr {
-	u-boot,dm-pre-reloc;
-	altr,bitstream = "fit_spl_fpga.itb";
-};
 
 &mmc {
-	u-boot,dm-pre-reloc;
 	status = "okay";
-	num-slots = <1>;
 	cap-sd-highspeed;
+	cap-mmc-highspeed;
 	broken-cd;
 	bus-width = <4>;
 };
@@ -57,20 +25,3 @@
 			     <48 IRQ_TYPE_LEVEL_HIGH>;
 	};
 };
-
-/* Clock available early */
-&main_sdmmc_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&peri_sdmmc_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&sdmmc_free_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&sdmmc_clk {
-	u-boot,dm-pre-reloc;
-};
-- 
2.21.0

[U-Boot] [PATCH 3/8] ARM: socfpga: arria10: Add common u-boot devicetree include

[Dalon Westergreen]

From: Dalon Westergreen <dalon.westergreen@intel.com>

Add a common u-boot devicetree include file for the SocFPGA
Arria10 device.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
---
 .../dts/socfpga_arria10-common-u-boot.dtsi    | 206 ++++++++++++++++++
 1 file changed, 206 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria10-common-u-boot.dtsi

diff --git a/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
new file mode 100644
index 0000000000..bd4f1271f3
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
@@ -0,0 +1,206 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
+ */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {
+		tick-timer = &timer2;
+		u-boot,dm-pre-reloc;
+	};
+
+	memory at 0 {
+		u-boot,dm-pre-reloc;
+	};
+
+	soc {
+		u-boot,dm-pre-reloc;
+
+		clkmgr at ffd04000 {
+			u-boot,dm-pre-reloc;
+
+			clocks {
+					u-boot,dm-pre-reloc;
+
+					cb_intosc_hs_div2_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					cb_intosc_ls_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					f2s_free_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					osc1 {
+						u-boot,dm-pre-reloc;
+					};
+
+					main_pll at 40 {
+						u-boot,dm-pre-reloc;
+
+						main_mpu_base_clk {
+							u-boot,dm-pre-reloc;
+						};
+
+						main_noc_base_clk {
+							u-boot,dm-pre-reloc;
+						};
+
+						main_emaca_clk at 68 {
+							u-boot,dm-pre-reloc;
+						};
+
+						main_emacb_clk at 6c {
+							u-boot,dm-pre-reloc;
+						};
+
+						main_emac_ptp_clk at 70 {
+							u-boot,dm-pre-reloc;
+						};
+
+						main_gpio_db_clk at 74 {
+							u-boot,dm-pre-reloc;
+						};
+
+						main_sdmmc_clk at 78 {
+							u-boot,dm-pre-reloc;
+						};
+
+						main_s2f_usr0_clk at 7c {
+							u-boot,dm-pre-reloc;
+						};
+
+						main_s2f_usr1_clk at 80 {
+							u-boot,dm-pre-reloc;
+						};
+
+						main_hmc_pll_ref_clk at 84 {
+							u-boot,dm-pre-reloc;
+						};
+
+						main_periph_ref_clk at 9c {
+							u-boot,dm-pre-reloc;
+						};
+					};
+
+					periph_pll at c0 {
+						u-boot,dm-pre-reloc;
+
+						peri_mpu_base_clk {
+							u-boot,dm-pre-reloc;
+						};
+
+						peri_noc_base_clk {
+							u-boot,dm-pre-reloc;
+						};
+
+						peri_emaca_clk at e8 {
+							u-boot,dm-pre-reloc;
+						};
+
+						peri_emacb_clk at ec {
+							u-boot,dm-pre-reloc;
+						};
+
+						peri_emac_ptp_clk at f0 {
+							u-boot,dm-pre-reloc;
+						};
+
+						peri_gpio_db_clk at f4 {
+							u-boot,dm-pre-reloc;
+						};
+
+						peri_sdmmc_clk at f8 {
+							u-boot,dm-pre-reloc;
+						};
+
+						peri_s2f_usr0_clk at fc {
+							u-boot,dm-pre-reloc;
+						};
+
+						peri_s2f_usr1_clk at 100 {
+							u-boot,dm-pre-reloc;
+						};
+
+						peri_hmc_pll_ref_clk at 104 {
+							u-boot,dm-pre-reloc;
+						};
+					};
+
+					mpu_free_clk at 60 {
+						u-boot,dm-pre-reloc;
+					};
+
+					noc_free_clk at 64 {
+						u-boot,dm-pre-reloc;
+					};
+
+					s2f_user1_free_clk at 104 {
+						u-boot,dm-pre-reloc;
+					};
+
+					sdmmc_free_clk at f8 {
+						u-boot,dm-pre-reloc;
+					};
+
+					l4_sys_free_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					l4_main_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					l4_mp_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					l4_sp_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					mpu_periph_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					sdmmc_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					qspi_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					nand_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					spi_m_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					usb_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					s2f_usr1_clk {
+						u-boot,dm-pre-reloc;
+					};
+				};
+		};
+	};
+};
+
+&rst {
+	u-boot,dm-pre-reloc;
+};
+
+&timer2 {
+	u-boot,dm-pre-reloc;
+};
-- 
2.21.0

[U-Boot] [PATCH 4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

[Dalon Westergreen]

From: Dalon Westergreen <dalon.westergreen@intel.com>

Generic handoff devicetree include uses a header generated by
the qts-filter-a10.sh script in mach-socfpga.  The script
creates the header based on design specific implementations
for clock and pinmux configurations.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
---
 .../dts/socfpga_arria10_handoff_u-boot.dtsi   | 232 ++++++++++++++++--
 1 file changed, 216 insertions(+), 16 deletions(-)

diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
index ef215230c2..69854352a0 100644
--- a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
@@ -1,91 +1,291 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 
 / {
-	chosen {
-		u-boot,dm-pre-reloc;
-	};
-
 	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
 		u-boot,dm-pre-reloc;
 
-		altera_arria10_hps_eosc1 {
+		altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <EOSC1_CLK_HZ>;
+			clock-output-names = "altera_arria10_hps_eosc1-clk";
 			u-boot,dm-pre-reloc;
 		};
 
-		altera_arria10_hps_cb_intosc_ls {
+		altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <CB_INTOSC_LS_CLK_HZ>;
+			clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
 			u-boot,dm-pre-reloc;
 		};
 
-		altera_arria10_hps_f2h_free {
+		/* Clock source: altera_arria10_hps_f2h_free */
+		altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <F2H_FREE_CLK_HZ>;
+			clock-output-names = "altera_arria10_hps_f2h_free-clk";
 			u-boot,dm-pre-reloc;
 		};
 	};
 
-	clock_manager at 0xffd04000 {
+	clkmgr at 0xffd04000 {
+		compatible = "altr,socfpga-a10-clk-init";
+		reg = <0xffd04000 0x00000200>;
+		reg-names = "soc_clock_manager_OCP_SLV";
 		u-boot,dm-pre-reloc;
 
 		mainpll {
+			vco0-psrc = <MAINPLLGRP_VCO0_PSRC>;
+			vco1-denom = <MAINPLLGRP_VCO1_DENOM>;
+			vco1-numer = <MAINPLLGRP_VCO1_NUMER>;
+			mpuclk-cnt = <MAINPLLGRP_MPUCLK_CNT>;
+			mpuclk-src = <MAINPLLGRP_MPUCLK_SRC>;
+			nocclk-cnt = <MAINPLLGRP_NOCCLK_CNT>;
+			nocclk-src = <MAINPLLGRP_NOCCLK_SRC>;
+			cntr2clk-cnt = <MAINPLLGRP_CNTR2CLK_CNT>;
+			cntr3clk-cnt = <MAINPLLGRP_CNTR3CLK_CNT>;
+			cntr4clk-cnt = <MAINPLLGRP_CNTR4CLK_CNT>;
+			cntr5clk-cnt = <MAINPLLGRP_CNTR5CLK_CNT>;
+			cntr6clk-cnt = <MAINPLLGRP_CNTR6CLK_CNT>;
+			cntr7clk-cnt = <MAINPLLGRP_CNTR7CLK_CNT>;
+			cntr7clk-src = <MAINPLLGRP_CNTR7CLK_SRC>;
+			cntr8clk-cnt = <MAINPLLGRP_CNTR8CLK_CNT>;
+			cntr9clk-cnt = <MAINPLLGRP_CNTR9CLK_CNT>;
+			cntr9clk-src = <MAINPLLGRP_CNTR9CLK_SRC>;
+			cntr15clk-cnt = <MAINPLLGRP_CNTR15CLK_CNT>;
+			nocdiv-l4mainclk = <MAINPLLGRP_NOCDIV_L4MAINCLK>;
+			nocdiv-l4mpclk = <MAINPLLGRP_NOCDIV_L4MPCLK>;
+			nocdiv-l4spclk = <MAINPLLGRP_NOCDIV_L4SPCLK>;
+			nocdiv-csatclk = <MAINPLLGRP_NOCDIV_CSATCLK>;
+			nocdiv-cstraceclk = <MAINPLLGRP_NOCDIV_CSTRACECLK>;
+			nocdiv-cspdbgclk = <MAINPLLGRP_NOCDIV_CSPDBGCLK>;
 			u-boot,dm-pre-reloc;
 		};
 
 		perpll {
+			vco0-psrc = <PERPLLGRP_VCO0_PSRC>;
+			vco1-denom = <PERPLLGRP_VCO1_DENOM>;
+			vco1-numer = <PERPLLGRP_VCO1_NUMER>;
+			cntr2clk-cnt = <PERPLLGRP_CNTR2CLK_CNT>;
+			cntr2clk-src = <PERPLLGRP_CNTR2CLK_SRC>;
+			cntr3clk-cnt = <PERPLLGRP_CNTR3CLK_CNT>;
+			cntr3clk-src = <PERPLLGRP_CNTR3CLK_SRC>;
+			cntr4clk-cnt = <PERPLLGRP_CNTR4CLK_CNT>;
+			cntr4clk-src = <PERPLLGRP_CNTR4CLK_SRC>;
+			cntr5clk-cnt = <PERPLLGRP_CNTR5CLK_CNT>;
+			cntr5clk-src = <PERPLLGRP_CNTR5CLK_SRC>;
+			cntr6clk-cnt = <PERPLLGRP_CNTR6CLK_CNT>;
+			cntr6clk-src = <PERPLLGRP_CNTR6CLK_SRC>;
+			cntr7clk-cnt = <PERPLLGRP_CNTR7CLK_CNT>;
+			cntr8clk-cnt = <PERPLLGRP_CNTR8CLK_CNT>;
+			cntr8clk-src = <PERPLLGRP_CNTR8CLK_SRC>;
+			cntr9clk-cnt = <PERPLLGRP_CNTR9CLK_CNT>;
+			emacctl-emac0sel = <PERPLLGRP_EMACCTL_EMAC0SEL>;
+			emacctl-emac1sel = <PERPLLGRP_EMACCTL_EMAC1SEL>;
+			emacctl-emac2sel = <PERPLLGRP_EMACCTL_EMAC2SEL>;
+			gpiodiv-gpiodbclk = <PERPLLGRP_GPIODIV_GPIODBCLK>;
 			u-boot,dm-pre-reloc;
 		};
 
 		alteragrp {
+			nocclk = <ALTERAGRP_NOCCLK>;
+			mpuclk = <ALTERAGRP_MPUCLK>;
 			u-boot,dm-pre-reloc;
 		};
 	};
 
-	pinmux at 0xffd07000 {
+	i_io48_pin_mux: pinmux at 0xffd07000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "pinctrl-single";
+		reg = <0xffd07000 0x00000800>;
+		reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
 		u-boot,dm-pre-reloc;
 
 		shared {
+			reg = <0xffd07000 0x00000200>;
+			pinctrl-single,register-width = <32>;
+			pinctrl-single,function-mask = <0x0000000f>;
+			pinctrl-single,pins =
+				<0x00000000 PINMUX_SHARED_IO_Q1_1_SEL>,
+				<0x00000004 PINMUX_SHARED_IO_Q1_2_SEL>,
+				<0x00000008 PINMUX_SHARED_IO_Q1_3_SEL>,
+				<0x0000000c PINMUX_SHARED_IO_Q1_4_SEL>,
+				<0x00000010 PINMUX_SHARED_IO_Q1_5_SEL>,
+				<0x00000014 PINMUX_SHARED_IO_Q1_6_SEL>,
+				<0x00000018 PINMUX_SHARED_IO_Q1_7_SEL>,
+				<0x0000001c PINMUX_SHARED_IO_Q1_8_SEL>,
+				<0x00000020 PINMUX_SHARED_IO_Q1_9_SEL>,
+				<0x00000024 PINMUX_SHARED_IO_Q1_10_SEL>,
+				<0x00000028 PINMUX_SHARED_IO_Q1_11_SEL>,
+				<0x0000002c PINMUX_SHARED_IO_Q1_12_SEL>,
+				<0x00000030 PINMUX_SHARED_IO_Q2_1_SEL>,
+				<0x00000034 PINMUX_SHARED_IO_Q2_2_SEL>,
+				<0x00000038 PINMUX_SHARED_IO_Q2_3_SEL>,
+				<0x0000003c PINMUX_SHARED_IO_Q2_4_SEL>,
+				<0x00000040 PINMUX_SHARED_IO_Q2_5_SEL>,
+				<0x00000044 PINMUX_SHARED_IO_Q2_6_SEL>,
+				<0x00000048 PINMUX_SHARED_IO_Q2_7_SEL>,
+				<0x0000004c PINMUX_SHARED_IO_Q2_8_SEL>,
+				<0x00000050 PINMUX_SHARED_IO_Q2_9_SEL>,
+				<0x00000054 PINMUX_SHARED_IO_Q2_10_SEL>,
+				<0x00000058 PINMUX_SHARED_IO_Q2_11_SEL>,
+				<0x0000005c PINMUX_SHARED_IO_Q2_12_SEL>,
+				<0x00000060 PINMUX_SHARED_IO_Q3_1_SEL>,
+				<0x00000064 PINMUX_SHARED_IO_Q3_2_SEL>,
+				<0x00000068 PINMUX_SHARED_IO_Q3_3_SEL>,
+				<0x0000006c PINMUX_SHARED_IO_Q3_4_SEL>,
+				<0x00000070 PINMUX_SHARED_IO_Q3_5_SEL>,
+				<0x00000074 PINMUX_SHARED_IO_Q3_6_SEL>,
+				<0x00000078 PINMUX_SHARED_IO_Q3_7_SEL>,
+				<0x0000007c PINMUX_SHARED_IO_Q3_8_SEL>,
+				<0x00000080 PINMUX_SHARED_IO_Q3_9_SEL>,
+				<0x00000084 PINMUX_SHARED_IO_Q3_10_SEL>,
+				<0x00000088 PINMUX_SHARED_IO_Q3_11_SEL>,
+				<0x0000008c PINMUX_SHARED_IO_Q3_12_SEL>,
+				<0x00000090 PINMUX_SHARED_IO_Q4_1_SEL>,
+				<0x00000094 PINMUX_SHARED_IO_Q4_2_SEL>,
+				<0x00000098 PINMUX_SHARED_IO_Q4_3_SEL>,
+				<0x0000009c PINMUX_SHARED_IO_Q4_4_SEL>,
+				<0x000000a0 PINMUX_SHARED_IO_Q4_5_SEL>,
+				<0x000000a4 PINMUX_SHARED_IO_Q4_6_SEL>,
+				<0x000000a8 PINMUX_SHARED_IO_Q4_7_SEL>,
+				<0x000000ac PINMUX_SHARED_IO_Q4_8_SEL>,
+				<0x000000b0 PINMUX_SHARED_IO_Q4_9_SEL>,
+				<0x000000b4 PINMUX_SHARED_IO_Q4_10_SEL>,
+				<0x000000b8 PINMUX_SHARED_IO_Q4_11_SEL>,
+				<0x000000bc PINMUX_SHARED_IO_Q4_12_SEL>;
 			u-boot,dm-pre-reloc;
 		};
 
 		dedicated {
+			reg = <0xffd07200 0x00000200>;
+			pinctrl-single,register-width = <32>;
+			pinctrl-single,function-mask = <0x0000000f>;
+			pinctrl-single,pins =
+				<0x0000000c PINMUX_DEDICATED_IO_4_SEL>,
+				<0x00000010 PINMUX_DEDICATED_IO_5_SEL>,
+				<0x00000014 PINMUX_DEDICATED_IO_6_SEL>,
+				<0x00000018 PINMUX_DEDICATED_IO_7_SEL>,
+				<0x0000001c PINMUX_DEDICATED_IO_8_SEL>,
+				<0x00000020 PINMUX_DEDICATED_IO_9_SEL>,
+				<0x00000024 PINMUX_DEDICATED_IO_10_SEL>,
+				<0x00000028 PINMUX_DEDICATED_IO_11_SEL>,
+				<0x0000002c PINMUX_DEDICATED_IO_12_SEL>,
+				<0x00000030 PINMUX_DEDICATED_IO_13_SEL>,
+				<0x00000034 PINMUX_DEDICATED_IO_14_SEL>,
+				<0x00000038 PINMUX_DEDICATED_IO_15_SEL>,
+				<0x0000003c PINMUX_DEDICATED_IO_16_SEL>,
+				<0x00000040 PINMUX_DEDICATED_IO_17_SEL>;
 			u-boot,dm-pre-reloc;
 		};
 
 		dedicated_cfg {
+			reg = <0xffd07200 0x00000200>;
+			pinctrl-single,register-width = <32>;
+			pinctrl-single,function-mask = <0x003f3f3f>;
+			pinctrl-single,pins =
+				<0x00000100 CONFIG_IO_BANK_VSEL>,
+				<0x00000104 CONFIG_IO_MACRO (CONFIG_IO_1)>,
+				<0x00000108 CONFIG_IO_MACRO (CONFIG_IO_2)>,
+				<0x0000010c CONFIG_IO_MACRO (CONFIG_IO_3)>,
+				<0x00000110 CONFIG_IO_MACRO (CONFIG_IO_4)>,
+				<0x00000114 CONFIG_IO_MACRO (CONFIG_IO_5)>,
+				<0x00000118 CONFIG_IO_MACRO (CONFIG_IO_6)>,
+				<0x0000011c CONFIG_IO_MACRO (CONFIG_IO_7)>,
+				<0x00000120 CONFIG_IO_MACRO (CONFIG_IO_8)>,
+				<0x00000124 CONFIG_IO_MACRO (CONFIG_IO_9)>,
+				<0x00000128 CONFIG_IO_MACRO (CONFIG_IO_10)>,
+				<0x0000012c CONFIG_IO_MACRO (CONFIG_IO_11)>,
+				<0x00000130 CONFIG_IO_MACRO (CONFIG_IO_12)>,
+				<0x00000134 CONFIG_IO_MACRO (CONFIG_IO_13)>,
+				<0x00000138 CONFIG_IO_MACRO (CONFIG_IO_14)>,
+				<0x0000013c CONFIG_IO_MACRO (CONFIG_IO_15)>,
+				<0x00000140 CONFIG_IO_MACRO (CONFIG_IO_16)>,
+				<0x00000144 CONFIG_IO_MACRO (CONFIG_IO_17)>;
 			u-boot,dm-pre-reloc;
 		};
 
 		fpga {
+			reg = <0xffd07400 0x00000100>;
+			pinctrl-single,register-width = <32>;
+			pinctrl-single,function-mask = <0x00000001>;
+			pinctrl-single,pins =
+				<0x00000000 PINMUX_RGMII0_USEFPGA_SEL>,
+				<0x00000004 PINMUX_RGMII1_USEFPGA_SEL>,
+				<0x00000008 PINMUX_RGMII2_USEFPGA_SEL>,
+				<0x0000000c PINMUX_I2C0_USEFPGA_SEL>,
+				<0x00000010 PINMUX_I2C1_USEFPGA_SEL>,
+				<0x00000014 PINMUX_I2CEMAC0_USEFPGA_SEL>,
+				<0x00000018 PINMUX_I2CEMAC1_USEFPGA_SEL>,
+				<0x0000001c PINMUX_I2CEMAC2_USEFPGA_SEL>,
+				<0x00000020 PINMUX_NAND_USEFPGA_SEL>,
+				<0x00000024 PINMUX_QSPI_USEFPGA_SEL>,
+				<0x00000028 PINMUX_SDMMC_USEFPGA_SEL>,
+				<0x0000002c PINMUX_SPIM0_USEFPGA_SEL>,
+				<0x00000030 PINMUX_SPIM1_USEFPGA_SEL>,
+				<0x00000034 PINMUX_SPIS0_USEFPGA_SEL>,
+				<0x00000038 PINMUX_SPIS1_USEFPGA_SEL>,
+				<0x0000003c PINMUX_UART0_USEFPGA_SEL>,
+				<0x00000040 PINMUX_UART1_USEFPGA_SEL>;
 			u-boot,dm-pre-reloc;
 		};
 	};
 
-	noc at 0xffd10000 {
+	i_noc: noc at 0xffd10000 {
+		compatible = "altr,socfpga-a10-noc";
+		reg = <0xffd10000 0x00008000>;
+		reg-names = "mpu_m0";
 		u-boot,dm-pre-reloc;
 
 		firewall {
+			mpu0 = <0x00000000 0x0000ffff>;
+			l3-0 = <0x00000000 0x0000ffff>;
+			fpga2sdram0-0 = <0x00000000 0x0000ffff>;
+			fpga2sdram1-0 = <0x00000000 0x0000ffff>;
+			fpga2sdram2-0 = <0x00000000 0x0000ffff>;
 			u-boot,dm-pre-reloc;
 		};
 	};
 
-	fpgabridge at 0 {
+	hps_fpgabridge0: fpgabridge at 0 {
+		compatible = "altr,socfpga-hps2fpga-bridge";
+		init-val = <H2F_AXI_MASTER>;
 		u-boot,dm-pre-reloc;
 	};
 
-	fpgabridge at 1 {
+	hps_fpgabridge1: fpgabridge at 1 {
+		compatible = "altr,socfpga-lwhps2fpga-bridge";
+		init-val = <LWH2F_AXI_MASTER>;
 		u-boot,dm-pre-reloc;
 	};
 
-	fpgabridge at 2 {
+	hps_fpgabridge2: fpgabridge at 2 {
+		compatible = "altr,socfpga-fpga2hps-bridge";
+		init-val = <F2H_AXI_SLAVE>;
 		u-boot,dm-pre-reloc;
 	};
 
-	fpgabridge at 3 {
+	hps_fpgabridge3: fpgabridge at 3 {
+		compatible = "altr,socfpga-fpga2sdram0-bridge";
+		init-val = <F2SDRAM0_AXI_SLAVE>;
 		u-boot,dm-pre-reloc;
 	};
 
-	fpgabridge at 4 {
+	hps_fpgabridge4: fpgabridge at 4 {
+		compatible = "altr,socfpga-fpga2sdram1-bridge";
+		init-val = <F2SDRAM1_AXI_SLAVE>;
 		u-boot,dm-pre-reloc;
 	};
 
-	fpgabridge at 5 {
+	hps_fpgabridge5: fpgabridge at 5 {
+		compatible = "altr,socfpga-fpga2sdram2-bridge";
+		init-val = <F2SDRAM2_AXI_SLAVE>;
 		u-boot,dm-pre-reloc;
 	};
 };
+
-- 
2.21.0

[U-Boot] [PATCH 5/8] ARM: socfpga: arria10: Add handoff header for A10 SoCDK SDMMC

[Dalon Westergreen]

From: Dalon Westergreen <dalon.westergreen@intel.com>

Add the qts-filter-a10.sh generated handoff data for the arria10
socdk sdmmc uboot devicetree.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
---
 .../dts/socfpga_arria10_socdk_sdmmc_handoff.h | 305 ++++++++++++++++++
 1 file changed, 305 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h

diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h
new file mode 100644
index 0000000000..3fd5555c04
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera Arria10 SoCFPGA configuration
+ */
+
+#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
+#define __SOCFPGA_ARRIA10_CONFIG_H__
+
+/* Clocks */
+#define CB_INTOSC_LS_CLK_HZ 60000000
+#define EMAC0_CLK_HZ 250000000
+#define EMAC1_CLK_HZ 250000000
+#define EMAC2_CLK_HZ 250000000
+#define EOSC1_CLK_HZ 25000000
+#define F2H_FREE_CLK_HZ 200000000
+#define H2F_USER0_CLK_HZ 400000000
+#define H2F_USER1_CLK_HZ 400000000
+#define L3_MAIN_FREE_CLK_HZ 200000000
+#define SDMMC_CLK_HZ 200000000
+#define TPIU_CLK_HZ 100000000
+#define MAINPLLGRP_CNTR15CLK_CNT 900
+#define MAINPLLGRP_CNTR2CLK_CNT 900
+#define MAINPLLGRP_CNTR3CLK_CNT 900
+#define MAINPLLGRP_CNTR4CLK_CNT 900
+#define MAINPLLGRP_CNTR5CLK_CNT 900
+#define MAINPLLGRP_CNTR6CLK_CNT 900
+#define MAINPLLGRP_CNTR7CLK_CNT 900
+#define MAINPLLGRP_CNTR7CLK_SRC 0
+#define MAINPLLGRP_CNTR8CLK_CNT 900
+#define MAINPLLGRP_CNTR9CLK_CNT 900
+#define MAINPLLGRP_CNTR9CLK_SRC 0
+#define MAINPLLGRP_MPUCLK_CNT 0
+#define MAINPLLGRP_MPUCLK_SRC 0
+#define MAINPLLGRP_NOCCLK_CNT 0
+#define MAINPLLGRP_NOCCLK_SRC 0
+#define MAINPLLGRP_NOCDIV_CSATCLK 0
+#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1
+#define MAINPLLGRP_NOCDIV_CSTRACECLK 1
+#define MAINPLLGRP_NOCDIV_L4MAINCLK 0
+#define MAINPLLGRP_NOCDIV_L4MPCLK 0
+#define MAINPLLGRP_NOCDIV_L4SPCLK 2
+#define MAINPLLGRP_VCO0_PSRC 0
+#define MAINPLLGRP_VCO1_DENOM 1
+#define MAINPLLGRP_VCO1_NUMER 191
+#define PERPLLGRP_CNTR2CLK_CNT 7
+#define PERPLLGRP_CNTR2CLK_SRC 1
+#define PERPLLGRP_CNTR3CLK_CNT 900
+#define PERPLLGRP_CNTR3CLK_SRC 1
+#define PERPLLGRP_CNTR4CLK_CNT 19
+#define PERPLLGRP_CNTR4CLK_SRC 1
+#define PERPLLGRP_CNTR5CLK_CNT 499
+#define PERPLLGRP_CNTR5CLK_SRC 1
+#define PERPLLGRP_CNTR6CLK_CNT 9
+#define PERPLLGRP_CNTR6CLK_SRC 1
+#define PERPLLGRP_CNTR7CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_SRC 0
+#define PERPLLGRP_CNTR9CLK_CNT 900
+#define PERPLLGRP_EMACCTL_EMAC0SEL 0
+#define PERPLLGRP_EMACCTL_EMAC1SEL 0
+#define PERPLLGRP_EMACCTL_EMAC2SEL 0
+#define PERPLLGRP_GPIODIV_GPIODBCLK 32000
+#define PERPLLGRP_VCO0_PSRC 0
+#define PERPLLGRP_VCO1_DENOM 1
+#define PERPLLGRP_VCO1_NUMER 159
+#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16
+#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8
+#define CLKMGR_TESTIOCTRL_PERICLKSEL 8
+#define ALTERAGRP_MPUCLK_MAINCNT 1
+#define ALTERAGRP_MPUCLK_PERICNT 900
+#define ALTERAGRP_NOCCLK_MAINCNT 11
+#define ALTERAGRP_NOCCLK_PERICNT 900
+#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \
+	(ALTERAGRP_MPUCLK_MAINCNT))
+#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \
+	(ALTERAGRP_NOCCLK_MAINCNT))
+
+/* Pin Mux Configuration */
+#define CONFIG_IO_10_INPUT_BUF_EN 0
+#define CONFIG_IO_10_PD_DRV_STRG 0
+#define CONFIG_IO_10_PD_SLW_RT 0
+#define CONFIG_IO_10_PU_DRV_STRG 0
+#define CONFIG_IO_10_PU_SLW_RT 0
+#define CONFIG_IO_10_RTRIM 1
+#define CONFIG_IO_10_WK_PU_EN 1
+#define CONFIG_IO_11_INPUT_BUF_EN 0
+#define CONFIG_IO_11_PD_DRV_STRG 0
+#define CONFIG_IO_11_PD_SLW_RT 0
+#define CONFIG_IO_11_PU_DRV_STRG 0
+#define CONFIG_IO_11_PU_SLW_RT 0
+#define CONFIG_IO_11_RTRIM 1
+#define CONFIG_IO_11_WK_PU_EN 1
+#define CONFIG_IO_12_INPUT_BUF_EN 1
+#define CONFIG_IO_12_PD_DRV_STRG 10
+#define CONFIG_IO_12_PD_SLW_RT 1
+#define CONFIG_IO_12_PU_DRV_STRG 8
+#define CONFIG_IO_12_PU_SLW_RT 1
+#define CONFIG_IO_12_RTRIM 1
+#define CONFIG_IO_12_WK_PU_EN 1
+#define CONFIG_IO_13_INPUT_BUF_EN 1
+#define CONFIG_IO_13_PD_DRV_STRG 10
+#define CONFIG_IO_13_PD_SLW_RT 1
+#define CONFIG_IO_13_PU_DRV_STRG 8
+#define CONFIG_IO_13_PU_SLW_RT 1
+#define CONFIG_IO_13_RTRIM 1
+#define CONFIG_IO_13_WK_PU_EN 1
+#define CONFIG_IO_14_INPUT_BUF_EN 1
+#define CONFIG_IO_14_PD_DRV_STRG 10
+#define CONFIG_IO_14_PD_SLW_RT 1
+#define CONFIG_IO_14_PU_DRV_STRG 8
+#define CONFIG_IO_14_PU_SLW_RT 1
+#define CONFIG_IO_14_RTRIM 1
+#define CONFIG_IO_14_WK_PU_EN 1
+#define CONFIG_IO_15_INPUT_BUF_EN 1
+#define CONFIG_IO_15_PD_DRV_STRG 10
+#define CONFIG_IO_15_PD_SLW_RT 1
+#define CONFIG_IO_15_PU_DRV_STRG 8
+#define CONFIG_IO_15_PU_SLW_RT 1
+#define CONFIG_IO_15_RTRIM 1
+#define CONFIG_IO_15_WK_PU_EN 1
+#define CONFIG_IO_16_INPUT_BUF_EN 0
+#define CONFIG_IO_16_PD_DRV_STRG 10
+#define CONFIG_IO_16_PD_SLW_RT 1
+#define CONFIG_IO_16_PU_DRV_STRG 8
+#define CONFIG_IO_16_PU_SLW_RT 1
+#define CONFIG_IO_16_RTRIM 1
+#define CONFIG_IO_16_WK_PU_EN 0
+#define CONFIG_IO_17_INPUT_BUF_EN 1
+#define CONFIG_IO_17_PD_DRV_STRG 10
+#define CONFIG_IO_17_PD_SLW_RT 1
+#define CONFIG_IO_17_PU_DRV_STRG 8
+#define CONFIG_IO_17_PU_SLW_RT 1
+#define CONFIG_IO_17_RTRIM 1
+#define CONFIG_IO_17_WK_PU_EN 0
+#define CONFIG_IO_1_INPUT_BUF_EN 1
+#define CONFIG_IO_1_PD_DRV_STRG 10
+#define CONFIG_IO_1_PD_SLW_RT 0
+#define CONFIG_IO_1_PU_DRV_STRG 8
+#define CONFIG_IO_1_PU_SLW_RT 0
+#define CONFIG_IO_1_RTRIM 1
+#define CONFIG_IO_1_WK_PU_EN 1
+#define CONFIG_IO_2_INPUT_BUF_EN 1
+#define CONFIG_IO_2_PD_DRV_STRG 10
+#define CONFIG_IO_2_PD_SLW_RT 0
+#define CONFIG_IO_2_PU_DRV_STRG 8
+#define CONFIG_IO_2_PU_SLW_RT 0
+#define CONFIG_IO_2_RTRIM 1
+#define CONFIG_IO_2_WK_PU_EN 1
+#define CONFIG_IO_3_INPUT_BUF_EN 1
+#define CONFIG_IO_3_PD_DRV_STRG 10
+#define CONFIG_IO_3_PD_SLW_RT 0
+#define CONFIG_IO_3_PU_DRV_STRG 8
+#define CONFIG_IO_3_PU_SLW_RT 0
+#define CONFIG_IO_3_RTRIM 1
+#define CONFIG_IO_3_WK_PU_EN 1
+#define CONFIG_IO_4_INPUT_BUF_EN 1
+#define CONFIG_IO_4_PD_DRV_STRG 10
+#define CONFIG_IO_4_PD_SLW_RT 1
+#define CONFIG_IO_4_PU_DRV_STRG 8
+#define CONFIG_IO_4_PU_SLW_RT 1
+#define CONFIG_IO_4_RTRIM 1
+#define CONFIG_IO_4_WK_PU_EN 0
+#define CONFIG_IO_5_INPUT_BUF_EN 1
+#define CONFIG_IO_5_PD_DRV_STRG 10
+#define CONFIG_IO_5_PD_SLW_RT 1
+#define CONFIG_IO_5_PU_DRV_STRG 8
+#define CONFIG_IO_5_PU_SLW_RT 1
+#define CONFIG_IO_5_RTRIM 1
+#define CONFIG_IO_5_WK_PU_EN 0
+#define CONFIG_IO_6_INPUT_BUF_EN 0
+#define CONFIG_IO_6_PD_DRV_STRG 10
+#define CONFIG_IO_6_PD_SLW_RT 1
+#define CONFIG_IO_6_PU_DRV_STRG 8
+#define CONFIG_IO_6_PU_SLW_RT 1
+#define CONFIG_IO_6_RTRIM 1
+#define CONFIG_IO_6_WK_PU_EN 0
+#define CONFIG_IO_7_INPUT_BUF_EN 1
+#define CONFIG_IO_7_PD_DRV_STRG 10
+#define CONFIG_IO_7_PD_SLW_RT 1
+#define CONFIG_IO_7_PU_DRV_STRG 8
+#define CONFIG_IO_7_PU_SLW_RT 1
+#define CONFIG_IO_7_RTRIM 1
+#define CONFIG_IO_7_WK_PU_EN 0
+#define CONFIG_IO_8_INPUT_BUF_EN 1
+#define CONFIG_IO_8_PD_DRV_STRG 10
+#define CONFIG_IO_8_PD_SLW_RT 1
+#define CONFIG_IO_8_PU_DRV_STRG 8
+#define CONFIG_IO_8_PU_SLW_RT 1
+#define CONFIG_IO_8_RTRIM 1
+#define CONFIG_IO_8_WK_PU_EN 0
+#define CONFIG_IO_9_INPUT_BUF_EN 1
+#define CONFIG_IO_9_PD_DRV_STRG 10
+#define CONFIG_IO_9_PD_SLW_RT 1
+#define CONFIG_IO_9_PU_DRV_STRG 8
+#define CONFIG_IO_9_PU_SLW_RT 1
+#define CONFIG_IO_9_RTRIM 1
+#define CONFIG_IO_9_WK_PU_EN 0
+#define CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
+#define CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
+#define PINMUX_DEDICATED_IO_10_SEL 10
+#define PINMUX_DEDICATED_IO_11_SEL 10
+#define PINMUX_DEDICATED_IO_12_SEL 8
+#define PINMUX_DEDICATED_IO_13_SEL 8
+#define PINMUX_DEDICATED_IO_14_SEL 8
+#define PINMUX_DEDICATED_IO_15_SEL 8
+#define PINMUX_DEDICATED_IO_16_SEL 13
+#define PINMUX_DEDICATED_IO_17_SEL 13
+#define PINMUX_DEDICATED_IO_4_SEL 8
+#define PINMUX_DEDICATED_IO_5_SEL 8
+#define PINMUX_DEDICATED_IO_6_SEL 8
+#define PINMUX_DEDICATED_IO_7_SEL 8
+#define PINMUX_DEDICATED_IO_8_SEL 8
+#define PINMUX_DEDICATED_IO_9_SEL 8
+#define PINMUX_I2C0_USEFPGA_SEL 0
+#define PINMUX_I2C1_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC0_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC1_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC2_USEFPGA_SEL 0
+#define PINMUX_NAND_USEFPGA_SEL 0
+#define PINMUX_PLL_CLOCK_OUT_USEFPGA_SEL 0
+#define PINMUX_QSPI_USEFPGA_SEL 0
+#define PINMUX_RGMII0_USEFPGA_SEL 0
+#define PINMUX_RGMII1_USEFPGA_SEL 0
+#define PINMUX_RGMII2_USEFPGA_SEL 0
+#define PINMUX_SDMMC_USEFPGA_SEL 0
+#define PINMUX_SHARED_IO_Q1_10_SEL 8
+#define PINMUX_SHARED_IO_Q1_11_SEL 8
+#define PINMUX_SHARED_IO_Q1_12_SEL 8
+#define PINMUX_SHARED_IO_Q1_1_SEL 8
+#define PINMUX_SHARED_IO_Q1_2_SEL 8
+#define PINMUX_SHARED_IO_Q1_3_SEL 8
+#define PINMUX_SHARED_IO_Q1_4_SEL 8
+#define PINMUX_SHARED_IO_Q1_5_SEL 8
+#define PINMUX_SHARED_IO_Q1_6_SEL 8
+#define PINMUX_SHARED_IO_Q1_7_SEL 8
+#define PINMUX_SHARED_IO_Q1_8_SEL 8
+#define PINMUX_SHARED_IO_Q1_9_SEL 8
+#define PINMUX_SHARED_IO_Q2_10_SEL 4
+#define PINMUX_SHARED_IO_Q2_11_SEL 4
+#define PINMUX_SHARED_IO_Q2_12_SEL 4
+#define PINMUX_SHARED_IO_Q2_1_SEL 4
+#define PINMUX_SHARED_IO_Q2_2_SEL 4
+#define PINMUX_SHARED_IO_Q2_3_SEL 4
+#define PINMUX_SHARED_IO_Q2_4_SEL 4
+#define PINMUX_SHARED_IO_Q2_5_SEL 4
+#define PINMUX_SHARED_IO_Q2_6_SEL 4
+#define PINMUX_SHARED_IO_Q2_7_SEL 4
+#define PINMUX_SHARED_IO_Q2_8_SEL 4
+#define PINMUX_SHARED_IO_Q2_9_SEL 4
+#define PINMUX_SHARED_IO_Q3_10_SEL 10
+#define PINMUX_SHARED_IO_Q3_11_SEL 1
+#define PINMUX_SHARED_IO_Q3_12_SEL 1
+#define PINMUX_SHARED_IO_Q3_1_SEL 3
+#define PINMUX_SHARED_IO_Q3_2_SEL 3
+#define PINMUX_SHARED_IO_Q3_3_SEL 3
+#define PINMUX_SHARED_IO_Q3_4_SEL 3
+#define PINMUX_SHARED_IO_Q3_5_SEL 3
+#define PINMUX_SHARED_IO_Q3_6_SEL 15
+#define PINMUX_SHARED_IO_Q3_7_SEL 10
+#define PINMUX_SHARED_IO_Q3_8_SEL 10
+#define PINMUX_SHARED_IO_Q3_9_SEL 10
+#define PINMUX_SHARED_IO_Q4_10_SEL 12
+#define PINMUX_SHARED_IO_Q4_11_SEL 12
+#define PINMUX_SHARED_IO_Q4_12_SEL 12
+#define PINMUX_SHARED_IO_Q4_1_SEL 0
+#define PINMUX_SHARED_IO_Q4_2_SEL 0
+#define PINMUX_SHARED_IO_Q4_3_SEL 15
+#define PINMUX_SHARED_IO_Q4_4_SEL 12
+#define PINMUX_SHARED_IO_Q4_5_SEL 15
+#define PINMUX_SHARED_IO_Q4_6_SEL 15
+#define PINMUX_SHARED_IO_Q4_7_SEL 10
+#define PINMUX_SHARED_IO_Q4_8_SEL 10
+#define PINMUX_SHARED_IO_Q4_9_SEL 12
+#define PINMUX_SPIM0_USEFPGA_SEL 0
+#define PINMUX_SPIM1_USEFPGA_SEL 0
+#define PINMUX_SPIS0_USEFPGA_SEL 0
+#define PINMUX_SPIS1_USEFPGA_SEL 0
+#define PINMUX_UART0_USEFPGA_SEL 0
+#define PINMUX_UART1_USEFPGA_SEL 0
+#define PINMUX_USB0_USEFPGA_SEL 0
+#define PINMUX_USB1_USEFPGA_SEL 0
+
+/* Bridge Configuration */
+#define F2H_AXI_SLAVE 1
+#define F2SDRAM0_AXI_SLAVE 1
+#define F2SDRAM1_AXI_SLAVE 0
+#define F2SDRAM2_AXI_SLAVE 1
+#define H2F_AXI_MASTER 1
+#define LWH2F_AXI_MASTER 1
+
+/* Voltage Select for Config IO */
+#define CONFIG_IO_BANK_VSEL \
+	(((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
+	(CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
+
+/* Macro for Config IO bit mapping */
+#define CONFIG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
+	((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \
+	((NAME ## _WK_PU_EN & 0x1) << 16) | \
+	((NAME ## _PU_SLW_RT & 0x1) << 13) | \
+	((NAME ## _PU_DRV_STRG & 0xf) << 8) | \
+	((NAME ## _PD_SLW_RT & 0x1) << 5) | \
+	(NAME ## _PD_DRV_STRG & 0x1f))
+
+#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */
-- 
2.21.0

[U-Boot] [PATCH 6/8] ARM: socfpga: arria10: Add u-boot include for A10 SoCDK SDMMC devicetree

[Dalon Westergreen]

From: Dalon Westergreen <dalon.westergreen@intel.com>

Rather then modifying the devicetree to add u-boot specific
requirements, use the -u-boot.dtsi convention to allow
binman to merge the devicetree appropriately.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
---
 .../socfpga_arria10_socdk_sdmmc-u-boot.dtsi   | 34 +++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi

diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
new file mode 100644
index 0000000000..3f41b1950b
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
+ */
+
+#include <socfpga_arria10_socdk_sdmmc_handoff.h>
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+#include "socfpga_arria10-common-u-boot.dtsi"
+
+/ {
+	chosen {
+		firmware-loader = <&fs_loader0>;
+	};
+
+	fs_loader0: fs-loader {
+		u-boot,dm-pre-reloc;
+		compatible = "u-boot,fs-loader";
+		phandlepart = <&mmc 1>;
+	};
+};
+
+&fpga_mgr {
+	u-boot,dm-pre-reloc;
+	altr,bitstream = "fit_spl_fpga.itb";
+};
+
+&mmc {
+	u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+	u-boot,dm-pre-reloc;
+};
+
-- 
2.21.0

[U-Boot] [PATCH 7/8] ARM: socfpga: arria10: Remove old A10 SoCDK Handoff dtsi

[Dalon Westergreen]

From: Dalon Westergreen <dalon.westergreen@intel.com>

This file is no longer needed and has been replaced with
socfpga_arria10_handoff_u-boot.dtsi and a generated header.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
---
 .../socfpga_arria10_socdk_sdmmc_handoff.dtsi  | 329 ------------------
 1 file changed, 329 deletions(-)
 delete mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi

diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
deleted file mode 100644
index 60c419251b..0000000000
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
+++ /dev/null
@@ -1,329 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright (C) 2016-2017 Intel Corporation
- *
- *<auto-generated>
- *	This code was generated by a tool based on
- *	handoffs from both Qsys and Quartus.
- *
- *	Changes to this file may be lost if
- *	the code is regenerated.
- *</auto-generated>
- */
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-	model = "SOCFPGA Arria10 Dev Kit";	/* Bootloader setting: uboot.model */
-
-	/* Clock sources */
-	clocks {
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		/* Clock source: altera_arria10_hps_eosc1 */
-		altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <25000000>;
-			clock-output-names = "altera_arria10_hps_eosc1-clk";
-		};
-
-		/* Clock source: altera_arria10_hps_cb_intosc_ls */
-		altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <60000000>;
-			clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
-		};
-
-		/* Clock source: altera_arria10_hps_f2h_free */
-		altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-			clock-output-names = "altera_arria10_hps_f2h_free-clk";
-		};
-	};
-
-	/*
-	 * Driver: altera_arria10_soc_clock_manager_arria10_uboot_driver
-	 * Version: 1.0
-	 * Binding: device
-	 */
-	i_clk_mgr: clock_manager at 0xffd04000 {
-		compatible = "altr,socfpga-a10-clk-init";
-		reg = <0xffd04000 0x00000200>;
-		reg-names = "soc_clock_manager_OCP_SLV";
-
-		/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */
-		mainpll {
-			vco0-psrc = <0>;	/* Field: vco0.psrc */
-			vco1-denom = <1>;	/* Field: vco1.denom */
-			vco1-numer = <191>;	/* Field: vco1.numer */
-			mpuclk-cnt = <0>;	/* Field: mpuclk.cnt */
-			mpuclk-src = <0>;	/* Field: mpuclk.src */
-			nocclk-cnt = <0>;	/* Field: nocclk.cnt */
-			nocclk-src = <0>;	/* Field: nocclk.src */
-			cntr2clk-cnt = <900>;	/* Field: cntr2clk.cnt */
-			cntr3clk-cnt = <900>;	/* Field: cntr3clk.cnt */
-			cntr4clk-cnt = <900>;	/* Field: cntr4clk.cnt */
-			cntr5clk-cnt = <900>;	/* Field: cntr5clk.cnt */
-			cntr6clk-cnt = <900>;	/* Field: cntr6clk.cnt */
-			cntr7clk-cnt = <900>;	/* Field: cntr7clk.cnt */
-			cntr7clk-src = <0>;	/* Field: cntr7clk.src */
-			cntr8clk-cnt = <900>;	/* Field: cntr8clk.cnt */
-			cntr9clk-cnt = <900>;	/* Field: cntr9clk.cnt */
-			cntr9clk-src = <0>;	/* Field: cntr9clk.src */
-			cntr15clk-cnt = <900>;	/* Field: cntr15clk.cnt */
-			nocdiv-l4mainclk = <0>;	/* Field: nocdiv.l4mainclk */
-			nocdiv-l4mpclk = <0>;	/* Field: nocdiv.l4mpclk */
-			nocdiv-l4spclk = <2>;	/* Field: nocdiv.l4spclk */
-			nocdiv-csatclk = <0>;	/* Field: nocdiv.csatclk */
-			nocdiv-cstraceclk = <1>;	/* Field: nocdiv.cstraceclk */
-			nocdiv-cspdbgclk = <1>;	/* Field: nocdiv.cspdbgclk */
-		};
-
-		/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp */
-		perpll {
-			vco0-psrc = <0>;	/* Field: vco0.psrc */
-			vco1-denom = <1>;	/* Field: vco1.denom */
-			vco1-numer = <159>;	/* Field: vco1.numer */
-			cntr2clk-cnt = <7>;	/* Field: cntr2clk.cnt */
-			cntr2clk-src = <1>;	/* Field: cntr2clk.src */
-			cntr3clk-cnt = <900>;	/* Field: cntr3clk.cnt */
-			cntr3clk-src = <1>;	/* Field: cntr3clk.src */
-			cntr4clk-cnt = <19>;	/* Field: cntr4clk.cnt */
-			cntr4clk-src = <1>;	/* Field: cntr4clk.src */
-			cntr5clk-cnt = <499>;	/* Field: cntr5clk.cnt */
-			cntr5clk-src = <1>;	/* Field: cntr5clk.src */
-			cntr6clk-cnt = <9>;	/* Field: cntr6clk.cnt */
-			cntr6clk-src = <1>;	/* Field: cntr6clk.src */
-			cntr7clk-cnt = <900>;	/* Field: cntr7clk.cnt */
-			cntr8clk-cnt = <900>;	/* Field: cntr8clk.cnt */
-			cntr8clk-src = <0>;	/* Field: cntr8clk.src */
-			cntr9clk-cnt = <900>;	/* Field: cntr9clk.cnt */
-			emacctl-emac0sel = <0>;	/* Field: emacctl.emac0sel */
-			emacctl-emac1sel = <0>;	/* Field: emacctl.emac1sel */
-			emacctl-emac2sel = <0>;	/* Field: emacctl.emac2sel */
-			gpiodiv-gpiodbclk = <32000>;	/* Field: gpiodiv.gpiodbclk */
-		};
-
-		/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp */
-		alteragrp {
-			nocclk = <0x0384000b>;	/* Register: nocclk */
-			mpuclk = <0x03840001>;	/* Register: mpuclk */
-		};
-	};
-
-	/*
-	 * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver
-	 * Version: 1.0
-	 * Binding: pinmux
-	 */
-	i_io48_pin_mux: pinmux at 0xffd07000 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "pinctrl-single";
-		reg = <0xffd07000 0x00000800>;
-		reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
-
-		/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp */
-		shared {
-			reg = <0xffd07000 0x00000200>;
-			pinctrl-single,register-width = <32>;
-			pinctrl-single,function-mask = <0x0000000f>;
-			pinctrl-single,pins =
-				<0x00000000 0x00000008>,	/* Register: pinmux_shared_io_q1_1 */
-				<0x00000004 0x00000008>,	/* Register: pinmux_shared_io_q1_2 */
-				<0x00000008 0x00000008>,	/* Register: pinmux_shared_io_q1_3 */
-				<0x0000000c 0x00000008>,	/* Register: pinmux_shared_io_q1_4 */
-				<0x00000010 0x00000008>,	/* Register: pinmux_shared_io_q1_5 */
-				<0x00000014 0x00000008>,	/* Register: pinmux_shared_io_q1_6 */
-				<0x00000018 0x00000008>,	/* Register: pinmux_shared_io_q1_7 */
-				<0x0000001c 0x00000008>,	/* Register: pinmux_shared_io_q1_8 */
-				<0x00000020 0x00000008>,	/* Register: pinmux_shared_io_q1_9 */
-				<0x00000024 0x00000008>,	/* Register: pinmux_shared_io_q1_10 */
-				<0x00000028 0x00000008>,	/* Register: pinmux_shared_io_q1_11 */
-				<0x0000002c 0x00000008>,	/* Register: pinmux_shared_io_q1_12 */
-				<0x00000030 0x00000004>,	/* Register: pinmux_shared_io_q2_1 */
-				<0x00000034 0x00000004>,	/* Register: pinmux_shared_io_q2_2 */
-				<0x00000038 0x00000004>,	/* Register: pinmux_shared_io_q2_3 */
-				<0x0000003c 0x00000004>,	/* Register: pinmux_shared_io_q2_4 */
-				<0x00000040 0x00000004>,	/* Register: pinmux_shared_io_q2_5 */
-				<0x00000044 0x00000004>,	/* Register: pinmux_shared_io_q2_6 */
-				<0x00000048 0x00000004>,	/* Register: pinmux_shared_io_q2_7 */
-				<0x0000004c 0x00000004>,	/* Register: pinmux_shared_io_q2_8 */
-				<0x00000050 0x00000004>,	/* Register: pinmux_shared_io_q2_9 */
-				<0x00000054 0x00000004>,	/* Register: pinmux_shared_io_q2_10 */
-				<0x00000058 0x00000004>,	/* Register: pinmux_shared_io_q2_11 */
-				<0x0000005c 0x00000004>,	/* Register: pinmux_shared_io_q2_12 */
-				<0x00000060 0x00000003>,	/* Register: pinmux_shared_io_q3_1 */
-				<0x00000064 0x00000003>,	/* Register: pinmux_shared_io_q3_2 */
-				<0x00000068 0x00000003>,	/* Register: pinmux_shared_io_q3_3 */
-				<0x0000006c 0x00000003>,	/* Register: pinmux_shared_io_q3_4 */
-				<0x00000070 0x00000003>,	/* Register: pinmux_shared_io_q3_5 */
-				<0x00000074 0x0000000f>,	/* Register: pinmux_shared_io_q3_6 */
-				<0x00000078 0x0000000a>,	/* Register: pinmux_shared_io_q3_7 */
-				<0x0000007c 0x0000000a>,	/* Register: pinmux_shared_io_q3_8 */
-				<0x00000080 0x0000000a>,	/* Register: pinmux_shared_io_q3_9 */
-				<0x00000084 0x0000000a>,	/* Register: pinmux_shared_io_q3_10 */
-				<0x00000088 0x00000001>,	/* Register: pinmux_shared_io_q3_11 */
-				<0x0000008c 0x00000001>,	/* Register: pinmux_shared_io_q3_12 */
-				<0x00000090 0x00000000>,	/* Register: pinmux_shared_io_q4_1 */
-				<0x00000094 0x00000000>,	/* Register: pinmux_shared_io_q4_2 */
-				<0x00000098 0x0000000f>,	/* Register: pinmux_shared_io_q4_3 */
-				<0x0000009c 0x0000000c>,	/* Register: pinmux_shared_io_q4_4 */
-				<0x000000a0 0x0000000f>,	/* Register: pinmux_shared_io_q4_5 */
-				<0x000000a4 0x0000000f>,	/* Register: pinmux_shared_io_q4_6 */
-				<0x000000a8 0x0000000a>,	/* Register: pinmux_shared_io_q4_7 */
-				<0x000000ac 0x0000000a>,	/* Register: pinmux_shared_io_q4_8 */
-				<0x000000b0 0x0000000c>,	/* Register: pinmux_shared_io_q4_9 */
-				<0x000000b4 0x0000000c>,	/* Register: pinmux_shared_io_q4_10 */
-				<0x000000b8 0x0000000c>,	/* Register: pinmux_shared_io_q4_11 */
-				<0x000000bc 0x0000000c>;	/* Register: pinmux_shared_io_q4_12 */
-		};
-
-		/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
-		dedicated {
-			reg = <0xffd07200 0x00000200>;
-			pinctrl-single,register-width = <32>;
-			pinctrl-single,function-mask = <0x0000000f>;
-			pinctrl-single,pins =
-				<0x0000000c 0x00000008>,	/* Register: pinmux_dedicated_io_4 */
-				<0x00000010 0x00000008>,	/* Register: pinmux_dedicated_io_5 */
-				<0x00000014 0x00000008>,	/* Register: pinmux_dedicated_io_6 */
-				<0x00000018 0x00000008>,	/* Register: pinmux_dedicated_io_7 */
-				<0x0000001c 0x00000008>,	/* Register: pinmux_dedicated_io_8 */
-				<0x00000020 0x00000008>,	/* Register: pinmux_dedicated_io_9 */
-				<0x00000024 0x0000000a>,	/* Register: pinmux_dedicated_io_10 */
-				<0x00000028 0x0000000a>,	/* Register: pinmux_dedicated_io_11 */
-				<0x0000002c 0x00000008>,	/* Register: pinmux_dedicated_io_12 */
-				<0x00000030 0x00000008>,	/* Register: pinmux_dedicated_io_13 */
-				<0x00000034 0x00000008>,	/* Register: pinmux_dedicated_io_14 */
-				<0x00000038 0x00000008>,	/* Register: pinmux_dedicated_io_15 */
-				<0x0000003c 0x0000000d>,	/* Register: pinmux_dedicated_io_16 */
-				<0x00000040 0x0000000d>;	/* Register: pinmux_dedicated_io_17 */
-		};
-
-		/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
-		dedicated_cfg {
-			reg = <0xffd07200 0x00000200>;
-			pinctrl-single,register-width = <32>;
-			pinctrl-single,function-mask = <0x003f3f3f>;
-			pinctrl-single,pins =
-				<0x00000100 0x00000101>,	/* Register: configuration_dedicated_io_bank */
-				<0x00000104 0x000b080a>,	/* Register: configuration_dedicated_io_1 */
-				<0x00000108 0x000b080a>,	/* Register: configuration_dedicated_io_2 */
-				<0x0000010c 0x000b080a>,	/* Register: configuration_dedicated_io_3 */
-				<0x00000110 0x000a282a>,	/* Register: configuration_dedicated_io_4 */
-				<0x00000114 0x000a282a>,	/* Register: configuration_dedicated_io_5 */
-				<0x00000118 0x0008282a>,	/* Register: configuration_dedicated_io_6 */
-				<0x0000011c 0x000a282a>,	/* Register: configuration_dedicated_io_7 */
-				<0x00000120 0x000a282a>,	/* Register: configuration_dedicated_io_8 */
-				<0x00000124 0x000a282a>,	/* Register: configuration_dedicated_io_9 */
-				<0x00000128 0x00090000>,	/* Register: configuration_dedicated_io_10 */
-				<0x0000012c 0x00090000>,	/* Register: configuration_dedicated_io_11 */
-				<0x00000130 0x000b282a>,	/* Register: configuration_dedicated_io_12 */
-				<0x00000134 0x000b282a>,	/* Register: configuration_dedicated_io_13 */
-				<0x00000138 0x000b282a>,	/* Register: configuration_dedicated_io_14 */
-				<0x0000013c 0x000b282a>,	/* Register: configuration_dedicated_io_15 */
-				<0x00000140 0x0008282a>,	/* Register: configuration_dedicated_io_16 */
-				<0x00000144 0x000a282a>;	/* Register: configuration_dedicated_io_17 */
-		};
-
-		/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp */
-		fpga {
-			reg = <0xffd07400 0x00000100>;
-			pinctrl-single,register-width = <32>;
-			pinctrl-single,function-mask = <0x00000001>;
-			pinctrl-single,pins =
-				<0x00000000 0x00000000>,	/* Register: pinmux_emac0_usefpga */
-				<0x00000004 0x00000000>,	/* Register: pinmux_emac1_usefpga */
-				<0x00000008 0x00000000>,	/* Register: pinmux_emac2_usefpga */
-				<0x0000000c 0x00000000>,	/* Register: pinmux_i2c0_usefpga */
-				<0x00000010 0x00000000>,	/* Register: pinmux_i2c1_usefpga */
-				<0x00000014 0x00000000>,	/* Register: pinmux_i2c_emac0_usefpga */
-				<0x00000018 0x00000000>,	/* Register: pinmux_i2c_emac1_usefpga */
-				<0x0000001c 0x00000000>,	/* Register: pinmux_i2c_emac2_usefpga */
-				<0x00000020 0x00000000>,	/* Register: pinmux_nand_usefpga */
-				<0x00000024 0x00000000>,	/* Register: pinmux_qspi_usefpga */
-				<0x00000028 0x00000000>,	/* Register: pinmux_sdmmc_usefpga */
-				<0x0000002c 0x00000000>,	/* Register: pinmux_spim0_usefpga */
-				<0x00000030 0x00000000>,	/* Register: pinmux_spim1_usefpga */
-				<0x00000034 0x00000000>,	/* Register: pinmux_spis0_usefpga */
-				<0x00000038 0x00000000>,	/* Register: pinmux_spis1_usefpga */
-				<0x0000003c 0x00000000>,	/* Register: pinmux_uart0_usefpga */
-				<0x00000040 0x00000000>;	/* Register: pinmux_uart1_usefpga */
-		};
-	};
-
-	/*
-	 * Driver: altera_arria10_soc_noc_arria10_uboot_driver
-	 * Version: 1.0
-	 * Binding: device
-	 */
-	i_noc: noc at 0xffd10000 {
-		compatible = "altr,socfpga-a10-noc";
-		reg = <0xffd10000 0x00008000>;
-		reg-names = "mpu_m0";
-
-		firewall {
-			/*
-			 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base
-			 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit
-			 */
-			mpu0 = <0x00000000 0x0000ffff>;
-			/*
-			 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.base
-			 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.limit
-			 */
-			l3-0 = <0x00000000 0x0000ffff>;
-			/*
-			 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.base
-			 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.limit
-			 */
-			fpga2sdram0-0 = <0x00000000 0x0000ffff>;
-			/*
-			 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.base
-			 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.limit
-			 */
-			fpga2sdram1-0 = <0x00000000 0x0000ffff>;
-			/*
-			 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.base
-			 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.limit
-			 */
-			fpga2sdram2-0 = <0x00000000 0x0000ffff>;
-		};
-	};
-
-	hps_fpgabridge0: fpgabridge at 0 {
-		compatible = "altr,socfpga-hps2fpga-bridge";
-		init-val = <1>;
-	};
-
-	hps_fpgabridge1: fpgabridge at 1 {
-		compatible = "altr,socfpga-lwhps2fpga-bridge";
-		init-val = <1>;
-	};
-
-	hps_fpgabridge2: fpgabridge at 2 {
-		compatible = "altr,socfpga-fpga2hps-bridge";
-		init-val = <1>;
-	};
-
-	hps_fpgabridge3: fpgabridge at 3 {
-		compatible = "altr,socfpga-fpga2sdram0-bridge";
-		init-val = <1>;
-	};
-
-	hps_fpgabridge4: fpgabridge at 4 {
-		compatible = "altr,socfpga-fpga2sdram1-bridge";
-		init-val = <0>;
-	};
-
-	hps_fpgabridge5: fpgabridge at 5 {
-		compatible = "altr,socfpga-fpga2sdram2-bridge";
-		init-val = <1>;
-	};
-};
-- 
2.21.0

[U-Boot] [PATCH 8/8] ARM: socfpga: Update README.socfpga to add qts-filter-a10

[Dalon Westergreen]

From: Dalon Westergreen <dalon.westergreen@intel.com>

Update the readme to add a simple description of using
the qts-filter-a10.sh script.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
---
 doc/README.socfpga | 37 +++++++++++++++++++++++++++++++++----
 1 file changed, 33 insertions(+), 4 deletions(-)

diff --git a/doc/README.socfpga b/doc/README.socfpga
index cae0ef1a21..c5a3b11133 100644
--- a/doc/README.socfpga
+++ b/doc/README.socfpga
@@ -16,9 +16,9 @@ controller support within SOCFPGA
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT	256
 -> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM
 
---------------------------------------------------
-Generating the handoff header files for U-Boot SPL
---------------------------------------------------
+---------------------------------------------------------------------
+Cyclone5 / Arria 5 Generating the handoff header files for U-Boot SPL
+---------------------------------------------------------------------
 
 This text is assuming quartus 16.1, but newer versions will probably work just fine too;
 verified with DE1_SOC_Linux_FB demo project (https://github.com/VCTLabs/DE1_SOC_Linux_FB).
@@ -32,7 +32,7 @@ Rebuilding your Quartus project
 
 Choose one of the follwing methods, either command line or GUI.
 
-Using the comaand line
+Using the command line
 ~~~~~~~~~~~~~~~~~~~~~~
 
 First run the embedded command shell, using your path to the Quartus install:
@@ -147,3 +147,32 @@ Note: file sizes will differ slightly depending on the selected board.
 
 Now your board is ready for full mainline support including U-Boot SPL.
 The Preloader will not be needed any more.
+
+----------------------------------------------------------
+Arria10 Generating the handoff header files for U-Boot SPL
+----------------------------------------------------------
+
+A header file for inclusion in a devicetree for Arria10 can be generated
+by the qts-filter-a10.sh script directly from the hps_isw_handoff/hps.xml
+file generated during the FPGA project compilation.  The header contains
+all PLL, clock, pinmux, and bridge configurations required.
+
+Please look at the socfpga_arria10_socdk_sdmmc-u-boot.dtsi for an example
+that includes use of the generated handoff header.
+
+Devicetree header generation
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The qts-filter-a10.sh script can process the compile time genetated hps.xml
+to create the appropriate devicetree header.
+
+
+  $ ./arch/arm/mach-socfpga/qts-filter-a10.sh \
+        <hps_xml> \
+        <output_file>
+
+    hps_xml      - hps_isw_handoff/hps.xml from Quartus project
+    output_file  - Output filename and location for header file
+
+The script generates a single header file names <output_file> that should
+be placed in arch/arm/dts.
-- 
2.21.0

[U-Boot] [PATCH 1/8] ARM: socfpga: arria10: Add qts-filter for arria10 socfpga

[Marek Vasut]

On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> From: Dalon Westergreen <dalon.westergreen@intel.com>
> 
> Add a script to process hps handoff data and generate a header
> for inclusion in u-boot specific devicetree addons.  The header
> should be included in the top level u-boot.dtsi.

A10 should already be completely DT based and should directly use the DT
generated by quartus, why is this script needed?

Also, if this is to be included in u-boot.dtsi , how does this work with
multiple distinct boards ?

[U-Boot] [PATCH 2/8] ARM: socfpga: arria10: Sync A10 SoCDK devicetrees

[Marek Vasut]

On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> From: Dalon Westergreen <dalon.westergreen@intel.com>
> 
> Sync devicetree from 5.2 kernel.

Linux 5.3 was already released, can you update this ?
Also, make sure to list the exact commit ID in the commit message when
importing stuff from Linux.

[U-Boot] [PATCH 3/8] ARM: socfpga: arria10: Add common u-boot devicetree include

[Marek Vasut]

On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> From: Dalon Westergreen <dalon.westergreen@intel.com>
> 
> Add a common u-boot devicetree include file for the SocFPGA
> Arria10 device.

Isn't arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi doing basically
the same thing, except more fine-grained ?

> diff --git a/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
> new file mode 100644
> index 0000000000..bd4f1271f3
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
> @@ -0,0 +1,206 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright Altera Corporation (C) 2014. All rights reserved.
> + */
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	chosen {
> +		tick-timer = &timer2;
> +		u-boot,dm-pre-reloc;
> +	};
> +
> +	memory at 0 {
> +		u-boot,dm-pre-reloc;
> +	};
> +
> +	soc {
> +		u-boot,dm-pre-reloc;
> +
> +		clkmgr at ffd04000 {
> +			u-boot,dm-pre-reloc;
> +
> +			clocks {
> +					u-boot,dm-pre-reloc;
> +
> +					cb_intosc_hs_div2_clk {
> +						u-boot,dm-pre-reloc;
> +					};
> +
> +					cb_intosc_ls_clk {
> +						u-boot,dm-pre-reloc;
> +					};
> +
> +					f2s_free_clk {
> +						u-boot,dm-pre-reloc;
> +					};
> +
> +					osc1 {
> +						u-boot,dm-pre-reloc;
> +					};
> +
> +					main_pll at 40 {
> +						u-boot,dm-pre-reloc;
> +
> +						main_mpu_base_clk {
> +							u-boot,dm-pre-reloc;
> +						};
> +
> +						main_noc_base_clk {
> +							u-boot,dm-pre-reloc;
> +						};
> +
> +						main_emaca_clk at 68 {
> +							u-boot,dm-pre-reloc;
> +						};

Do we really need all this in SPL for every board ?

[U-Boot] [PATCH 4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

[Marek Vasut]

On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> From: Dalon Westergreen <dalon.westergreen@intel.com>
> 
> Generic handoff devicetree include uses a header generated by
> the qts-filter-a10.sh script in mach-socfpga.  The script
> creates the header based on design specific implementations
> for clock and pinmux configurations.

[...]

> diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi

[...]

> -	clock_manager at 0xffd04000 {
> +	clkmgr at 0xffd04000 {
> +		compatible = "altr,socfpga-a10-clk-init";
> +		reg = <0xffd04000 0x00000200>;
> +		reg-names = "soc_clock_manager_OCP_SLV";
>  		u-boot,dm-pre-reloc;
>  
>  		mainpll {
> +			vco0-psrc = <MAINPLLGRP_VCO0_PSRC>;
> +			vco1-denom = <MAINPLLGRP_VCO1_DENOM>;
> +			vco1-numer = <MAINPLLGRP_VCO1_NUMER>;

But these bits are board-specific , they shouldn't be in common DT.

[U-Boot] [PATCH 4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

[Dalon L Westergreen]

On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > From: Dalon Westergreen <dalon.westergreen@intel.com>
> > Generic handoff devicetree include uses a header generated bythe qts-filter-
> > a10.sh script in mach-socfpga.  The scriptcreates the header based on design
> > specific implementationsfor clock and pinmux configurations.
> 
> [...]
> > diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> > b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> 
> [...]
> > -	clock_manager at 0xffd04000 {+	clkmgr at 0xffd04000 {+		compatible =
> > "altr,socfpga-a10-clk-init";+		reg = <0xffd04000 0x00000200>;+	
> > 	reg-names = "soc_clock_manager_OCP_SLV"; 		u-boot,dm-pre-
> > reloc;  		mainpll {+			vco0-psrc =
> > <MAINPLLGRP_VCO0_PSRC>;+			vco1-denom =
> > <MAINPLLGRP_VCO1_DENOM>;+			vco1-numer =
> > <MAINPLLGRP_VCO1_NUMER>;
> 
> But these bits are board-specific , they shouldn't be in common DT.

This common dtsi requires that the top level u-boot.dtsi include the board
specific header.  The format
and #define names are in fact common.

--dalon

[U-Boot] [PATCH 1/8] ARM: socfpga: arria10: Add qts-filter for arria10 socfpga

[Dalon L Westergreen]

On Sat, 2019-10-05 at 01:47 +0200, Marek Vasut wrote:
> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > From: Dalon Westergreen <dalon.westergreen@intel.com>
> > Add a script to process hps handoff data and generate a headerfor inclusion
> > in u-boot specific devicetree addons.  The headershould be included in the
> > top level u-boot.dtsi.
> 
> A10 should already be completely DT based and should directly use the
> DTgenerated by quartus, why is this script needed?

The bsp-editor is on the path to being deprecated, this completely removes the
need for the generated devicetree

> Also, if this is to be included in u-boot.dtsi , how does this work
> withmultiple distinct boards ?

Each board has its own top-level devicetree name.  the intent is that the header
is included
in the top-level u-boot.dtsi, as in socfpga_arria10_socdk_sdmmc-u-boot.dtsi
which
is for a specific board implementation.  Other implementations should have their
own devicetree.

In this patch set, the header is socfpga_arria10_socdk_sdmmc_handoff.h included
in socfpga_arria10_socdk_sdmmc-u-boot.dtsi. 

--dalon

[U-Boot] [PATCH 2/8] ARM: socfpga: arria10: Sync A10 SoCDK devicetrees

[Dalon L Westergreen]

On Sat, 2019-10-05 at 01:47 +0200, Marek Vasut wrote:
> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > From: Dalon Westergreen <dalon.westergreen@intel.com>
> > Sync devicetree from 5.2 kernel.
> 
> Linux 5.3 was already released, can you update this ?Also, make sure to list
> the exact commit ID in the commit message whenimporting stuff from Linux.

Sure.  will do.

--dalon

[U-Boot] [PATCH 3/8] ARM: socfpga: arria10: Add common u-boot devicetree include

[Dalon L Westergreen]

On Sat, 2019-10-05 at 01:49 +0200, Marek Vasut wrote:
> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > From: Dalon Westergreen <dalon.westergreen@intel.com>
> > Add a common u-boot devicetree include file for the SocFPGAArria10 device.
> 
> Isn't arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi doing basicallythe same
> thing, except more fine-grained ?
> > diff --git a/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
> > b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsinew file mode 100644index
> > 0000000000..bd4f1271f3--- /dev/null+++ b/arch/arm/dts/socfpga_arria10-
> > common-u-boot.dtsi@@ -0,0 +1,206 @@+// SPDX-License-Identifier: GPL-2.0+/*+
> > * Copyright Altera Corporation (C) 2014. All rights reserved.+ */++/ {+	
> > #address-cells = <1>;+	#size-cells = <1>;++	chosen {+		tick
> > -timer = &timer2;+		u-boot,dm-pre-reloc;+	};++	memory at 0 {+	
> > 	u-boot,dm-pre-reloc;+	};++	soc {+		u-boot,dm-pre-
> > reloc;++		clkmgr at ffd04000 {+			u-boot,dm-pre-
> > reloc;++			clocks {+					u-
> > boot,dm-pre-reloc;++					cb_intosc_hs_div
> > 2_clk {+						u-boot,dm-pre-reloc;+	
> > 				};++					cb_i
> > ntosc_ls_clk {+						u-boot,dm-pre-
> > reloc;+					};++				
> > 	f2s_free_clk {+						u-boot,dm-
> > pre-reloc;+					};++				
> > 	osc1 {+						u-boot,dm-pre-
> > reloc;+					};++				
> > 	main_pll at 40 {+						u-boot,dm-
> > pre-reloc;++						main_mpu_base_cl
> > k {+							u-boot,dm-pre-
> > reloc;+						};++			
> > 			main_noc_base_clk {+					
> > 		u-boot,dm-pre-reloc;+						
> > };++						main_emaca_clk at 68 {+	
> > 						u-boot,dm-pre-reloc;+		
> > 				};
> 
> Do we really need all this in SPL for every board ?

We likely don't, but we arent that memory constrained in a10 and this simplifies
devicetree creation for custom boards.  We do have customers using ethernet
in spl, for example.  I can slim this down, but is it necessary?

--dalon

[U-Boot] [PATCH 3/8] ARM: socfpga: arria10: Add common u-boot devicetree include

[Marek Vasut]

On 10/6/19 1:25 AM, Dalon L Westergreen wrote:
> On Sat, 2019-10-05 at 01:49 +0200, Marek Vasut wrote:
>> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
>>> From: Dalon Westergreen <dalon.westergreen@intel.com>
>>> Add a common u-boot devicetree include file for the SocFPGAArria10 device.
>>
>> Isn't arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi doing basicallythe same
>> thing, except more fine-grained ?
>>> diff --git a/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
>>> b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsinew file mode 100644index
>>> 0000000000..bd4f1271f3--- /dev/null+++ b/arch/arm/dts/socfpga_arria10-
>>> common-u-boot.dtsi@@ -0,0 +1,206 @@+// SPDX-License-Identifier: GPL-2.0+/*+
>>> * Copyright Altera Corporation (C) 2014. All rights reserved.+ */++/ {+	
>>> #address-cells = <1>;+	#size-cells = <1>;++	chosen {+		tick
>>> -timer = &timer2;+		u-boot,dm-pre-reloc;+	};++	memory at 0 {+	
>>> 	u-boot,dm-pre-reloc;+	};++	soc {+		u-boot,dm-pre-
>>> reloc;++		clkmgr at ffd04000 {+			u-boot,dm-pre-
>>> reloc;++			clocks {+					u-
>>> boot,dm-pre-reloc;++					cb_intosc_hs_div
>>> 2_clk {+						u-boot,dm-pre-reloc;+	
>>> 				};++					cb_i
>>> ntosc_ls_clk {+						u-boot,dm-pre-
>>> reloc;+					};++				
>>> 	f2s_free_clk {+						u-boot,dm-
>>> pre-reloc;+					};++				
>>> 	osc1 {+						u-boot,dm-pre-
>>> reloc;+					};++				
>>> 	main_pll at 40 {+						u-boot,dm-
>>> pre-reloc;++						main_mpu_base_cl
>>> k {+							u-boot,dm-pre-
>>> reloc;+						};++			
>>> 			main_noc_base_clk {+					
>>> 		u-boot,dm-pre-reloc;+						
>>> };++						main_emaca_clk at 68 {+	
>>> 						u-boot,dm-pre-reloc;+		
>>> 				};
>>
>> Do we really need all this in SPL for every board ?
> 
> We likely don't, but we arent that memory constrained in a10 and this simplifies
> devicetree creation for custom boards.

We shouldn't enable what we don't need in SPL.

> We do have customers using ethernet
> in spl, for example.  I can slim this down, but is it necessary?

Just enable the necessary clock in the board-specific DT, since it's a
board-specific configuration.

[U-Boot] [PATCH 4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

[Marek Vasut]

On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
> On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
>> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
>>> From: Dalon Westergreen <dalon.westergreen@intel.com>
>>> Generic handoff devicetree include uses a header generated bythe qts-filter-
>>> a10.sh script in mach-socfpga.  The scriptcreates the header based on design
>>> specific implementationsfor clock and pinmux configurations.
>>
>> [...]
>>> diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
>>> b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
>>
>> [...]
>>> -	clock_manager at 0xffd04000 {+	clkmgr at 0xffd04000 {+		compatible =
>>> "altr,socfpga-a10-clk-init";+		reg = <0xffd04000 0x00000200>;+	
>>> 	reg-names = "soc_clock_manager_OCP_SLV"; 		u-boot,dm-pre-
>>> reloc;  		mainpll {+			vco0-psrc =
>>> <MAINPLLGRP_VCO0_PSRC>;+			vco1-denom =
>>> <MAINPLLGRP_VCO1_DENOM>;+			vco1-numer =
>>> <MAINPLLGRP_VCO1_NUMER>;
>>
>> But these bits are board-specific , they shouldn't be in common DT.
> 
> This common dtsi requires that the top level u-boot.dtsi include the board
> specific header.  The format
> and #define names are in fact common.

OK, I now see what you're doing here. Can you explain that in a bit more
detail in the commit message ?

Basically socfpga_board.h is included socfpga_board.dts , and then the
preprocessor correctly expands the values from socfpga_board.h in the
socfpga_board.dts , so this works for multiple boards too ?

[U-Boot] [PATCH 4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

[Dalon L Westergreen]

On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
> On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
> > On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
> > > On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > > > From: Dalon Westergreen <dalon.westergreen@intel.com>Generic handoff
> > > > devicetree include uses a header generated bythe qts-filter-a10.sh
> > > > script in mach-socfpga.  The scriptcreates the header based on
> > > > designspecific implementationsfor clock and pinmux configurations.
> > > 
> > > [...]
> > > > diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-
> > > > boot.dtsib/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> > > 
> > > [...]
> > > > -	clock_manager at 0xffd04000 {+	clkmgr at 0xffd04000 {+		
> > > > compatible ="altr,socfpga-a10-clk-init";+		reg =
> > > > <0xffd04000 0x00000200>;+		reg-names =
> > > > "soc_clock_manager_OCP_SLV"; 		u-boot,dm-pre-reloc;  		
> > > > mainpll {+			vco0-psrc =<MAINPLLGRP_VCO0_PSRC>;+		
> > > > 	vco1-denom =<MAINPLLGRP_VCO1_DENOM>;+			vco1-
> > > > numer =<MAINPLLGRP_VCO1_NUMER>;
> > > 
> > > But these bits are board-specific , they shouldn't be in common DT.
> > 
> > This common dtsi requires that the top level u-boot.dtsi include the
> > boardspecific header.  The formatand #define names are in fact common.
> 
> OK, I now see what you're doing here. Can you explain that in a bit moredetail
> in the commit message ?
> Basically socfpga_board.h is included socfpga_board.dts , and then
> thepreprocessor correctly expands the values from socfpga_board.h in
> thesocfpga_board.dts , so this works for multiple boards too ?

Exactly.  Will add more detail in the commit message, and slim down the included
clocks in
the u-boot.dtsi

[U-Boot] [PATCH 4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

[Simon Goldschmidt]

Am 06.10.2019 um 19:44 schrieb Dalon L Westergreen:
> On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
>> On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
>>> On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
>>>> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
>>>>> From: Dalon Westergreen <
>>>>> dalon.westergreen at intel.com
>>>>>  <mailto:dalon.westergreen@intel.com>
>>>>> >
>>>>> Generic handoff devicetree include uses a header generated bythe qts-filter-
>>>>> a10.sh script in mach-socfpga.  The scriptcreates the header based on design
>>>>> specific implementationsfor clock and pinmux configurations.
>>>>
>>>> [...]
>>>>> diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
>>>>> b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
>>>>
>>>> [...]
>>>>> -	clock_manager at 0xffd04000 {+	clkmgr at 0xffd04000 {+		compatible =
>>>>> "altr,socfpga-a10-clk-init";+		reg = <0xffd04000 0x00000200>;+	
>>>>> 	reg-names = "soc_clock_manager_OCP_SLV"; 		u-boot,dm-pre-
>>>>> reloc;  		mainpll {+			vco0-psrc =
>>>>> <MAINPLLGRP_VCO0_PSRC>;+			vco1-denom =
>>>>> <MAINPLLGRP_VCO1_DENOM>;+			vco1-numer =
>>>>> <MAINPLLGRP_VCO1_NUMER>;
>>>>
>>>> But these bits are board-specific , they shouldn't be in common DT.
>>>
>>> This common dtsi requires that the top level u-boot.dtsi include the board
>>> specific header.  The format
>>> and #define names are in fact common.
>>
>> OK, I now see what you're doing here. Can you explain that in a bit more
>> detail in the commit message ?
>>
>> Basically socfpga_board.h is included socfpga_board.dts , and then the
>> preprocessor correctly expands the values from socfpga_board.h in the
>> socfpga_board.dts , so this works for multiple boards too ?
> 
> Exactly. Will add more detail in the commit message, and slim down the 
> included clocks in
> the u-boot.dtsi

I'm (still) working on a series to bring gen5 completely to devicetree, 
so that the 'qts' directories can be removed. I chose a different 
approach however, in that I generated everything into a '-handoff.dtsi' 
file (*). I'd be happy if we could find a common mechanism for all 
socfpga sub-archs. How does S10/Agilex handle this?

(*): Gen5 has the downside that we're low on memory in SPL (regarding 
DM), and as we require large binary arrays there, I chose to encode the 
binary blob arrays in host byte order so that they could be used 
in-place instead of copying them from BE (dtb) to LE (stack/heap). Maybe 
that doesn't fit A10/S10/Agilex anyway?

Regards,
Simon

[U-Boot] [PATCH 4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

[Dalon L Westergreen]

On Sun, 2019-10-06 at 20:05 +0200, Simon Goldschmidt wrote:
> Am 06.10.2019 um 19:44 schrieb Dalon L Westergreen:
> > On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
> > > On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
> > > > On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
> > > > > On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > > > > > From: Dalon Westergreen <dalon.westergreen@intel.com
> > > > > >  <mailto:dalon.westergreen@intel.com>
> > > > > > Generic handoff devicetree include uses a header generated bythe
> > > > > > qts-filter-a10.sh script in mach-socfpga.  The scriptcreates the
> > > > > > header based on designspecific implementationsfor clock and pinmux
> > > > > > configurations.
> > > > > 
> > > > > [...]
> > > > > > diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-
> > > > > > boot.dtsib/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> > > > > 
> > > > > [...]
> > > > > > -	clock_manager at 0xffd04000 {+	clkmgr at 0xffd04000 {+		comp
> > > > > > atible ="altr,socfpga-a10-clk-init";+		reg =
> > > > > > <0xffd04000 0x00000200>;+		reg-names =
> > > > > > "soc_clock_manager_OCP_SLV"; 		u-boot,dm-pre-reloc;  	
> > > > > > 	mainpll {+			vco0-psrc =<MAINPLLGRP_VCO0_PSRC>;+	
> > > > > > 		vco1-denom =<MAINPLLGRP_VCO1_DENOM>;+			
> > > > > > vco1-numer =<MAINPLLGRP_VCO1_NUMER>;
> > > > > 
> > > > > But these bits are board-specific , they shouldn't be in common DT.
> > > > 
> > > > This common dtsi requires that the top level u-boot.dtsi include the
> > > > boardspecific header.  The formatand #define names are in fact common.
> > > 
> > > OK, I now see what you're doing here. Can you explain that in a bit
> > > moredetail in the commit message ?
> > > Basically socfpga_board.h is included socfpga_board.dts , and then
> > > thepreprocessor correctly expands the values from socfpga_board.h in
> > > thesocfpga_board.dts , so this works for multiple boards too ?
> > 
> > Exactly. Will add more detail in the commit message, and slim down the
> > included clocks inthe u-boot.dtsi
> 
> I'm (still) working on a series to bring gen5 completely to devicetree, so
> that the 'qts' directories can be removed. I chose a different approach
> however, in that I generated everything into a '-handoff.dtsi' file (*). I'd
> be happy if we could find a common mechanism for all socfpga sub-archs. How
> does S10/Agilex handle this?
> (*): Gen5 has the downside that we're low on memory in SPL (regarding DM), and
> as we require large binary arrays there, I chose to encode the binary blob
> arrays in host byte order so that they could be used in-place instead of
> copying them from BE (dtb) to LE (stack/heap). Maybe that doesn't fit
> A10/S10/Agilex anyway?

S10/Agilex are entirely different.  The onchip ram is loaded with any
configuration data bythe secure device manager.  There is no need to modify the
dts for any io/pll/bridgeconfiguration. 
A10 is better than cv/av in that is requires far less configuration data, and no
dataregarding the dram is needed.  Also, there is no binary parsing required for
extractingthe required data, hence the simple qts-filter-a10.sh.  
I think a -handoff.dtsi is a good approach, but why not do the same thing i do
here anduse a header file for the config data.  that way the -handoff.dtsi can
be common and theheader only needs to be included in the toplevel -u-boot.dtsi?
--dalon
> Regards,Simon

[U-Boot] [PATCH 4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

[Dalon L Westergreen]

On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
> On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
> > On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
> > > On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > > > From: Dalon Westergreen <dalon.westergreen@intel.com>Generic handoff
> > > > devicetree include uses a header generated bythe qts-filter-a10.sh
> > > > script in mach-socfpga.  The scriptcreates the header based on
> > > > designspecific implementationsfor clock and pinmux configurations.
> > > 
> > > [...]
> > > > diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-
> > > > boot.dtsib/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> > > 
> > > [...]
> > > > -	clock_manager at 0xffd04000 {+	clkmgr at 0xffd04000 {+		
> > > > compatible ="altr,socfpga-a10-clk-init";+		reg =
> > > > <0xffd04000 0x00000200>;+		reg-names =
> > > > "soc_clock_manager_OCP_SLV"; 		u-boot,dm-pre-reloc;  		
> > > > mainpll {+			vco0-psrc =<MAINPLLGRP_VCO0_PSRC>;+		
> > > > 	vco1-denom =<MAINPLLGRP_VCO1_DENOM>;+			vco1-
> > > > numer =<MAINPLLGRP_VCO1_NUMER>;
> > > 
> > > But these bits are board-specific , they shouldn't be in common DT.
> > 
> > This common dtsi requires that the top level u-boot.dtsi include the
> > boardspecific header.  The formatand #define names are in fact common.
> 
> OK, I now see what you're doing here. Can you explain that in a bit moredetail
> in the commit message ?
> Basically socfpga_board.h is included socfpga_board.dts , and then
> thepreprocessor correctly expands the values from socfpga_board.h in
> thesocfpga_board.dts , so this works for multiple boards too ?

oh, and yes, it does work for multiple boards, i have already tested this.

--dalon

[U-Boot] [PATCH 3/8] ARM: socfpga: arria10: Add common u-boot devicetree include

[Dalon L Westergreen]

On Sat, 2019-10-05 at 01:49 +0200, Marek Vasut wrote:
> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > From: Dalon Westergreen <dalon.westergreen@intel.com>
> > Add a common u-boot devicetree include file for the SocFPGAArria10 device.
> 
> Isn't arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi doing basicallythe same
> thing, except more fine-grained ?

I wanted to keep the dts fragment dependent on the handoff header separate from
thegeneric base u-boot include.
> > diff --git a/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
> > b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsinew file mode 100644index
> > 0000000000..bd4f1271f3--- /dev/null+++ b/arch/arm/dts/socfpga_arria10-
> > common-u-boot.dtsi@@ -0,0 +1,206 @@+// SPDX-License-Identifier: GPL-2.0+/*+
> > * Copyright Altera Corporation (C) 2014. All rights reserved.+ */++/ {+	
> > #address-cells = <1>;+	#size-cells = <1>;++	chosen {+		tick
> > -timer = &timer2;+		u-boot,dm-pre-reloc;+	};++	memory at 0 {+	
> > 	u-boot,dm-pre-reloc;+	};++	soc {+		u-boot,dm-pre-
> > reloc;++		clkmgr at ffd04000 {+			u-boot,dm-pre-
> > reloc;++			clocks {+					u-
> > boot,dm-pre-reloc;++					cb_intosc_hs_div
> > 2_clk {+						u-boot,dm-pre-reloc;+	
> > 				};++					cb_i
> > ntosc_ls_clk {+						u-boot,dm-pre-
> > reloc;+					};++				
> > 	f2s_free_clk {+						u-boot,dm-
> > pre-reloc;+					};++				
> > 	osc1 {+						u-boot,dm-pre-
> > reloc;+					};++				
> > 	main_pll at 40 {+						u-boot,dm-
> > pre-reloc;++						main_mpu_base_cl
> > k {+							u-boot,dm-pre-
> > reloc;+						};++			
> > 			main_noc_base_clk {+					
> > 		u-boot,dm-pre-reloc;+						
> > };++						main_emaca_clk at 68 {+	
> > 						u-boot,dm-pre-reloc;+		
> > 				};
> 
> Do we really need all this in SPL for every board ?

[U-Boot] [PATCH 2/8] ARM: socfpga: arria10: Sync A10 SoCDK devicetrees

[Dalon L Westergreen]

On Sat, 2019-10-05 at 16:23 -0700, Dalon L Westergreen wrote:
> On Sat, 2019-10-05 at 01:47 +0200, Marek Vasut wrote:
> > On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > > From: Dalon Westergreen <dalon.westergreen@intel.com>Sync devicetree from
> > > 5.2 kernel.
> > 
> > Linux 5.3 was already released, can you update this ?Also, make sure to
> > listthe exact commit ID in the commit message whenimporting stuff from
> > Linux.
> 
> Sure.  will do.
> --dalon

The 5.3 mainline devicetrees do not as of yet have all appropriate compatibility
stringsfor the socfpga platform and still differs slightly from the linux-
socfpga/5.2 kernelas can be seen below.
I would suggest sticking with the linux-socfpga/5.2 kernel devicetrees and i can
appendthe commit message with the commit and git repo if that works?
--dalon
[dwesterg at dwesterg-mobl1 linux-socfpga]$ diff socfpga_arria10.dtsi
/home/dwesterg/data/git/uboot/u-boot/arch/arm/dts/socfpga_arria10.dtsi diff:
socfpga_arria10.dtsi: No such file or directory[dwesterg at dwesterg-mobl1 linux-
socfpga]$ diff arch/arm/boot/dts/socfpga_arria10.dtsi
/home/dwesterg/data/git/uboot/u-boot/arch/arm/dts/socfpga_arria10.dtsi 70a71> 		
		microcode-cached;421c422< 			compatible =
"altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";---> 			
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a",
"snps,dwmac";441,442c442,443< 			compatible = "altr,socfpga-
stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";< 			altr,sys
mgr-syscon = <&sysmgr 0x48 8>;---> 			compatible =
"altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";> 			
altr,sysmgr-syscon = <&sysmgr 0x48 0>;461,462c462,463< 			compatib
le = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";< 			
altr,sysmgr-syscon = <&sysmgr 0x4C 16>;---> 			compatible =
"altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";> 			
altr,sysmgr-syscon = <&sysmgr 0x4C 0>;[dwesterg at dwesterg-mobl1 linux-socfpga]$
diff arch/arm/boot/dts/socfpga_arria10.dtsi /home/dwesterg/data/git/uboot/u-
boot/arch/arm/dts/socfpga_arria10socfpga_arria10-common-u-
boot.dtsi       socfpga_arria10_handoff_u-
boot.dtsi~     socfpga_arria10_socdk_sdmmc.dts          socfpga_arria10.dtsi    
                 socfpga_arria10_socdk.dtsi               socfpga_arria10_socdk_
sdmmc_handoff.h    socfpga_arria10-
handoff.dtsi             socfpga_arria10_socdk_sdmmc.dtb          socfpga_arria1
0_socdk_sdmmc-u-boot.dtsi  [dwesterg at dwesterg-mobl1 linux-socfpga]$ diff
arch/arm/boot/dts/socfpga_arria10_socdk.dtsi /home/dwesterg/data/git/uboot/u-
boot/arch/arm/dts/socfpga_arria10_socdk.dtsi 123a124,127> > 		ps_alarm
{> 			compatible = "altr,a10sr-hwmon";> 		};149a15
4,161> 	lcd: lcd at 28 {> 		compatible = "newhaven,nhd-0216k3z-nsw-bbw";> 		
reg = <0x28>;> 		height = <2>;> 		width = <16>;> 		brightne
ss = <8>;> 	};> 158a171,175> 	};> > 	max at 4c {> 		compatib
le = "max1619";> 		reg = <0x4c>;


> _______________________________________________U-Boot mailing 
> listU-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 3/8] ARM: socfpga: arria10: Add common u-boot devicetree include

[Simon Goldschmidt]

On Mon, Oct 7, 2019 at 3:38 PM Dalon L Westergreen
<dalon.westergreen@linux.intel.com> wrote:
>
> On Sat, 2019-10-05 at 01:49 +0200, Marek Vasut wrote:
>
> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
>
> From: Dalon Westergreen <
>
> dalon.westergreen at intel.com
>
> >
>
>
> Add a common u-boot devicetree include file for the SocFPGA
>
> Arria10 device.
>
>
> Isn't arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi doing basically
>
> the same thing, except more fine-grained ?
>
>
> I wanted to keep the dts fragment dependent on the handoff header separate from the
> generic base u-boot include.

Hmm, ok, I see. Is it encouraged to add more header files in arch/arm/dts?
If so, I wouldn't be too opposed on going that way for gen5 as well...

Regards,
Simon

>
>
> diff --git a/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
>
> new file mode 100644
>
> index 0000000000..bd4f1271f3
>
> --- /dev/null
>
> +++ b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
>
> @@ -0,0 +1,206 @@
>
> +// SPDX-License-Identifier: GPL-2.0
>
> +/*
>
> + * Copyright Altera Corporation (C) 2014. All rights reserved.
>
> + */
>
> +
>
> +/ {
>
> + #address-cells = <1>;
>
> + #size-cells = <1>;
>
> +
>
> + chosen {
>
> + tick-timer = &timer2;
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + memory at 0 {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + soc {
>
> + u-boot,dm-pre-reloc;
>
> +
>
> + clkmgr at ffd04000 {
>
> + u-boot,dm-pre-reloc;
>
> +
>
> + clocks {
>
> + u-boot,dm-pre-reloc;
>
> +
>
> + cb_intosc_hs_div2_clk {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + cb_intosc_ls_clk {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + f2s_free_clk {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + osc1 {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + main_pll at 40 {
>
> + u-boot,dm-pre-reloc;
>
> +
>
> + main_mpu_base_clk {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + main_noc_base_clk {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + main_emaca_clk at 68 {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
>
> Do we really need all this in SPL for every board ?

[U-Boot] [PATCH 2/8] ARM: socfpga: arria10: Sync A10 SoCDK devicetrees

[Marek Vasut]

On 10/7/19 4:03 PM, Dalon L Westergreen wrote:
> On Sat, 2019-10-05 at 16:23 -0700, Dalon L Westergreen wrote:
>> On Sat, 2019-10-05 at 01:47 +0200, Marek Vasut wrote:
>>> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
>>>> From: Dalon Westergreen <dalon.westergreen@intel.com>Sync devicetree from
>>>> 5.2 kernel.
>>>
>>> Linux 5.3 was already released, can you update this ?Also, make sure to
>>> listthe exact commit ID in the commit message whenimporting stuff from
>>> Linux.
>>
>> Sure.  will do.
>> --dalon
> 
> The 5.3 mainline devicetrees do not as of yet have all appropriate compatibility
> stringsfor the socfpga platform and still differs slightly from the linux-
> socfpga/5.2 kernelas can be seen below.
> I would suggest sticking with the linux-socfpga/5.2 kernel devicetrees and i can
> appendthe commit message with the commit and git repo if that works?

What's linux-socfpga , is that something else than linux mainline ?

If there's stuff missing in the DTs, put it into -u-boot.dtsi for now,
until it trickles upstream.

> --dalon
> [dwesterg at dwesterg-mobl1 linux-socfpga]$ diff socfpga_arria10.dtsi
> /home/dwesterg/data/git/uboot/u-boot/arch/arm/dts/socfpga_arria10.dtsi diff:
> socfpga_arria10.dtsi: No such file or directory[dwesterg at dwesterg-mobl1 linux-
> socfpga]$ diff arch/arm/boot/dts/socfpga_arria10.dtsi
> /home/dwesterg/data/git/uboot/u-boot/arch/arm/dts/socfpga_arria10.dtsi 70a71> 		
> 		microcode-cached;421c422< 			compatible =
> "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";---> 			
> compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a",
> "snps,dwmac";441,442c442,443< 			compatible = "altr,socfpga-
> stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";< 			altr,sys

[...]

[U-Boot] [PATCH 4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

[Dalon L Westergreen]

On Sun, 2019-10-06 at 20:05 +0200, Simon Goldschmidt wrote:
> Am 06.10.2019 um 19:44 schrieb Dalon L Westergreen:
> > On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
> > > On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
> > > > On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
> > > > > On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > > > > > From: Dalon Westergreen <dalon.westergreen@intel.com
> > > > > >  <mailto:dalon.westergreen@intel.com>
> > > > > > Generic handoff devicetree include uses a header generated bythe
> > > > > > qts-filter-a10.sh script in mach-socfpga.  The scriptcreates the
> > > > > > header based on designspecific implementationsfor clock and pinmux
> > > > > > configurations.
> > > > > 
> > > > > [...]
> > > > > > diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-
> > > > > > boot.dtsib/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> > > > > 
> > > > > [...]
> > > > > > -	clock_manager at 0xffd04000 {+	clkmgr at 0xffd04000 {+		comp
> > > > > > atible ="altr,socfpga-a10-clk-init";+		reg =
> > > > > > <0xffd04000 0x00000200>;+		reg-names =
> > > > > > "soc_clock_manager_OCP_SLV"; 		u-boot,dm-pre-reloc;  	
> > > > > > 	mainpll {+			vco0-psrc =<MAINPLLGRP_VCO0_PSRC>;+	
> > > > > > 		vco1-denom =<MAINPLLGRP_VCO1_DENOM>;+			
> > > > > > vco1-numer =<MAINPLLGRP_VCO1_NUMER>;
> > > > > 
> > > > > But these bits are board-specific , they shouldn't be in common DT.
> > > > 
> > > > This common dtsi requires that the top level u-boot.dtsi include the
> > > > boardspecific header.  The formatand #define names are in fact common.
> > > 
> > > OK, I now see what you're doing here. Can you explain that in a bit
> > > moredetail in the commit message ?
> > > Basically socfpga_board.h is included socfpga_board.dts , and then
> > > thepreprocessor correctly expands the values from socfpga_board.h in
> > > thesocfpga_board.dts , so this works for multiple boards too ?
> > 
> > Exactly. Will add more detail in the commit message, and slim down the
> > included clocks inthe u-boot.dtsi
> 
> I'm (still) working on a series to bring gen5 completely to devicetree, so
> that the 'qts' directories can be removed. I chose a different approach
> however, in that I generated everything into a '-handoff.dtsi' file (*). I'd
> be happy if we could find a common mechanism for all socfpga sub-archs. How
> does S10/Agilex handle this?
> (*): Gen5 has the downside that we're low on memory in SPL (regarding DM), and
> as we require large binary arrays there, I chose to encode the binary blob
> arrays in host byte order so that they could be used in-place instead of
> copying them from BE (dtb) to LE (stack/heap). Maybe that doesn't fit
> A10/S10/Agilex anyway?

Can you share your patch set with me, privately or otherwise, just so we can
take a similarapproach in the devicetree?
Also, have you looked at the bsp-editor python source that generates the
"generated" filesfrom the bsp-editor?  
19.1std/647/linux64/ip/altera/preloader/scripts
I am hoping to replace these with a script included in the u-boot
source.  iocsr.py doesa bunch of binary parsing.
--dalon
> Regards,Simon

[U-Boot] [PATCH 4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

[Simon Goldschmidt]

There's something wrong with your mailer: indentation of replies doesn't seem
to work. It gets kind of hard to read who wrote what...

On Mon, Oct 7, 2019 at 4:34 PM Dalon L Westergreen
<dalon.westergreen@linux.intel.com> wrote:
>
> On Sun, 2019-10-06 at 20:05 +0200, Simon Goldschmidt wrote:
>
> Am 06.10.2019 um 19:44 schrieb Dalon L Westergreen:
>
> On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
>
> On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
>
> On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
>
> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
>
> From: Dalon Westergreen <
>
> dalon.westergreen at intel.com
>
>
>  <mailto:
>
> dalon.westergreen at intel.com
>
> >
>
>
> Generic handoff devicetree include uses a header generated bythe qts-filter-
>
> a10.sh script in mach-socfpga.  The scriptcreates the header based on design
>
> specific implementationsfor clock and pinmux configurations.
>
>
> [...]
>
> diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
>
> b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
>
>
> [...]
>
> - clock_manager at 0xffd04000 {+ clkmgr at 0xffd04000 {+ compatible =
>
> "altr,socfpga-a10-clk-init";+ reg = <0xffd04000 0x00000200>;+
>
> reg-names = "soc_clock_manager_OCP_SLV"; u-boot,dm-pre-
>
> reloc;   mainpll {+ vco0-psrc =
>
> <MAINPLLGRP_VCO0_PSRC>;+ vco1-denom =
>
> <MAINPLLGRP_VCO1_DENOM>;+ vco1-numer =
>
> <MAINPLLGRP_VCO1_NUMER>;
>
>
> But these bits are board-specific , they shouldn't be in common DT.
>
>
> This common dtsi requires that the top level u-boot.dtsi include the board
>
> specific header.  The format
>
> and #define names are in fact common.
>
>
> OK, I now see what you're doing here. Can you explain that in a bit more
>
> detail in the commit message ?
>
>
> Basically socfpga_board.h is included socfpga_board.dts , and then the
>
> preprocessor correctly expands the values from socfpga_board.h in the
>
> socfpga_board.dts , so this works for multiple boards too ?
>
>
> Exactly. Will add more detail in the commit message, and slim down the
>
> included clocks in
>
> the u-boot.dtsi
>
>
> I'm (still) working on a series to bring gen5 completely to devicetree,
>
> so that the 'qts' directories can be removed. I chose a different
>
> approach however, in that I generated everything into a '-handoff.dtsi'
>
> file (*). I'd be happy if we could find a common mechanism for all
>
> socfpga sub-archs. How does S10/Agilex handle this?
>
>
> (*): Gen5 has the downside that we're low on memory in SPL (regarding
>
> DM), and as we require large binary arrays there, I chose to encode the
>
> binary blob arrays in host byte order so that they could be used
>
> in-place instead of copying them from BE (dtb) to LE (stack/heap). Maybe
>
> that doesn't fit A10/S10/Agilex anyway?
>
>
> Can you share your patch set with me, privately or otherwise, just so we can take a similar
> approach in the devicetree?

Give me a week max. and I'll send the series as RFC.

>
> Also, have you looked at the bsp-editor python source that generates the "generated" files
> from the bsp-editor?
>
> 19.1std/647/linux64/ip/altera/preloader/scripts

No, I mainly focused on the U-Boot part for now. I just wrote a C program
that did the conversion from 'official generated' files to DTS...

>
> I am hoping to replace these with a script included in the u-boot source. iocsr.py does
> a bunch of binary parsing.

Right, a direct conversion from compilation output to U-Boot would be better.
However, that would require Intel to keep that output consistent!

Regards,
Simon

>
> --dalon
>
>
> Regards,
>
> Simon

[U-Boot] [PATCH 2/8] ARM: socfpga: arria10: Sync A10 SoCDK devicetrees

[Dalon L Westergreen]

On Mon, 2019-10-07 at 16:06 +0200, Marek Vasut wrote:
> On 10/7/19 4:03 PM, Dalon L Westergreen wrote:
> > On Sat, 2019-10-05 at 16:23 -0700, Dalon L Westergreen wrote:
> > > On Sat, 2019-10-05 at 01:47 +0200, Marek Vasut wrote:
> > > > On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > > > > From: Dalon Westergreen <dalon.westergreen@intel.com>Sync devicetree
> > > > > from5.2 kernel.
> > > > 
> > > > Linux 5.3 was already released, can you update this ?Also, make sure
> > > > tolistthe exact commit ID in the commit message whenimporting stuff
> > > > fromLinux.
> > > 
> > > Sure.  will do.--dalon
> > 
> > The 5.3 mainline devicetrees do not as of yet have all appropriate
> > compatibilitystringsfor the socfpga platform and still differs slightly from
> > the linux-socfpga/5.2 kernelas can be seen below.I would suggest sticking
> > with the linux-socfpga/5.2 kernel devicetrees and i canappendthe commit
> > message with the commit and git repo if that works?
> 
> What's linux-socfpga , is that something else than linux mainline ?
> If there's stuff missing in the DTs, put it into -u-boot.dtsi for now,until it
> trickles upstream.

Sounds good.

> 
> > --dalon
> > [dwesterg at dwesterg-mobl1 linux-socfpga]$ diff socfpga_arria10.dtsi
> > /home/dwesterg/data/git/uboot/u-boot/arch/arm/dts/socfpga_arria10.dtsi diff:
> > socfpga_arria10.dtsi: No such file or directory[dwesterg at dwesterg-mobl1 linux-
> > socfpga]$ diff arch/arm/boot/dts/socfpga_arria10.dtsi
> > /home/dwesterg/data/git/uboot/u-boot/arch/arm/dts/socfpga_arria10.dtsi 70a71> 		
> > 		microcode-cached;421c422< 			compatible =
> > "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";---> 			
> > compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a",
> > "snps,dwmac";441,442c442,443< 			compatible = "altr,socfpga-
> > stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";< 			altr,sys
> 
> [...]

[U-Boot] [PATCH 2/8] ARM: socfpga: arria10: Sync A10 SoCDK devicetrees

[Dalon L Westergreen]

On Mon, 2019-10-07 at 07:49 -0700, Dalon L Westergreen wrote:
> On Mon, 2019-10-07 at 16:06 +0200, Marek Vasut wrote:
> > On 10/7/19 4:03 PM, Dalon L Westergreen wrote:
> > > On Sat, 2019-10-05 at 16:23 -0700, Dalon L Westergreen wrote:
> > > > On Sat, 2019-10-05 at 01:47 +0200, Marek Vasut wrote:
> > > > > On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > > > > > From: Dalon Westergreen <dalon.westergreen@intel.com>Sync
> > > > > > devicetreefrom5.2 kernel.
> > > > > 
> > > > > Linux 5.3 was already released, can you update this ?Also, make
> > > > > suretolistthe exact commit ID in the commit message whenimporting
> > > > > stufffromLinux.
> > > > 
> > > > Sure.  will do.--dalon
> > > 
> > > The 5.3 mainline devicetrees do not as of yet have all
> > > appropriatecompatibilitystringsfor the socfpga platform and still differs
> > > slightly fromthe linux-socfpga/5.2 kernelas can be seen below.I would
> > > suggest stickingwith the linux-socfpga/5.2 kernel devicetrees and i
> > > canappendthe commitmessage with the commit and git repo if that works?
> > 
> > What's linux-socfpga , is that something else than linux mainline ?If
> > there's stuff missing in the DTs, put it into -u-boot.dtsi for now,until
> > ittrickles upstream.
> 
> Sounds good.

digging a little deeper, it is just that the dwmac-socfpga add on to the
ethernet driver in u-bootis lagging a bit and doesnt have the altr,socfpga-
stmmac-a10-s10 for a10/s10 differences.
i'll look at updating the driver in another patch set.
--dalon
> > > --dalon[dwesterg at dwesterg-mobl1 linux-socfpga]$ diff
> > > socfpga_arria10.dtsi/home/dwesterg/data/git/uboot/u-
> > > boot/arch/arm/dts/socfpga_arria10.dtsi diff:socfpga_arria10.dtsi: No such
> > > file or directory[dwesterg at dwesterg-mobl1 linux-socfpga]$ diff
> > > arch/arm/boot/dts/socfpga_arria10.dtsi/home/dwesterg/data/git/uboot/u-
> > > boot/arch/arm/dts/socfpga_arria10.dtsi 70a71> 				
> > > microcode-cached;421c422< 			compatible ="altr,socfpga-
> > > stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";---> 			
> > > compatible = "altr,socfpga-stmmac", "snps,dwmac-
> > > 3.72a","snps,dwmac";441,442c442,443< 			compatible =
> > > "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";< 		
> > > 	altr,sys
> > 
> > [...]
> _______________________________________________U-Boot mailing 
> listU-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

[Dalon L Westergreen]

On Mon, 2019-10-07 at 16:45 +0200, Simon Goldschmidt wrote:
> There's something wrong with your mailer: indentation of replies doesn't
> seemto work. It gets kind of hard to read who wrote what...
> On Mon, Oct 7, 2019 at 4:34 PM Dalon L Westergreen<
> dalon.westergreen at linux.intel.com> wrote:
> > On Sun, 2019-10-06 at 20:05 +0200, Simon Goldschmidt wrote:
> > Am 06.10.2019 um 19:44 schrieb Dalon L Westergreen:
> > On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
> > On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
> > On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
> > On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > From: Dalon Westergreen <
> > dalon.westergreen at intel.com
> > 
> > 
> >  <mailto:
> > dalon.westergreen at intel.com
> > 
> > 
> > Generic handoff devicetree include uses a header generated bythe qts-filter-
> > a10.sh script in mach-socfpga.  The scriptcreates the header based on design
> > specific implementationsfor clock and pinmux configurations.
> > 
> > [...]
> > diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> > b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> > 
> > [...]
> > - clock_manager at 0xffd04000 {+ clkmgr at 0xffd04000 {+ compatible =
> > "altr,socfpga-a10-clk-init";+ reg = <0xffd04000 0x00000200>;+
> > reg-names = "soc_clock_manager_OCP_SLV"; u-boot,dm-pre-
> > reloc;   mainpll {+ vco0-psrc =
> > <MAINPLLGRP_VCO0_PSRC>;+ vco1-denom =
> > <MAINPLLGRP_VCO1_DENOM>;+ vco1-numer =
> > <MAINPLLGRP_VCO1_NUMER>;
> > 
> > But these bits are board-specific , they shouldn't be in common DT.
> > 
> > This common dtsi requires that the top level u-boot.dtsi include the board
> > specific header.  The format
> > and #define names are in fact common.
> > 
> > OK, I now see what you're doing here. Can you explain that in a bit more
> > detail in the commit message ?
> > 
> > Basically socfpga_board.h is included socfpga_board.dts , and then the
> > preprocessor correctly expands the values from socfpga_board.h in the
> > socfpga_board.dts , so this works for multiple boards too ?
> > 
> > Exactly. Will add more detail in the commit message, and slim down the
> > included clocks in
> > the u-boot.dtsi
> > 
> > I'm (still) working on a series to bring gen5 completely to devicetree,
> > so that the 'qts' directories can be removed. I chose a different
> > approach however, in that I generated everything into a '-handoff.dtsi'
> > file (*). I'd be happy if we could find a common mechanism for all
> > socfpga sub-archs. How does S10/Agilex handle this?
> > 
> > (*): Gen5 has the downside that we're low on memory in SPL (regarding
> > DM), and as we require large binary arrays there, I chose to encode the
> > binary blob arrays in host byte order so that they could be used
> > in-place instead of copying them from BE (dtb) to LE (stack/heap). Maybe
> > that doesn't fit A10/S10/Agilex anyway?
> > 
> > Can you share your patch set with me, privately or otherwise, just so we can
> > take a similarapproach in the devicetree?
> 
> Give me a week max. and I'll send the series as RFC.
> > Also, have you looked at the bsp-editor python source that generates the
> > "generated" filesfrom the bsp-editor?
> > 19.1std/647/linux64/ip/altera/preloader/scripts
> 
> No, I mainly focused on the U-Boot part for now. I just wrote a C programthat
> did the conversion from 'official generated' files to DTS...
> > I am hoping to replace these with a script included in the u-boot source.
> > iocsr.py doesa bunch of binary parsing.
> 
> Right, a direct conversion from compilation output to U-Boot would be
> better.However, that would require Intel to keep that output consistent!
It should be consistent at this point.  i would not worry about that.
> Regards,Simon
> > --dalon
> > 
> > Regards,
> > Simon

[U-Boot] [PATCH 1/8] ARM: socfpga: arria10: Add qts-filter for arria10 socfpga

[Chee, Tien Fong]

On Fri, 2019-10-04 at 15:30 -0700, Dalon Westergreen wrote:
> From: Dalon Westergreen <dalon.westergreen@intel.com>
> 
> Add a script to process hps handoff data and generate a header
> for inclusion in u-boot specific devicetree addons.  The header
> should be included in the top level u-boot.dtsi.
> 
> Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
> ---
>  arch/arm/mach-socfpga/qts-filter-a10.sh | 141
> ++++++++++++++++++++++++
>  1 file changed, 141 insertions(+)
>  create mode 100755 arch/arm/mach-socfpga/qts-filter-a10.sh
> 
> diff --git a/arch/arm/mach-socfpga/qts-filter-a10.sh b/arch/arm/mach-
> socfpga/qts-filter-a10.sh
> new file mode 100755
> index 0000000000..ddb0d0a6f3
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/qts-filter-a10.sh
> @@ -0,0 +1,141 @@
> +#!/bin/bash
> +
> +#
> +# helper function to convert from DOS to Unix, if necessary, and
> handle
> +# lines ending in '\'.
> +#
> +fix_newlines_in_macros() {
> +	sed -n ':next;s/\r$//;/[^\\]\\$/ {N;s/\\\n//;b next};p' $1
> +}
> +
> +#filter out only what we need from a10 hps.xml
> +grep_a10_hps_config() {
> +	egrep "clk_hz|i_clk_mgr|i_io48_pin_mux|AXI_SLAVE|AXI_MASTER"
> +}

Above function seems unused.

> +
> +#
> +# Process hps.xml
> +# $1:	hps.xml
> +# $2:	Output File
> +#
> +process_a10_hps_config() {
> +	hps_xml="$1"
> +	outfile="$2"
> +
> +	(cat << EOF
> +/* SPDX-License-Identifier: BSD-3-Clause */
> +/*
> + * Altera Arria10 SoCFPGA configuration
> + */
> +
> +#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
> +#define __SOCFPGA_ARRIA10_CONFIG_H__
> +
> +EOF
> +
> +	echo "/* Clocks */"
> +	fix_newlines_in_macros \
> +		${hps_xml} | egrep "clk_hz" |
> +			awk -F"'" '{ gsub("\\.","_",$2) ; \
> +				print "#define" " " toupper($2) " "
> $4}' |
> +			sed 's/\.[0-9]//' |
> +			sed 's/I_CLK_MGR_//' |
> +			sort
> +	fix_newlines_in_macros \
> +		${hps_xml} | egrep "i_clk_mgr_mainpll" |
> +			awk -F"'" '{ gsub("\\.","_",$2) ; \
> +				print "#define" " " toupper($2) " "
> $4}' |
> +			sed 's/\.[0-9]//' |
> +			sed 's/I_CLK_MGR_//' |
> +			sort
> +	fix_newlines_in_macros \
> +		${hps_xml} | egrep "i_clk_mgr_perpll" |
> +			awk -F"'" '{ gsub("\\.","_",$2) ; \
> +				print "#define" " " toupper($2) " "
> $4}' |
> +			sed 's/\.[0-9]//' |
> +			sed 's/I_CLK_MGR_//' |
> +			sort
> +	fix_newlines_in_macros \
> +		${hps_xml} | egrep "i_clk_mgr_clkmgr" |
> +			awk -F"'" '{ gsub("\\.","_",$2) ; \
> +				print "#define" " " toupper($2) " "
> $4}' |
> +			sed 's/\.[0-9]//' |
> +			sed 's/I_CLK_MGR_//' |
> +			sort
> +	fix_newlines_in_macros \
> +		${hps_xml} | egrep "i_clk_mgr_alteragrp" |
> +			awk -F"'" '{ gsub("\\.","_",$2) ; \
> +				print "#define" " " toupper($2) " "
> $4}' |
> +			sed 's/\.[0-9]//' |
> +			sed 's/I_CLK_MGR_//' |
> +			sort
> +	echo "#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT <<
> 16) | \\"
> +	echo "	(ALTERAGRP_MPUCLK_MAINCNT))"
> +	echo "#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT <<
> 16) | \\"
> +	echo "	(ALTERAGRP_NOCCLK_MAINCNT))"
> +
> +	echo
> +	echo "/* Pin Mux Configuration */"
> +	fix_newlines_in_macros \
> +		${hps_xml} | egrep "i_io48_pin_mux" |
> +			awk -F"'" '{ gsub("\\.","_",$2) ; \
> +				print "#define" " " toupper($2) " "
> $4}' |
> +			sed 's/I_IO48_PIN_MUX_//' |
> +			sed 's/SHARED_3V_IO_GRP_//' |
> +			sed 's/FPGA_INTERFACE_GRP_//' |
> +			sed 's/DEDICATED_IO_GRP_//' |
> +			sed 's/CONFIGURATION_DEDICATED/CONFIG/' |
> +			sort
> +
> +	echo
> +	echo "/* Bridge Configuration */"
> +	fix_newlines_in_macros \
> +		${hps_xml} | egrep "AXI_SLAVE|AXI_MASTER" |
> +			awk -F"'" '{ gsub("\\.","_",$2) ; \
> +				print "#define" " " toupper($2) " "
> $4}' |
> +			sed 's/true/1/' |
> +			sed 's/false/0/' |
> +			sort
> +
> +	echo
> +	echo "/* Voltage Select for Config IO */"
> +	echo "#define CONFIG_IO_BANK_VSEL \\"
> +	echo "	(((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3)
> << 8) | \\"
> +	echo "	(CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))"
> +
> +	echo
> +	echo "/* Macro for Config IO bit mapping */"
> +	echo -n "#define CONFIG_IO_MACRO(NAME) "
> +	echo "(((NAME ## _RTRIM & 0xff) << 19) | \\"
> +	echo "	((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \\"
> +	echo "	((NAME ## _WK_PU_EN & 0x1) << 16) | \\"
> +	echo "	((NAME ## _PU_SLW_RT & 0x1) << 13) | \\"
> +	echo "	((NAME ## _PU_DRV_STRG & 0xf) << 8) | \\"
> +	echo "	((NAME ## _PD_SLW_RT & 0x1) << 5) | \\"
> +	echo "	(NAME ## _PD_DRV_STRG & 0x1f))"
> +
> +	cat << EOF
> +
> +#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */
> +EOF
> +	) > "${outfile}"
> +}
> +
> +usage() {
> +	echo "$0 [hps_xml] [output_file]"
> +	echo "Process QTS-generated hps.xml into devicetree header."
> +	echo ""
> +	echo "  hps_xml      - hps.xml file from hps_isw_handoff"
> +	echo "  output_file  - Output header file for dtsi include"
> +	echo ""
> +}
> +
> +hps_xml="$1"
> +outfile="$2"
> +
> +if [ "$#" -ne 2 ] ; then
> +	usage
> +	exit 1
> +fi
> +
> +process_a10_hps_config "${hps_xml}" "${outfile}"