All of lore.kernel.org
 help / color / mirror / Atom feed
From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>,
	intel-gfx@lists.freedesktop.org, "Ursulin,
	Tvrtko" <tvrtko.ursulin@intel.com>
Subject: Re: [PATCH v5 2/9] drm/i915: Define an engine class enum for the uABI
Date: Thu, 9 Nov 2017 22:16:26 +0000	[thread overview]
Message-ID: <305a46a2-6d8d-218f-223e-e61eec1dd44b@intel.com> (raw)
In-Reply-To: <151026298416.14762.7758969832220625760@mail.alporthouse.com>

On 09/11/17 21:29, Chris Wilson wrote:
> Quoting Lionel Landwerlin (2017-11-09 09:13:03)
>> On 08/11/17 19:14, Chris Wilson wrote:
>>>    
>>> +/*
>>> + * Different engines serve different roles, and there may be more than one
>>> + * engine serving each role. enum drm_i915_gem_engine_class provides a
>>> + * classification of the role of the engine, which may be used when requesting
>>> + * operations to be performed on a certain subset of engines, or for providing
>>> + * information about that group.
>>> + */
>>> +enum drm_i915_gem_engine_class {
>>> +     I915_ENGINE_CLASS_OTHER = 0,
>>> +     I915_ENGINE_CLASS_RENDER = 1,
>>> +     I915_ENGINE_CLASS_COPY = 2,
>>> +     I915_ENGINE_CLASS_VIDEO = 3,
>>> +     I915_ENGINE_CLASS_VIDEO_ENHANCE = 4,
>>> +};
>>> +
>> I've tried to build a bit UI in GPUTop to show this.
>> I'm a bit skeptical about the OTHER type because if this enum is meant
>> to be extended, then why do we need an OTHER class? We should create new
>> classes instead.
> Whilst OTHER is certainly a question of "why not add a define for the
> new class", my 2c is that we do want an explicit INVALID enum. It
> doesn't have to 0, -1 will work just fine as well, but there will be a
> time either in userspace or in reporting from the kernel where we will
> need to store an invalid value that is guaranteed not to map onto a real
> class.
>
> So I915_ENGINE_CLASS_INVALID = -1 ?
> -Chris
>
Okay, so you want to use that value for userspace to say "execute this 
batch buffer on whatever engine".
And in that case that's fine with me, I didn't get that would be used in 
the userspace->kernel direction.

But I'm still struggling to understand why the kernel would report that 
there is an "invalid" class of engine on this device, rather than 
something more descriptive.

-
Lionel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2017-11-09 22:16 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-11-08 19:14 Context isolation Chris Wilson
2017-11-08 19:14 ` [PATCH v5 1/9] drm/i915: Include engine state on detecting a missed breadcrumb/seqno Chris Wilson
2017-11-09 11:03   ` Mika Kuoppala
2017-11-09 11:12     ` Chris Wilson
2017-11-08 19:14 ` [PATCH v5 2/9] drm/i915: Define an engine class enum for the uABI Chris Wilson
2017-11-09  9:13   ` Lionel Landwerlin
2017-11-09  9:27     ` Tvrtko Ursulin
2017-11-09  9:37       ` Chris Wilson
2017-11-09 10:04         ` Tvrtko Ursulin
2017-11-09 11:13           ` Chris Wilson
2017-11-09 11:19             ` Lionel Landwerlin
2017-11-09 21:29     ` Chris Wilson
2017-11-09 22:16       ` Lionel Landwerlin [this message]
2017-11-09 22:41         ` Chris Wilson
2017-11-10 13:19   ` [PATCH v3] " Chris Wilson
2017-11-10 14:15     ` Lionel Landwerlin
2017-11-10 13:19   ` Chris Wilson
2017-11-08 19:14 ` [PATCH v5 3/9] drm/i915: Force the switch to the i915->kernel_context Chris Wilson
2017-11-08 19:14 ` [PATCH v5 4/9] drm/i915: Move GT powersaving init to i915_gem_init() Chris Wilson
2017-11-08 19:14 ` [PATCH v5 5/9] drm/i915: Move intel_init_clock_gating() " Chris Wilson
2017-11-08 19:27   ` Ville Syrjälä
2017-11-08 19:33     ` Chris Wilson
2017-11-08 19:40       ` Ville Syrjälä
2017-11-08 19:14 ` [PATCH v5 6/9] drm/i915: Inline intel_modeset_gem_init() Chris Wilson
2017-11-08 19:15 ` [PATCH v5 7/9] drm/i915: Mark the context state as dirty/written Chris Wilson
2017-11-08 19:15 ` [PATCH v5 8/9] drm/i915: Record the default hw state after reset upon load Chris Wilson
2017-11-08 19:15 ` [PATCH v5 9/9] drm/i915: Stop caching the "golden" renderstate Chris Wilson
2017-11-08 19:45 ` ✗ Fi.CI.BAT: failure for series starting with [v5,1/9] drm/i915: Include engine state on detecting a missed breadcrumb/seqno Patchwork
2017-11-08 19:54   ` Chris Wilson
2017-11-09 10:14 ` Patchwork
2017-11-10 13:41 ` ✗ Fi.CI.BAT: warning for series starting with [v5,1/9] drm/i915: Include engine state on detecting a missed breadcrumb/seqno (rev3) Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=305a46a2-6d8d-218f-223e-e61eec1dd44b@intel.com \
    --to=lionel.g.landwerlin@intel.com \
    --cc=chris@chris-wilson.co.uk \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=tvrtko.ursulin@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.