From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.6 required=3.0 tests=FROM_EXCESS_BASE64, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1155EC6778C for ; Fri, 29 Jun 2018 19:21:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C575F2756D for ; Fri, 29 Jun 2018 19:21:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C575F2756D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=siol.net Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755608AbeF2TVD convert rfc822-to-8bit (ORCPT ); Fri, 29 Jun 2018 15:21:03 -0400 Received: from mailoutvs11.siol.net ([185.57.226.202]:51711 "EHLO mail.siol.net" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753865AbeF2TVC (ORCPT ); Fri, 29 Jun 2018 15:21:02 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id DB80E5224A2; Fri, 29 Jun 2018 21:20:59 +0200 (CEST) X-Virus-Scanned: amavisd-new at psrvmta10.zcs-production.pri Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta10.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id MJu36op5NJ-9; Fri, 29 Jun 2018 21:20:59 +0200 (CEST) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id 70B89522F6C; Fri, 29 Jun 2018 21:20:59 +0200 (CEST) Received: from jernej-laptop.localnet (unknown [194.152.15.144]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPA id CCDEB5224A2; Fri, 29 Jun 2018 21:20:58 +0200 (CEST) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Chen-Yu Tsai Cc: Maxime Ripard , Rob Herring , David Airlie , Gustavo Padovan , Maarten Lankhorst , Sean Paul , Mark Rutland , dri-devel , devicetree , linux-arm-kernel , linux-kernel , linux-clk , linux-sunxi Subject: Re: [PATCH v3 16/24] drm/sun4i: Enable DW HDMI PHY clock Date: Fri, 29 Jun 2018 21:19:33 +0200 Message-ID: <3131254.YlICBQirlu@jernej-laptop> In-Reply-To: References: <20180625120304.7543-1-jernej.skrabec@siol.net> <20180625120304.7543-17-jernej.skrabec@siol.net> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Dne četrtek, 28. junij 2018 ob 04:22:36 CEST je Chen-Yu Tsai napisal(a): > On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec wrote: > > Current DW HDMI PHY code never prepares and enables PHY clock after it is > > created. It's just used as it is. This may work in some cases, but it's > > clearly wrong. Fix it by adding proper calls to enable/disable PHY > > clock. > > > > Fixes: 4f86e81748fe ("drm/sun4i: Add support for H3 HDMI PHY variant") > > > > Signed-off-by: Jernej Skrabec > > So why does it work on the H3? Because there's only one PLL that the whole > display pipeline uses? > > We should probably tag this for stable. So, > > Cc: > Reviewed-by: Chen-Yu Tsai Same question as before, how this should be handled? Can I send separate patch with same content to stable ML only? Best regards, Jernej From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jernej =?utf-8?B?xaBrcmFiZWM=?= Subject: Re: [PATCH v3 16/24] drm/sun4i: Enable DW HDMI PHY clock Date: Fri, 29 Jun 2018 21:19:33 +0200 Message-ID: <3131254.YlICBQirlu@jernej-laptop> References: <20180625120304.7543-1-jernej.skrabec@siol.net> <20180625120304.7543-17-jernej.skrabec@siol.net> Reply-To: jernej.skrabec-gGgVlfcn5nU@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Chen-Yu Tsai Cc: Maxime Ripard , Rob Herring , David Airlie , Gustavo Padovan , Maarten Lankhorst , Sean Paul , Mark Rutland , dri-devel , devicetree , linux-arm-kernel , linux-kernel , linux-clk , linux-sunxi List-Id: devicetree@vger.kernel.org Dne =C4=8Detrtek, 28. junij 2018 ob 04:22:36 CEST je Chen-Yu Tsai napisal(a= ): > On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec = =20 wrote: > > Current DW HDMI PHY code never prepares and enables PHY clock after it = is > > created. It's just used as it is. This may work in some cases, but it's > > clearly wrong. Fix it by adding proper calls to enable/disable PHY > > clock. > >=20 > > Fixes: 4f86e81748fe ("drm/sun4i: Add support for H3 HDMI PHY variant") > >=20 > > Signed-off-by: Jernej Skrabec >=20 > So why does it work on the H3? Because there's only one PLL that the whol= e > display pipeline uses? >=20 > We should probably tag this for stable. So, >=20 > Cc: > Reviewed-by: Chen-Yu Tsai Same question as before, how this should be handled? Can I send separate pa= tch=20 with same content to stable ML only? Best regards, Jernej --=20 You received this message because you are subscribed to the Google Groups "= linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an e= mail to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org For more options, visit https://groups.google.com/d/optout. From mboxrd@z Thu Jan 1 00:00:00 1970 From: jernej.skrabec@siol.net (Jernej =?utf-8?B?xaBrcmFiZWM=?=) Date: Fri, 29 Jun 2018 21:19:33 +0200 Subject: [PATCH v3 16/24] drm/sun4i: Enable DW HDMI PHY clock In-Reply-To: References: <20180625120304.7543-1-jernej.skrabec@siol.net> <20180625120304.7543-17-jernej.skrabec@siol.net> Message-ID: <3131254.YlICBQirlu@jernej-laptop> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Dne ?etrtek, 28. junij 2018 ob 04:22:36 CEST je Chen-Yu Tsai napisal(a): > On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec wrote: > > Current DW HDMI PHY code never prepares and enables PHY clock after it is > > created. It's just used as it is. This may work in some cases, but it's > > clearly wrong. Fix it by adding proper calls to enable/disable PHY > > clock. > > > > Fixes: 4f86e81748fe ("drm/sun4i: Add support for H3 HDMI PHY variant") > > > > Signed-off-by: Jernej Skrabec > > So why does it work on the H3? Because there's only one PLL that the whole > display pipeline uses? > > We should probably tag this for stable. So, > > Cc: > Reviewed-by: Chen-Yu Tsai Same question as before, how this should be handled? Can I send separate patch with same content to stable ML only? Best regards, Jernej