From: Rebecca Cran <rebecca@nuviainc.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>
Subject: Re: [PATCH v4 2/4] target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
Date: Sun, 7 Feb 2021 23:50:48 -0700 [thread overview]
Message-ID: <3134cfab-7455-dbdf-29e0-11643340efde@nuviainc.com> (raw)
In-Reply-To: <a85fa6f0-d6ee-5811-4c7f-d2830b8eafb9@linaro.org>
On 2/3/21 10:19 AM, Richard Henderson wrote:
> On 2/2/21 6:58 PM, Rebecca Cran wrote:
>> @@ -9433,8 +9448,9 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
>> * For exceptions taken to AArch32 we must clear the SS bit in both
>> * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
>> */
>> - env->uncached_cpsr &= ~PSTATE_SS;
>> - env->spsr = cpsr_read(env);
>> + env->pstate &= ~PSTATE_SS;
>> + env->spsr = cpsr_read_for_spsr_elx(env);
>> +
>
> Again, this is the aarch32 exception path, and should not use
> cpsr_read_for_spsr_elx.
Yeah, sorry I'm not sure why/how that got in.
I'm hoping the v5 series that I'm sending out in a few minutes fixes
these issues.
--
Rebecca Cran
next prev parent reply other threads:[~2021-02-08 11:32 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-03 4:58 [PATCH v4 0/4] target/arm: Add support for FEAT_DIT, Data Independent Timing Rebecca Cran
2021-02-03 4:58 ` [PATCH v4 1/4] " Rebecca Cran
2021-02-03 4:58 ` [PATCH v4 2/4] target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate Rebecca Cran
2021-02-03 17:17 ` Richard Henderson
2021-02-03 20:28 ` Rebecca Cran
2021-02-03 20:36 ` Richard Henderson
2021-02-03 17:19 ` Richard Henderson
2021-02-08 6:50 ` Rebecca Cran [this message]
2021-02-03 4:58 ` [PATCH v4 3/4] target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU Rebecca Cran
2021-02-03 4:58 ` [PATCH v4 4/4] target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU Rebecca Cran
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