[PATCH-for-6.0?] target/mips: Fix TCG temporary leak in gen_cache_operation()

[PATCH-for-6.0?] target/mips: Fix TCG temporary leak in gen_cache_operation()

[Philippe Mathieu-Daudé]

Fix a TCG temporary leak when translating CACHE opcode.

Fixes: 0d74a222c27 ("make ITC Configuration Tags accessible to the CPU")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index c518bf3963b..71fa5ec1973 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -12804,6 +12804,8 @@ static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base,
     TCGv t1 = tcg_temp_new();
     gen_base_offset_addr(ctx, t1, base, offset);
     gen_helper_cache(cpu_env, t1, t0);
+    tcg_temp_free(t1);
+    tcg_temp_free_i32(t0);
 }
 
 #if defined(TARGET_MIPS64)
-- 
2.26.3

Re: [PATCH-for-6.0?] target/mips: Fix TCG temporary leak in gen_cache_operation()

[Richard Henderson]

On 4/6/21 1:28 PM, Philippe Mathieu-Daudé wrote:
> Fix a TCG temporary leak when translating CACHE opcode.
> 
> Fixes: 0d74a222c27 ("make ITC Configuration Tags accessible to the CPU")
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/translate.c | 2 ++
>   1 file changed, 2 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~