From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 694AFC433EF for ; Mon, 20 Jun 2022 14:55:54 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2A67381970; Mon, 20 Jun 2022 16:55:52 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1655736952; bh=9jUvyhiCL/C1fiteTKjVAMY582Ybzs6UZZf/A9QOZgc=; h=Date:Subject:To:Cc:References:From:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=mBrWzSBJViOX3u5CW41mOhb/WQ1SqfrRlQd752N6xDFmw14i3+naz6XIOhPAeLrvX 66dg578Qha1RJzBMu5KLflh9zu3sy0nCP/DS/NapUzjg8IrEYS8L+VNz5FfFiEysN4 vz8+ONWoDnEZ2kHTUhe1D3xPfyffNBHlzmgbcY3u/VI8N1OZDql787OVA+jX/bVrQ5 FaQipga5daNlT8oMPGPlb+7hW+4fDPsEyT/hTSIm19lbckdsI+VSoa4ohDy9+cNVlc ly3/rG/IWgJTJONGaM8+3wGLb0Cr/QpEDkFKtRRS+BgmJODS9c7PB9YNoP0CGMXqHI iKFW6EDAZ2PYw== Received: by phobos.denx.de (Postfix, from userid 109) id 36AD781A02; Mon, 20 Jun 2022 16:55:50 +0200 (CEST) Received: from mout-u-204.mailbox.org (mout-u-204.mailbox.org [IPv6:2001:67c:2050:101:465::204]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C792180F88 for ; Mon, 20 Jun 2022 16:55:47 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sr@denx.de Received: from smtp1.mailbox.org (smtp1.mailbox.org [IPv6:2001:67c:2050:b231:465::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-204.mailbox.org (Postfix) with ESMTPS id 4LRXl56grsz9sQF; Mon, 20 Jun 2022 16:55:45 +0200 (CEST) Message-ID: <31663304-da94-67af-163c-d82ec75322bd@denx.de> Date: Mon, 20 Jun 2022 16:55:44 +0200 MIME-Version: 1.0 Subject: Re: [PATCH v2] watchdog: add amlogic watchdog support Content-Language: en-US To: Philippe Boos , Neil Armstrong Cc: u-boot@lists.denx.de, u-boot-amlogic@groups.io, Jerome Brunet , Alexandre Bailon References: <20220613140056.10316-1-pboos@baylibre.com> From: Stefan Roese In-Reply-To: <20220613140056.10316-1-pboos@baylibre.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 4LRXl56grsz9sQF X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On 13.06.22 16:00, Philippe Boos wrote: > Add support for hardware watchdog timer for Amlogic SoCs. > This driver has been heavily inspired by his Linux equivalent > (meson_gxbb_wdt.c). > > Reviewed-by: Jerome Brunet > Reviewed-by: Neil Armstrong > > Signed-off-by: Philippe Boos > Reviewed-by: Stefan Roese Thanks, Stefan > --- > > Your recommendations have been implemented. I let you check this version 2. > The reset works well when triggered by the wdt command in u-boot. > > This watchdog driver has been tested on a GXL libretech-cc board and also on > a custom G12a board. I did the following test cases: > * boot with a faulty boot command, then we reach watchdog reset successfully, > * boot a Linux kernel with and without watchdog support, and check if it is > working as expected. > > > MAINTAINERS | 1 + > doc/board/amlogic/index.rst | 2 + > drivers/watchdog/Kconfig | 7 ++ > drivers/watchdog/Makefile | 1 + > drivers/watchdog/meson_gxbb_wdt.c | 136 ++++++++++++++++++++++++++++++ > 5 files changed, 147 insertions(+) > create mode 100644 drivers/watchdog/meson_gxbb_wdt.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 28e4d38238..ab3ef041f7 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -160,6 +160,7 @@ F: drivers/spi/meson_spifc.c > F: drivers/pinctrl/meson/ > F: drivers/power/domain/meson-gx-pwrc-vpu.c > F: drivers/video/meson/ > +F: drivers/watchdog/meson_gxbb_wdt.c > F: include/configs/meson64.h > F: include/configs/meson64_android.h > F: doc/board/amlogic/ > diff --git a/doc/board/amlogic/index.rst b/doc/board/amlogic/index.rst > index 9c7fadf2c0..cc2ba50889 100644 > --- a/doc/board/amlogic/index.rst > +++ b/doc/board/amlogic/index.rst > @@ -73,6 +73,8 @@ This matrix concerns the actual source code version. > +-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ > | PCIe (+NVMe) | *N/A* | *N/A* | *N/A* | **Yes** | **Yes** | **Yes** | **Yes** | > +-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ > +| Watchdog | *N/A* | **Yes** | *N/A* | *N/A* | *N/A* | *N/A* | *N/A* | > ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ > > Boot Documentation > ------------------ > diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig > index c3eb8a8aec..da0fa5396f 100644 > --- a/drivers/watchdog/Kconfig > +++ b/drivers/watchdog/Kconfig > @@ -175,6 +175,13 @@ config WDT_MAX6370 > help > Select this to enable max6370 watchdog timer. > > +config WDT_MESON_GXBB > + bool "Amlogic watchdog timer support" > + depends on WDT > + help > + Select this to enable Meson watchdog timer, > + which can be found on some Amlogic platforms. > + > config WDT_MPC8xx > bool "MPC8xx watchdog timer support" > depends on WDT && MPC8xx > diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile > index 1f6199beca..0e2f582a5f 100644 > --- a/drivers/watchdog/Makefile > +++ b/drivers/watchdog/Makefile > @@ -27,6 +27,7 @@ obj-$(CONFIG_WDT_ORION) += orion_wdt.o > obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o > obj-$(CONFIG_WDT_GPIO) += gpio_wdt.o > obj-$(CONFIG_WDT_MAX6370) += max6370_wdt.o > +obj-$(CONFIG_WDT_MESON_GXBB) += meson_gxbb_wdt.o > obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o > obj-$(CONFIG_WDT_MT7620) += mt7620_wdt.o > obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o > diff --git a/drivers/watchdog/meson_gxbb_wdt.c b/drivers/watchdog/meson_gxbb_wdt.c > new file mode 100644 > index 0000000000..6ab005813f > --- /dev/null > +++ b/drivers/watchdog/meson_gxbb_wdt.c > @@ -0,0 +1,136 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (c) 2022 BayLibre, SAS. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define GXBB_WDT_CTRL_REG 0x0 > +#define GXBB_WDT_TCNT_REG 0x8 > +#define GXBB_WDT_RSET_REG 0xc > + > +#define GXBB_WDT_CTRL_SYS_RESET_NOW BIT(26) > +#define GXBB_WDT_CTRL_CLKDIV_EN BIT(25) > +#define GXBB_WDT_CTRL_CLK_EN BIT(24) > +#define GXBB_WDT_CTRL_EE_RESET BIT(21) > +#define GXBB_WDT_CTRL_EN BIT(18) > + > +#define GXBB_WDT_CTRL_DIV_MASK GENMASK(17, 0) > +#define GXBB_WDT_TCNT_SETUP_MASK GENMASK(15, 0) > + > + > +struct amlogic_wdt_priv { > + void __iomem *reg_base; > +}; > + > +static int amlogic_wdt_set_timeout(struct udevice *dev, u64 timeout_ms) > +{ > + struct amlogic_wdt_priv *data = dev_get_priv(dev); > + > + if (timeout_ms > GXBB_WDT_TCNT_SETUP_MASK) { > + dev_warn(dev, "%s: timeout_ms=%llu: maximum watchdog timeout exceeded\n", > + __func__, timeout_ms); > + timeout_ms = GXBB_WDT_TCNT_SETUP_MASK; > + } > + > + writel(timeout_ms, data->reg_base + GXBB_WDT_TCNT_REG); > + > + return 0; > +} > + > +static int amlogic_wdt_stop(struct udevice *dev) > +{ > + struct amlogic_wdt_priv *data = dev_get_priv(dev); > + > + writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) & ~GXBB_WDT_CTRL_EN, > + data->reg_base + GXBB_WDT_CTRL_REG); > + > + return 0; > +} > + > +static int amlogic_wdt_start(struct udevice *dev, u64 time_ms, ulong flags) > +{ > + struct amlogic_wdt_priv *data = dev_get_priv(dev); > + > + writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) | GXBB_WDT_CTRL_EN, > + data->reg_base + GXBB_WDT_CTRL_REG); > + > + return amlogic_wdt_set_timeout(dev, time_ms); > +} > + > +static int amlogic_wdt_reset(struct udevice *dev) > +{ > + struct amlogic_wdt_priv *data = dev_get_priv(dev); > + > + writel(0, data->reg_base + GXBB_WDT_RSET_REG); > + > + return 0; > +} > + > +static int amlogic_wdt_expire_now(struct udevice *dev, ulong flags) > +{ > + struct amlogic_wdt_priv *data = dev_get_priv(dev); > + > + writel(0, data->reg_base + GXBB_WDT_CTRL_SYS_RESET_NOW); > + > + return 0; > +} > + > +static int amlogic_wdt_probe(struct udevice *dev) > +{ > + struct amlogic_wdt_priv *data = dev_get_priv(dev); > + int ret; > + > + data->reg_base = dev_remap_addr(dev); > + if (!data->reg_base) > + return -EINVAL; > + > + struct clk clk; > + > + ret = clk_get_by_index(dev, 0, &clk); > + if (ret) > + return ret; > + > + ret = clk_enable(&clk); > + if (ret) { > + clk_free(&clk); > + return ret; > + } > + > + /* Setup with 1ms timebase */ > + writel(((clk_get_rate(&clk) / 1000) & GXBB_WDT_CTRL_DIV_MASK) | > + GXBB_WDT_CTRL_EE_RESET | > + GXBB_WDT_CTRL_CLK_EN | > + GXBB_WDT_CTRL_CLKDIV_EN, > + data->reg_base + GXBB_WDT_CTRL_REG); > + > + return 0; > +} > + > +static const struct wdt_ops amlogic_wdt_ops = { > + .start = amlogic_wdt_start, > + .reset = amlogic_wdt_reset, > + .stop = amlogic_wdt_stop, > + .expire_now = amlogic_wdt_expire_now, > +}; > + > +static const struct udevice_id amlogic_wdt_ids[] = { > + { .compatible = "amlogic,meson-gxbb-wdt" }, > + {} > +}; > + > +U_BOOT_DRIVER(amlogic_wdt) = { > + .name = "amlogic_wdt", > + .id = UCLASS_WDT, > + .of_match = amlogic_wdt_ids, > + .priv_auto = sizeof(struct amlogic_wdt_priv), > + .probe = amlogic_wdt_probe, > + .ops = &amlogic_wdt_ops, > + .flags = DM_FLAG_PRE_RELOC, > +}; Viele Grüße, Stefan Roese -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de