[PATCH v4,04/10] Add the MIPS32R2 'ins' and 'ext' instructions for use by the kernel's micro-assembler.

[PATCH v4,04/10] Add the MIPS32R2 'ins' and 'ext' instructions for use by the kernel's micro-assembler.

[Steven J. Hill]

From: "Steven J. Hill" <sjhill@mips.com>

Signed-off-by: Steven J. Hill <sjhill@mips.com>
---
 arch/mips/include/asm/uasm.h |  2 ++
 arch/mips/mm/uasm.c          | 15 +++++++++++++--
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 53db9d7..5c7fc47 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -92,6 +92,8 @@ Ip_u2u1u3(_dsrl);
 Ip_u2u1u3(_dsrl32);
 Ip_u3u1u2(_dsubu);
 Ip_0(_eret);
+Ip_u2u1msbu3(_ext);
+Ip_u2u1msbu3(_ins);
 Ip_u1(_j);
 Ip_u1(_jal);
 Ip_u1(_jr);
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index 5fa1851..663b6b1 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -63,8 +63,8 @@ enum opcode {
 	insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
 	insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
 	insn_dsrl32, insn_drotr, insn_drotr32, insn_dsubu, insn_eret,
-	insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld,
-	insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori,
+	insn_ext, insn_ins, insn_j, insn_jal, insn_jr, insn_ld, insn_ll,
+	insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori,
 	insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
 	insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp,
 	insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
@@ -113,6 +113,8 @@ static struct insn insn_table[] __uasminitdata = {
 	{ insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
 	{ insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
 	{ insn_eret,  M(cop0_op, cop_op, 0, 0, 0, eret_op),  0 },
+	{ insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE },
+	{ insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE },
 	{ insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
 	{ insn_jal,  M(jal_op, 0, 0, 0, 0, 0),  JIMM },
 	{ insn_jr,  M(spec_op, 0, 0, 0, 0, jr_op),  RS },
@@ -343,6 +345,13 @@ Ip_u2u1msbu3(op)					\
 }							\
 UASM_EXPORT_SYMBOL(uasm_i##op);
 
+#define I_u2u1mmsbu3(op) 				\
+Ip_u2u1msbu3(op)					\
+{							\
+	build_insn(buf, insn##op, b, a, d-1, c);	\
+}							\
+UASM_EXPORT_SYMBOL(uasm_i##op);
+
 #define I_u1u2(op)					\
 Ip_u1u2(op)						\
 {							\
@@ -396,6 +405,8 @@ I_u2u1u3(_drotr)
 I_u2u1u3(_drotr32)
 I_u3u1u2(_dsubu)
 I_0(_eret)
+I_u2u1mmsbu3(_ext)
+I_u2u1msbu3(_ins)
 I_u1(_j)
 I_u1(_jal)
 I_u1(_jr)
-- 
1.7.11.1

Re: [PATCH v4,04/10] Add the MIPS32R2 'ins' and 'ext' instructions for use by the kernel's micro-assembler.

[Sergei Shtylyov]

Hello.

On 29-06-2012 22:35, Steven J. Hill wrote:

> From: "Steven J. Hill"<sjhill@mips.com>

> Signed-off-by: Steven J. Hill<sjhill@mips.com>
[...]

> diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
> index 5fa1851..663b6b1 100644
> --- a/arch/mips/mm/uasm.c
> +++ b/arch/mips/mm/uasm.c
[...]
> @@ -343,6 +345,13 @@ Ip_u2u1msbu3(op)					\
>   }							\
>   UASM_EXPORT_SYMBOL(uasm_i##op);
>
> +#define I_u2u1mmsbu3(op) 				\
> +Ip_u2u1msbu3(op)					\
> +{							\
> +	build_insn(buf, insn##op, b, a, d-1, c);	\
> +}							\
> +UASM_EXPORT_SYMBOL(uasm_i##op);
> +
>   #define I_u1u2(op)					\
>   Ip_u1u2(op)						\
>   {							\
> @@ -396,6 +405,8 @@ I_u2u1u3(_drotr)
>   I_u2u1u3(_drotr32)
>   I_u3u1u2(_dsubu)
>   I_0(_eret)
> +I_u2u1mmsbu3(_ext)
> +I_u2u1msbu3(_ins)

    Not I_u2u1mmsbu3()?

WBR, Sergei

RE: [PATCH v4,04/10] Add the MIPS32R2 'ins' and 'ext' instructions for use by the kernel's micro-assembler.

[Hill, Steven]

>> @@ -396,6 +405,8 @@ I_u2u1u3(_drotr)
>>   I_u2u1u3(_drotr32)
>>   I_u3u1u2(_dsubu)
>>   I_0(_eret)
>> +I_u2u1mmsbu3(_ext)
>> +I_u2u1msbu3(_ins)
>
>   Not I_u2u1mmsbu3()?
>
No, the 'ins' instruction opcode layout is identical to the 'dins' instruction. Thus, it is correct.