* [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree
@ 2018-10-20 7:14 Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 01/29] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann
` (29 more replies)
0 siblings, 30 replies; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
Hi,
this patchset converts the RISC-V decoder to decodetree in three major steps:
1) Convert 32-bit instructions to decodetree [Patch 1-14]:
Many of the gen_* functions are called by the decode functions for 16-bit
and 32-bit functions. If we move translation code from the gen_*
functions to the generated trans_* functions of decode-tree, we get a lot of
duplication. Therefore, we mostly generate calls to the old gen_* function
which are properly replaced after step 2).
Each of the trans_ functions are grouped into files corresponding to their
ISA extension, e.g. addi which is in RV32I is translated in the file
'trans_rvi.inc.c'.
2) Convert 16-bit instructions to decodetree [Patch 15-17]:
All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
we convert the arguments in the 16 bit trans_ function to the arguments of
the corresponding 32 bit instruction and call the 32 bit trans_ function.
3) Remove old manual decoding in gen_* function [Patch 17-28]:
this move all manual translation code into the trans_* instructions of
decode tree, such that we can remove the old decode_* functions.
the full tree can be found here:
https://github.com/bkoppelmann/qemu/tree/riscv-dt-v2
Cheers,
Bastian
v1->v2:
- ex_shift_amount returns uint32_t
- use ctx->env instead of current_cpu->env_ptr
- fixed functionspacing
- RISCV32 now returns false instead of raising an exception
- shift translators now also use gen_arithm_imm()
- simplified fence/fence_i as suggested by Richard
- simplified gen_amo() with function pointers
- rs2 @atom_ld is now decimal
- use simplfied gen_amo() with function pointers
- REQUIRE_FPU uses do {} while (0)
- Add REQUIRE_FPU to arithm helpers
- RISCV32 now returns false instead of raising an exception
- Add REQUIRE_FPU to arithm helpers
- Stack allocate arg_c_* structs
- ex_rvc_register returns int
- special case of trans_c_addi4spn() returns false
- consistently return false for reserved cases instead of raising an
exception
- simplified trans_c_srli by Richard's suggestion
- remove extract_cj() since its result isn't used
- trans_branch -> gen_branch
- trans_load -> gen_load
- removed negative memop check
- trans_store -> gen_store
- removed negative memop check
- trans_arith_imm -> gen_arith_imm
- Add missing TARGET_RISC64 checks
- Reimplement shift translators that were omited in [0004/0028]
- trans_shift -> gen_shift
- Add missing TARGET_RISCV64 conditions
- trans_arith_w -> gen_arith_w
- Add missing gen_exception_illegal
- dropped 0028
Bastian Koppelmann (29):
target/riscv: Move CPURISCVState pointer to DisasContext
targer/riscv: Activate decodetree and implemnt LUI & AUIPC
target/riscv: Convert RVXI branch insns to decodetree
target/riscv: Convert RVXI load/store insns to decodetree
target/riscv: Convert RVXI arithmetic insns to decodetree
target/riscv: Convert RVXI fence insns to decodetree
target/riscv: Convert RVXI csr insns to decodetree
target/riscv: Convert RVXM insns to decodetree
target/riscv: Convert RV32A insns to decodetree
target/riscv: Convert RV64A insns to decodetree
target/riscv: Convert RV32F insns to decodetree
target/riscv: Convert RV64F insns to decodetree
target/riscv: Convert RV32D insns to decodetree
target/riscv: Convert RV64D insns to decodetree
target/riscv: Convert RV priv insns to decodetree
target/riscv: Convert quadrant 0 of RVXC insns to decodetree
target/riscv: Convert quadrant 1 of RVXC insns to decodetree
target/riscv: Convert quadrant 2 of RVXC insns to decodetree
target/riscv: Remove gen_jalr()
target/riscv: Remove manual decoding from gen_branch()
target/riscv: Remove manual decoding from gen_load()
target/riscv: Remove manual decoding from gen_store()
target/riscv: Move gen_arith_imm() decoding into trans_* functions
target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
target/riscv: Remove shift and slt insn manual decoding
target/riscv: Remove manual decoding of RV32/64M insn
target/riscv: Remove gen_system()
target/riscv: Remove decode_RV32_64G()
target/riscv: Rename trans_arith to gen_arith
target/riscv/Makefile.objs | 17 +
target/riscv/insn16.decode | 126 ++
target/riscv/insn32.decode | 256 +++
.../riscv/insn_trans/trans_privileged.inc.c | 111 ++
target/riscv/insn_trans/trans_rva.inc.c | 244 +++
target/riscv/insn_trans/trans_rvc.inc.c | 337 ++++
target/riscv/insn_trans/trans_rvd.inc.c | 413 ++++
target/riscv/insn_trans/trans_rvf.inc.c | 402 ++++
target/riscv/insn_trans/trans_rvi.inc.c | 629 ++++++
target/riscv/insn_trans/trans_rvm.inc.c | 125 ++
target/riscv/translate.c | 1756 ++---------------
11 files changed, 2853 insertions(+), 1563 deletions(-)
create mode 100644 target/riscv/insn16.decode
create mode 100644 target/riscv/insn32.decode
create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c
create mode 100644 target/riscv/insn_trans/trans_rva.inc.c
create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c
create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c
create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c
create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c
--
2.19.1
^ permalink raw reply [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 01/29] target/riscv: Move CPURISCVState pointer to DisasContext
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-25 16:38 ` Palmer Dabbelt
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 02/29] targer/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
` (28 subsequent siblings)
29 siblings, 1 reply; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
CPURISCVState is rarely used, so there is no need to pass it to every
translate function. This paves the way for decodetree which only passes
DisasContext to translate functions.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/riscv/translate.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 18d7b6d147..e81b9f097e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -52,6 +52,7 @@ typedef struct DisasContext {
to any system register, which includes CSR_FRM, so we do not have
to reset this known value. */
int frm;
+ CPURISCVState *env;
} DisasContext;
/* convert riscv funct3 to qemu memop for load/store */
@@ -1789,19 +1790,19 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
}
}
-static void decode_opc(CPURISCVState *env, DisasContext *ctx)
+static void decode_opc(DisasContext *ctx)
{
/* check for compressed insn */
if (extract32(ctx->opcode, 0, 2) != 3) {
- if (!riscv_has_ext(env, RVC)) {
+ if (!riscv_has_ext(ctx->env, RVC)) {
gen_exception_illegal(ctx);
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 2;
- decode_RV32_64C(env, ctx);
+ decode_RV32_64C(ctx->env, ctx);
}
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 4;
- decode_RV32_64G(env, ctx);
+ decode_RV32_64G(ctx->env, ctx);
}
}
@@ -1846,10 +1847,10 @@ static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPURISCVState *env = cpu->env_ptr;
+ ctx->env = cpu->env_ptr;
- ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
- decode_opc(env, ctx);
+ ctx->opcode = cpu_ldl_code(ctx->env, ctx->base.pc_next);
+ decode_opc(ctx);
ctx->base.pc_next = ctx->pc_succ_insn;
if (ctx->base.is_jmp == DISAS_NEXT) {
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 02/29] targer/riscv: Activate decodetree and implemnt LUI & AUIPC
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 01/29] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-20 19:32 ` Richard Henderson
2018-10-25 16:58 ` Palmer Dabbelt
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 03/29] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
` (27 subsequent siblings)
29 siblings, 2 replies; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
for now only LUI & AUIPC are decoded and translated. If decodetree fails, we
fall back to the old decoder.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v1 -> v2:
- ex_shift_amount returns uint32_t
target/riscv/Makefile.objs | 10 +++++++
target/riscv/insn32.decode | 30 +++++++++++++++++++++
target/riscv/insn_trans/trans_rvi.inc.c | 35 +++++++++++++++++++++++++
target/riscv/translate.c | 24 ++++++++++++-----
4 files changed, 92 insertions(+), 7 deletions(-)
create mode 100644 target/riscv/insn32.decode
create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index abd0a7cde3..ea02f9b9ef 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -1 +1,11 @@
obj-y += translate.o op_helper.o helper.o cpu.o fpu_helper.o gdbstub.o pmp.o
+
+DECODETREE = $(SRC_PATH)/scripts/decodetree.py
+
+target/riscv/decode_insn32.inc.c: \
+ $(SRC_PATH)/target/riscv/insn32.decode $(DECODETREE)
+ $(call quiet-command, \
+ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $<, \
+ "GEN", $(TARGET_DIR)$@)
+
+target/riscv/translate.o: target/riscv/decode_insn32.inc.c
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
new file mode 100644
index 0000000000..44d4e922b6
--- /dev/null
+++ b/target/riscv/insn32.decode
@@ -0,0 +1,30 @@
+#
+# RISC-V translation routines for the RVXI Base Integer Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see <http://www.gnu.org/licenses/>.
+
+# Fields:
+%rd 7:5
+
+# immediates:
+%imm_u 12:s20 !function=ex_shift_12
+
+# Formats 32:
+@u .................... ..... ....... imm=%imm_u %rd
+
+# *** RV32I Base Instruction Set ***
+lui .................... ..... 0110111 @u
+auipc .................... ..... 0010111 @u
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
new file mode 100644
index 0000000000..aee0d1637d
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -0,0 +1,35 @@
+/*
+ * RISC-V translation routines for the RVXI Base Integer Instruction Set.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_lui(DisasContext *ctx, arg_lui *a, uint32_t insn)
+{
+ if (a->rd != 0) {
+ tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
+ }
+ return true;
+}
+
+static bool trans_auipc(DisasContext *ctx, arg_auipc *a, uint32_t insn)
+{
+ if (a->rd != 0) {
+ tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next);
+ }
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index e81b9f097e..65a323a201 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1667,6 +1667,19 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
}
}
+#define EX_SH(amount) \
+ static int32_t ex_shift_##amount(int imm) \
+ { \
+ return imm << amount; \
+ }
+EX_SH(12)
+
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
+/* Include the auto-generated decoder for 32 bit insn */
+#include "decode_insn32.inc.c"
+/* Include insn module translation function */
+#include "insn_trans/trans_rvi.inc.c"
+
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
int rs1;
@@ -1687,12 +1700,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
imm = GET_IMM(ctx->opcode);
switch (op) {
- case OPC_RISC_LUI:
- if (rd == 0) {
- break; /* NOP */
- }
- tcg_gen_movi_tl(cpu_gpr[rd], sextract64(ctx->opcode, 12, 20) << 12);
- break;
case OPC_RISC_AUIPC:
if (rd == 0) {
break; /* NOP */
@@ -1802,7 +1809,10 @@ static void decode_opc(DisasContext *ctx)
}
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 4;
- decode_RV32_64G(ctx->env, ctx);
+ if (!decode_insn32(ctx, ctx->opcode)) {
+ /* fallback to old decoder */
+ decode_RV32_64G(ctx->env, ctx);
+ }
}
}
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 03/29] target/riscv: Convert RVXI branch insns to decodetree
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 01/29] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 02/29] targer/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-20 19:34 ` Richard Henderson
2018-10-25 20:24 ` Palmer Dabbelt
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 04/29] target/riscv: Convert RVXI load/store " Bastian Koppelmann
` (26 subsequent siblings)
29 siblings, 2 replies; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v1 -> v2:
- use ctx->env instead of current_cpu->env_ptr
target/riscv/insn32.decode | 19 ++++++++++
target/riscv/insn_trans/trans_rvi.inc.c | 49 +++++++++++++++++++++++++
target/riscv/translate.c | 19 +---------
3 files changed, 69 insertions(+), 18 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 44d4e922b6..b49913416d 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -17,14 +17,33 @@
# this program. If not, see <http://www.gnu.org/licenses/>.
# Fields:
+%rs2 20:5
+%rs1 15:5
%rd 7:5
# immediates:
+%imm_i 20:s12
+%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
+%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
%imm_u 12:s20 !function=ex_shift_12
+# Argument sets:
+&branch imm rs2 rs1
+
# Formats 32:
+@i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd
+@b ....... ..... ..... ... ..... ....... &branch imm=%imm_b %rs2 %rs1
@u .................... ..... ....... imm=%imm_u %rd
+@j .................... ..... ....... imm=%imm_j %rd
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
auipc .................... ..... 0010111 @u
+jal .................... ..... 1101111 @j
+jalr ............ ..... 000 ..... 1100111 @i
+beq ....... ..... ..... 000 ..... 1100011 @b
+bne ....... ..... ..... 001 ..... 1100011 @b
+blt ....... ..... ..... 100 ..... 1100011 @b
+bge ....... ..... ..... 101 ..... 1100011 @b
+bltu ....... ..... ..... 110 ..... 1100011 @b
+bgeu ....... ..... ..... 111 ..... 1100011 @b
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index aee0d1637d..3935a80ba5 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -33,3 +33,52 @@ static bool trans_auipc(DisasContext *ctx, arg_auipc *a, uint32_t insn)
}
return true;
}
+
+static bool trans_jal(DisasContext *ctx, arg_jal *a, uint32_t insn)
+{
+ gen_jal(ctx->env, ctx, a->rd, a->imm);
+ return true;
+}
+
+static bool trans_jalr(DisasContext *ctx, arg_jalr *a, uint32_t insn)
+{
+ gen_jalr(ctx->env, ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_beq(DisasContext *ctx, arg_beq *a, uint32_t insn)
+{
+ gen_branch(ctx->env, ctx, OPC_RISC_BEQ, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_bne(DisasContext *ctx, arg_bne *a, uint32_t insn)
+{
+ gen_branch(ctx->env, ctx, OPC_RISC_BNE, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_blt(DisasContext *ctx, arg_blt *a, uint32_t insn)
+{
+ gen_branch(ctx->env, ctx, OPC_RISC_BLT, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_bge(DisasContext *ctx, arg_bge *a, uint32_t insn)
+{
+ gen_branch(ctx->env, ctx, OPC_RISC_BGE, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_bltu(DisasContext *ctx, arg_bltu *a, uint32_t insn)
+{
+ gen_branch(ctx->env, ctx, OPC_RISC_BLTU, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a, uint32_t insn)
+{
+
+ gen_branch(ctx->env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 65a323a201..9b6848e666 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1672,6 +1672,7 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
{ \
return imm << amount; \
}
+EX_SH(1)
EX_SH(12)
bool decode_insn32(DisasContext *ctx, uint32_t insn);
@@ -1700,24 +1701,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
imm = GET_IMM(ctx->opcode);
switch (op) {
- case OPC_RISC_AUIPC:
- if (rd == 0) {
- break; /* NOP */
- }
- tcg_gen_movi_tl(cpu_gpr[rd], (sextract64(ctx->opcode, 12, 20) << 12) +
- ctx->base.pc_next);
- break;
- case OPC_RISC_JAL:
- imm = GET_JAL_IMM(ctx->opcode);
- gen_jal(env, ctx, rd, imm);
- break;
- case OPC_RISC_JALR:
- gen_jalr(env, ctx, MASK_OP_JALR(ctx->opcode), rd, rs1, imm);
- break;
- case OPC_RISC_BRANCH:
- gen_branch(env, ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2,
- GET_B_IMM(ctx->opcode));
- break;
case OPC_RISC_LOAD:
gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm);
break;
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 04/29] target/riscv: Convert RVXI load/store insns to decodetree
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (2 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 03/29] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 05/29] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
` (25 subsequent siblings)
29 siblings, 0 replies; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v1 -> v2:
- fixed spacing
target/riscv/insn32.decode | 15 +++++
target/riscv/insn_trans/trans_rvi.inc.c | 78 +++++++++++++++++++++++++
target/riscv/translate.c | 7 ---
3 files changed, 93 insertions(+), 7 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b49913416d..badd1d9216 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -23,6 +23,7 @@
# immediates:
%imm_i 20:s12
+%imm_s 25:s7 7:5
%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
%imm_u 12:s20 !function=ex_shift_12
@@ -33,6 +34,7 @@
# Formats 32:
@i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd
@b ....... ..... ..... ... ..... ....... &branch imm=%imm_b %rs2 %rs1
+@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1
@u .................... ..... ....... imm=%imm_u %rd
@j .................... ..... ....... imm=%imm_j %rd
@@ -47,3 +49,16 @@ blt ....... ..... ..... 100 ..... 1100011 @b
bge ....... ..... ..... 101 ..... 1100011 @b
bltu ....... ..... ..... 110 ..... 1100011 @b
bgeu ....... ..... ..... 111 ..... 1100011 @b
+lb ............ ..... 000 ..... 0000011 @i
+lh ............ ..... 001 ..... 0000011 @i
+lw ............ ..... 010 ..... 0000011 @i
+lbu ............ ..... 100 ..... 0000011 @i
+lhu ............ ..... 101 ..... 0000011 @i
+sb ....... ..... ..... 000 ..... 0100011 @s
+sh ....... ..... ..... 001 ..... 0100011 @s
+sw ....... ..... ..... 010 ..... 0100011 @s
+
+# *** RV64I Base Instruction Set (in addition to RV32I) ***
+lwu ............ ..... 110 ..... 0000011 @i
+ld ............ ..... 011 ..... 0000011 @i
+sd ....... ..... ..... 011 ..... 0100011 @s
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 3935a80ba5..2c8ecff76f 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -82,3 +82,81 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a, uint32_t insn)
gen_branch(ctx->env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
return true;
}
+
+static bool trans_lb(DisasContext *ctx, arg_lb *a, uint32_t insn)
+{
+ gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_lh(DisasContext *ctx, arg_lh *a, uint32_t insn)
+{
+ gen_load(ctx, OPC_RISC_LH, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_lw(DisasContext *ctx, arg_lw *a, uint32_t insn)
+{
+ gen_load(ctx, OPC_RISC_LW, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_lbu(DisasContext *ctx, arg_lbu *a, uint32_t insn)
+{
+ gen_load(ctx, OPC_RISC_LBU, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_lhu(DisasContext *ctx, arg_lhu *a, uint32_t insn)
+{
+ gen_load(ctx, OPC_RISC_LHU, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_lwu(DisasContext *ctx, arg_lwu *a, uint32_t insn)
+{
+#ifdef TARGET_RISCV64
+ gen_load(ctx, OPC_RISC_LWU, a->rd, a->rs1, a->imm);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_ld(DisasContext *ctx, arg_ld *a, uint32_t insn)
+{
+#ifdef TARGET_RISCV64
+ gen_load(ctx, OPC_RISC_LD, a->rd, a->rs1, a->imm);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_sb(DisasContext *ctx, arg_sb *a, uint32_t insn)
+{
+ gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_sh(DisasContext *ctx, arg_sh *a, uint32_t insn)
+{
+ gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_sw(DisasContext *ctx, arg_sw *a, uint32_t insn)
+{
+ gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_sd(DisasContext *ctx, arg_sd *a, uint32_t insn)
+{
+#ifdef TARGET_RISCV64
+ gen_store(ctx, OPC_RISC_SD, a->rs1, a->rs2, a->imm);
+ return true;
+#else
+ return false;
+#endif
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9b6848e666..6b59dbb373 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1701,13 +1701,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
imm = GET_IMM(ctx->opcode);
switch (op) {
- case OPC_RISC_LOAD:
- gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm);
- break;
- case OPC_RISC_STORE:
- gen_store(ctx, MASK_OP_STORE(ctx->opcode), rs1, rs2,
- GET_STORE_IMM(ctx->opcode));
- break;
case OPC_RISC_ARITH_IMM:
#if defined(TARGET_RISCV64)
case OPC_RISC_ARITH_IMM_W:
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 05/29] target/riscv: Convert RVXI arithmetic insns to decodetree
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (3 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 04/29] target/riscv: Convert RVXI load/store " Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 06/29] target/riscv: Convert RVXI fence " Bastian Koppelmann
` (24 subsequent siblings)
29 siblings, 0 replies; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
we cannot remove the call to gen_arith() in decode_RV32_64G() since it
is used to translate multiply instructions.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v1 -> v2:
- RISCV32 now returns false instead of raising an exception
- shift translators now also use gen_arithm_imm()
target/riscv/insn32.decode | 36 +++++
target/riscv/insn_trans/trans_rvi.inc.c | 181 ++++++++++++++++++++++++
target/riscv/translate.c | 9 --
3 files changed, 217 insertions(+), 9 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index badd1d9216..cb7622e223 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -21,6 +21,9 @@
%rs1 15:5
%rd 7:5
+%sh6 20:6
+%sh5 20:5
+
# immediates:
%imm_i 20:s12
%imm_s 25:s7 7:5
@@ -30,14 +33,19 @@
# Argument sets:
&branch imm rs2 rs1
+&shift shamt rs1 rd
# Formats 32:
+@r ....... ..... ..... ... ..... ....... %rs2 %rs1 %rd
@i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd
@b ....... ..... ..... ... ..... ....... &branch imm=%imm_b %rs2 %rs1
@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1
@u .................... ..... ....... imm=%imm_u %rd
@j .................... ..... ....... imm=%imm_j %rd
+@sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd
+@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
+
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
auipc .................... ..... 0010111 @u
@@ -57,8 +65,36 @@ lhu ............ ..... 101 ..... 0000011 @i
sb ....... ..... ..... 000 ..... 0100011 @s
sh ....... ..... ..... 001 ..... 0100011 @s
sw ....... ..... ..... 010 ..... 0100011 @s
+addi ............ ..... 000 ..... 0010011 @i
+slti ............ ..... 010 ..... 0010011 @i
+sltiu ............ ..... 011 ..... 0010011 @i
+xori ............ ..... 100 ..... 0010011 @i
+ori ............ ..... 110 ..... 0010011 @i
+andi ............ ..... 111 ..... 0010011 @i
+slli 000000 ...... ..... 001 ..... 0010011 @sh6
+srli 000000 ...... ..... 101 ..... 0010011 @sh6
+srai 010000 ...... ..... 101 ..... 0010011 @sh6
+add 0000000 ..... ..... 000 ..... 0110011 @r
+sub 0100000 ..... ..... 000 ..... 0110011 @r
+sll 0000000 ..... ..... 001 ..... 0110011 @r
+slt 0000000 ..... ..... 010 ..... 0110011 @r
+sltu 0000000 ..... ..... 011 ..... 0110011 @r
+xor 0000000 ..... ..... 100 ..... 0110011 @r
+srl 0000000 ..... ..... 101 ..... 0110011 @r
+sra 0100000 ..... ..... 101 ..... 0110011 @r
+or 0000000 ..... ..... 110 ..... 0110011 @r
+and 0000000 ..... ..... 111 ..... 0110011 @r
# *** RV64I Base Instruction Set (in addition to RV32I) ***
lwu ............ ..... 110 ..... 0000011 @i
ld ............ ..... 011 ..... 0000011 @i
sd ....... ..... ..... 011 ..... 0100011 @s
+addiw ............ ..... 000 ..... 0011011 @i
+slliw 0000000 ..... ..... 001 ..... 0011011 @sh5
+srliw 0000000 ..... ..... 101 ..... 0011011 @sh5
+sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5
+addw 0000000 ..... ..... 000 ..... 0111011 @r
+subw 0100000 ..... ..... 000 ..... 0111011 @r
+sllw 0000000 ..... ..... 001 ..... 0111011 @r
+srlw 0000000 ..... ..... 101 ..... 0111011 @r
+sraw 0100000 ..... ..... 101 ..... 0111011 @r
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 2c8ecff76f..e5a67e64cb 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -160,3 +160,184 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a, uint32_t insn)
return false;
#endif
}
+
+static bool trans_addi(DisasContext *ctx, arg_addi *a, uint32_t insn)
+{
+ gen_arith_imm(ctx, OPC_RISC_ADDI, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_slti(DisasContext *ctx, arg_slti *a, uint32_t insn)
+{
+ gen_arith_imm(ctx, OPC_RISC_SLTI, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a, uint32_t insn)
+{
+ gen_arith_imm(ctx, OPC_RISC_SLTIU, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_xori(DisasContext *ctx, arg_xori *a, uint32_t insn)
+{
+ gen_arith_imm(ctx, OPC_RISC_XORI, a->rd, a->rs1, a->imm);
+ return true;
+}
+static bool trans_ori(DisasContext *ctx, arg_ori *a, uint32_t insn)
+{
+ gen_arith_imm(ctx, OPC_RISC_ORI, a->rd, a->rs1, a->imm);
+ return true;
+}
+static bool trans_andi(DisasContext *ctx, arg_andi *a, uint32_t insn)
+{
+ gen_arith_imm(ctx, OPC_RISC_ANDI, a->rd, a->rs1, a->imm);
+ return true;
+}
+static bool trans_slli(DisasContext *ctx, arg_slli *a, uint32_t insn)
+{
+ gen_arith_imm(ctx, OPC_RISC_SLLI, a->rd, a->rs1, a->shamt);
+ return true;
+}
+
+static bool trans_srli(DisasContext *ctx, arg_srli *a, uint32_t insn)
+{
+ gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt);
+ return true;
+}
+
+static bool trans_srai(DisasContext *ctx, arg_srai *a, uint32_t insn)
+{
+ gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt | 0x400);
+ return true;
+}
+
+static bool trans_add(DisasContext *ctx, arg_add *a, uint32_t insn)
+{
+ gen_arith(ctx, OPC_RISC_ADD, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_sub(DisasContext *ctx, arg_sub *a, uint32_t insn)
+{
+ gen_arith(ctx, OPC_RISC_SUB, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_sll(DisasContext *ctx, arg_sll *a, uint32_t insn)
+{
+ gen_arith(ctx, OPC_RISC_SLL, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_slt(DisasContext *ctx, arg_slt *a, uint32_t insn)
+{
+ gen_arith(ctx, OPC_RISC_SLT, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_sltu(DisasContext *ctx, arg_sltu *a, uint32_t insn)
+{
+ gen_arith(ctx, OPC_RISC_SLTU, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_xor(DisasContext *ctx, arg_xor *a, uint32_t insn)
+{
+ gen_arith(ctx, OPC_RISC_XOR, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_srl(DisasContext *ctx, arg_srl *a, uint32_t insn)
+{
+ gen_arith(ctx, OPC_RISC_SRL, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_sra(DisasContext *ctx, arg_sra *a, uint32_t insn)
+{
+ gen_arith(ctx, OPC_RISC_SRA, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_or(DisasContext *ctx, arg_or *a, uint32_t insn)
+{
+ gen_arith(ctx, OPC_RISC_OR, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_and(DisasContext *ctx, arg_and *a, uint32_t insn)
+{
+ gen_arith(ctx, OPC_RISC_AND, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_addiw(DisasContext *ctx, arg_addiw *a, uint32_t insn)
+{
+ gen_arith_imm(ctx, OPC_RISC_ADDIW, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_slliw(DisasContext *ctx, arg_slliw *a, uint32_t insn)
+{
+ gen_arith_imm(ctx, OPC_RISC_SLLIW, a->rd, a->rs1, a->shamt);
+ return true;
+}
+
+static bool trans_srliw(DisasContext *ctx, arg_srliw *a, uint32_t insn)
+{
+ gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW, a->rd, a->rs1, a->shamt);
+ return true;
+}
+
+static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a, uint32_t insn)
+{
+ gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW , a->rd, a->rs1,
+ a->shamt | 0x400);
+ return true;
+}
+
+static bool trans_addw(DisasContext *ctx, arg_addw *a, uint32_t insn)
+{
+#if !defined(TARGET_RISCV64)
+ return false;
+#endif
+ gen_arith(ctx, OPC_RISC_ADDW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_subw(DisasContext *ctx, arg_subw *a, uint32_t insn)
+{
+#if !defined(TARGET_RISCV64)
+ return false;
+#endif
+ gen_arith(ctx, OPC_RISC_SUBW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_sllw(DisasContext *ctx, arg_sllw *a, uint32_t insn)
+{
+#if !defined(TARGET_RISCV64)
+ return false;
+#endif
+ gen_arith(ctx, OPC_RISC_SLLW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_srlw(DisasContext *ctx, arg_srlw *a, uint32_t insn)
+{
+#if !defined(TARGET_RISCV64)
+ return false;
+#endif
+ gen_arith(ctx, OPC_RISC_SRLW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_sraw(DisasContext *ctx, arg_sraw *a, uint32_t insn)
+{
+#if !defined(TARGET_RISCV64)
+ return false;
+#endif
+ gen_arith(ctx, OPC_RISC_SRAW, a->rd, a->rs1, a->rs2);
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 6b59dbb373..3e296a2627 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1701,15 +1701,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
imm = GET_IMM(ctx->opcode);
switch (op) {
- case OPC_RISC_ARITH_IMM:
-#if defined(TARGET_RISCV64)
- case OPC_RISC_ARITH_IMM_W:
-#endif
- if (rd == 0) {
- break; /* NOP */
- }
- gen_arith_imm(ctx, MASK_OP_ARITH_IMM(ctx->opcode), rd, rs1, imm);
- break;
case OPC_RISC_ARITH:
#if defined(TARGET_RISCV64)
case OPC_RISC_ARITH_W:
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 06/29] target/riscv: Convert RVXI fence insns to decodetree
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (4 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 05/29] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-21 14:05 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 07/29] target/riscv: Convert RVXI csr " Bastian Koppelmann
` (23 subsequent siblings)
29 siblings, 1 reply; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v1 -> v2:
- simplified fence/fence_i as suggested by Richard
target/riscv/insn32.decode | 6 ++++++
target/riscv/insn_trans/trans_rvi.inc.c | 20 ++++++++++++++++++++
target/riscv/translate.c | 14 --------------
3 files changed, 26 insertions(+), 14 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index cb7622e223..00e30dbc71 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -24,6 +24,9 @@
%sh6 20:6
%sh5 20:5
+%pred 24:4
+%succ 20:4
+
# immediates:
%imm_i 20:s12
%imm_s 25:s7 7:5
@@ -36,6 +39,7 @@
&shift shamt rs1 rd
# Formats 32:
+
@r ....... ..... ..... ... ..... ....... %rs2 %rs1 %rd
@i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd
@b ....... ..... ..... ... ..... ....... &branch imm=%imm_b %rs2 %rs1
@@ -84,6 +88,8 @@ srl 0000000 ..... ..... 101 ..... 0110011 @r
sra 0100000 ..... ..... 101 ..... 0110011 @r
or 0000000 ..... ..... 110 ..... 0110011 @r
and 0000000 ..... ..... 111 ..... 0110011 @r
+fence ---- pred:4 succ:4 ----- 000 ----- 0001111
+fence_i ---- ---- ---- ----- 001 ----- 0001111
# *** RV64I Base Instruction Set (in addition to RV32I) ***
lwu ............ ..... 110 ..... 0000011 @i
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index e5a67e64cb..14164a952d 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -341,3 +341,23 @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a, uint32_t insn)
gen_arith(ctx, OPC_RISC_SRAW, a->rd, a->rs1, a->rs2);
return true;
}
+
+static bool trans_fence(DisasContext *ctx, arg_fence *a, uint32_t insn)
+{
+#ifndef CONFIG_USER_ONLY
+ /* FENCE is a full memory barrier. */
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
+#endif
+ return true;
+}
+static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a, uint32_t insn)
+{
+#ifndef CONFIG_USER_ONLY
+ /* FENCE_I is a no-op in QEMU,
+ * however we need to end the translation block */
+ tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+ tcg_gen_exit_tb(NULL, 0);
+ ctx->base.is_jmp = DISAS_NORETURN;
+#endif
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3e296a2627..f2567117b9 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1740,20 +1740,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
gen_fp_arith(ctx, MASK_OP_FP_ARITH(ctx->opcode), rd, rs1, rs2,
GET_RM(ctx->opcode));
break;
- case OPC_RISC_FENCE:
-#ifndef CONFIG_USER_ONLY
- if (ctx->opcode & 0x1000) {
- /* FENCE_I is a no-op in QEMU,
- * however we need to end the translation block */
- tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- tcg_gen_exit_tb(NULL, 0);
- ctx->base.is_jmp = DISAS_NORETURN;
- } else {
- /* FENCE is a full memory barrier. */
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
- }
-#endif
- break;
case OPC_RISC_SYSTEM:
gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
(ctx->opcode & 0xFFF00000) >> 20);
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 07/29] target/riscv: Convert RVXI csr insns to decodetree
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (5 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 06/29] target/riscv: Convert RVXI fence " Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 08/29] target/riscv: Convert RVXM " Bastian Koppelmann
` (22 subsequent siblings)
29 siblings, 0 replies; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32.decode | 9 +++
target/riscv/insn_trans/trans_rvi.inc.c | 79 +++++++++++++++++++++++++
target/riscv/translate.c | 43 +-------------
3 files changed, 89 insertions(+), 42 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 00e30dbc71..4f6341aa37 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -23,6 +23,7 @@
%sh6 20:6
%sh5 20:5
+%csr 20:12
%pred 24:4
%succ 20:4
@@ -49,6 +50,7 @@
@sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd
@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
+@csr ............ ..... ... ..... ....... %csr %rs1 %rd
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
@@ -90,6 +92,13 @@ or 0000000 ..... ..... 110 ..... 0110011 @r
and 0000000 ..... ..... 111 ..... 0110011 @r
fence ---- pred:4 succ:4 ----- 000 ----- 0001111
fence_i ---- ---- ---- ----- 001 ----- 0001111
+csrrw ............ ..... 001 ..... 1110011 @csr
+csrrs ............ ..... 010 ..... 1110011 @csr
+csrrc ............ ..... 011 ..... 1110011 @csr
+csrrwi ............ ..... 101 ..... 1110011 @csr
+csrrsi ............ ..... 110 ..... 1110011 @csr
+csrrci ............ ..... 111 ..... 1110011 @csr
+
# *** RV64I Base Instruction Set (in addition to RV32I) ***
lwu ............ ..... 110 ..... 0000011 @i
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 14164a952d..5d0b4627ae 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -361,3 +361,82 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a, uint32_t insn)
#endif
return true;
}
+
+#define RISCV_OP_CSR_PRE do {\
+ source1 = tcg_temp_new(); \
+ csr_store = tcg_temp_new(); \
+ dest = tcg_temp_new(); \
+ rs1_pass = tcg_temp_new(); \
+ gen_get_gpr(source1, a->rs1); \
+ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); \
+ tcg_gen_movi_tl(rs1_pass, a->rs1); \
+ tcg_gen_movi_tl(csr_store, a->csr); \
+ gen_io_start();\
+} while (0)
+
+#define RISCV_OP_CSR_POST do {\
+ gen_io_end(); \
+ gen_set_gpr(a->rd, dest); \
+ tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \
+ tcg_gen_exit_tb(NULL, 0); \
+ ctx->base.is_jmp = DISAS_NORETURN; \
+ tcg_temp_free(source1); \
+ tcg_temp_free(csr_store); \
+ tcg_temp_free(dest); \
+ tcg_temp_free(rs1_pass); \
+} while (0)
+
+
+static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a, uint32_t insn)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrw(dest, cpu_env, source1, csr_store);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a, uint32_t insn)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a, uint32_t insn)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a, uint32_t insn)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrw(dest, cpu_env, rs1_pass, csr_store);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a, uint32_t insn)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrs(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a, uint32_t insn)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrc(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
+ RISCV_OP_CSR_POST;
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f2567117b9..d811090764 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1277,16 +1277,11 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
int rd, int rs1, int csr)
{
- TCGv source1, csr_store, dest, rs1_pass, imm_rs1;
+ TCGv source1, dest;
source1 = tcg_temp_new();
- csr_store = tcg_temp_new();
dest = tcg_temp_new();
- rs1_pass = tcg_temp_new();
- imm_rs1 = tcg_temp_new();
gen_get_gpr(source1, rs1);
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
- tcg_gen_movi_tl(rs1_pass, rs1);
- tcg_gen_movi_tl(csr_store, csr); /* copy into temp reg to feed to helper */
#ifndef CONFIG_USER_ONLY
/* Extract funct7 value and check whether it matches SFENCE.VMA */
@@ -1349,45 +1344,9 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
break;
}
break;
- default:
- tcg_gen_movi_tl(imm_rs1, rs1);
- gen_io_start();
- switch (opc) {
- case OPC_RISC_CSRRW:
- gen_helper_csrrw(dest, cpu_env, source1, csr_store);
- break;
- case OPC_RISC_CSRRS:
- gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass);
- break;
- case OPC_RISC_CSRRC:
- gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass);
- break;
- case OPC_RISC_CSRRWI:
- gen_helper_csrrw(dest, cpu_env, imm_rs1, csr_store);
- break;
- case OPC_RISC_CSRRSI:
- gen_helper_csrrs(dest, cpu_env, imm_rs1, csr_store, rs1_pass);
- break;
- case OPC_RISC_CSRRCI:
- gen_helper_csrrc(dest, cpu_env, imm_rs1, csr_store, rs1_pass);
- break;
- default:
- gen_exception_illegal(ctx);
- return;
- }
- gen_io_end();
- gen_set_gpr(rd, dest);
- /* end tb since we may be changing priv modes, to get mmu_index right */
- tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
}
tcg_temp_free(source1);
- tcg_temp_free(csr_store);
tcg_temp_free(dest);
- tcg_temp_free(rs1_pass);
- tcg_temp_free(imm_rs1);
}
static void decode_RV32_64C0(DisasContext *ctx)
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 08/29] target/riscv: Convert RVXM insns to decodetree
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (6 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 07/29] target/riscv: Convert RVXI csr " Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 09/29] target/riscv: Convert RV32A " Bastian Koppelmann
` (21 subsequent siblings)
29 siblings, 0 replies; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v1 -> v2:
- fixed spacing
target/riscv/insn32.decode | 17 +++++
target/riscv/insn_trans/trans_rvm.inc.c | 98 +++++++++++++++++++++++++
target/riscv/translate.c | 10 +--
3 files changed, 116 insertions(+), 9 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 4f6341aa37..a484844f34 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -113,3 +113,20 @@ subw 0100000 ..... ..... 000 ..... 0111011 @r
sllw 0000000 ..... ..... 001 ..... 0111011 @r
srlw 0000000 ..... ..... 101 ..... 0111011 @r
sraw 0100000 ..... ..... 101 ..... 0111011 @r
+
+# *** RV32M Standard Extension ***
+mul 0000001 ..... ..... 000 ..... 0110011 @r
+mulh 0000001 ..... ..... 001 ..... 0110011 @r
+mulhsu 0000001 ..... ..... 010 ..... 0110011 @r
+mulhu 0000001 ..... ..... 011 ..... 0110011 @r
+div 0000001 ..... ..... 100 ..... 0110011 @r
+divu 0000001 ..... ..... 101 ..... 0110011 @r
+rem 0000001 ..... ..... 110 ..... 0110011 @r
+remu 0000001 ..... ..... 111 ..... 0110011 @r
+
+# *** RV64M Standard Extension (in addition to RV32M) ***
+mulw 0000001 ..... ..... 000 ..... 0111011 @r
+divw 0000001 ..... ..... 100 ..... 0111011 @r
+divuw 0000001 ..... ..... 101 ..... 0111011 @r
+remw 0000001 ..... ..... 110 ..... 0111011 @r
+remuw 0000001 ..... ..... 111 ..... 0111011 @r
diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_trans/trans_rvm.inc.c
new file mode 100644
index 0000000000..ffeae57a36
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvm.inc.c
@@ -0,0 +1,98 @@
+/*
+ * RISC-V translation routines for the RV64M Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+static bool trans_mul(DisasContext *ctx, arg_mul *a, uint32_t insn)
+{
+ gen_arith(ctx, OPC_RISC_MUL, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_mulh(DisasContext *ctx, arg_mulh *a, uint32_t insn)
+{
+ gen_arith(ctx, OPC_RISC_MULH, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a, uint32_t insn)
+{
+ gen_arith(ctx, OPC_RISC_MULHSU, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a, uint32_t insn)
+{
+ gen_arith(ctx, OPC_RISC_MULHU, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_div(DisasContext *ctx, arg_div *a, uint32_t insn)
+{
+ gen_arith(ctx, OPC_RISC_DIV, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_divu(DisasContext *ctx, arg_divu *a, uint32_t insn)
+{
+ gen_arith(ctx, OPC_RISC_DIVU, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_rem(DisasContext *ctx, arg_rem *a, uint32_t insn)
+{
+ gen_arith(ctx, OPC_RISC_REM, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_remu(DisasContext *ctx, arg_remu *a, uint32_t insn)
+{
+ gen_arith(ctx, OPC_RISC_REMU, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_mulw(DisasContext *ctx, arg_mulw *a, uint32_t insn)
+{
+ gen_arith(ctx, OPC_RISC_MULW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_divw(DisasContext *ctx, arg_divw *a, uint32_t insn)
+{
+ gen_arith(ctx, OPC_RISC_DIVW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_divuw(DisasContext *ctx, arg_divuw *a, uint32_t insn)
+{
+ gen_arith(ctx, OPC_RISC_DIVUW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_remw(DisasContext *ctx, arg_remw *a, uint32_t insn)
+{
+ gen_arith(ctx, OPC_RISC_REMW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_remuw(DisasContext *ctx, arg_remuw *a, uint32_t insn)
+{
+ gen_arith(ctx, OPC_RISC_REMUW, a->rd, a->rs1, a->rs2);
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d811090764..17c4d79b18 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1639,6 +1639,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
#include "decode_insn32.inc.c"
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
+#include "insn_trans/trans_rvm.inc.c"
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
@@ -1660,15 +1661,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
imm = GET_IMM(ctx->opcode);
switch (op) {
- case OPC_RISC_ARITH:
-#if defined(TARGET_RISCV64)
- case OPC_RISC_ARITH_W:
-#endif
- if (rd == 0) {
- break; /* NOP */
- }
- gen_arith(ctx, MASK_OP_ARITH(ctx->opcode), rd, rs1, rs2);
- break;
case OPC_RISC_FP_LOAD:
gen_fp_load(ctx, MASK_OP_FP_LOAD(ctx->opcode), rd, rs1, imm);
break;
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 09/29] target/riscv: Convert RV32A insns to decodetree
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (7 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 08/29] target/riscv: Convert RVXM " Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-23 8:19 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 10/29] target/riscv: Convert RV64A " Bastian Koppelmann
` (20 subsequent siblings)
29 siblings, 1 reply; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v1 -> v2:
- simplified gen_amo() with function pointers
- rs2 @atom_ld is now decimal
target/riscv/insn32.decode | 17 +++
target/riscv/insn_trans/trans_rva.inc.c | 145 ++++++++++++++++++++++++
target/riscv/translate.c | 1 +
3 files changed, 163 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_rva.inc.c
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index a484844f34..687eadcaa5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -38,6 +38,7 @@
# Argument sets:
&branch imm rs2 rs1
&shift shamt rs1 rd
+&atomic aq rl rs2 rs1 rd
# Formats 32:
@@ -52,6 +53,9 @@
@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
@csr ............ ..... ... ..... ....... %csr %rs1 %rd
+@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
+@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
+
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
auipc .................... ..... 0010111 @u
@@ -130,3 +134,16 @@ divw 0000001 ..... ..... 100 ..... 0111011 @r
divuw 0000001 ..... ..... 101 ..... 0111011 @r
remw 0000001 ..... ..... 110 ..... 0111011 @r
remuw 0000001 ..... ..... 111 ..... 0111011 @r
+
+# *** RV32A Standard Extension ***
+lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
+sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st
+amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st
+amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st
+amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st
+amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st
+amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st
+amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st
+amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
+amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
+amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_trans/trans_rva.inc.c
new file mode 100644
index 0000000000..dd0fb02b23
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rva.inc.c
@@ -0,0 +1,145 @@
+/*
+ * RISC-V translation routines for the RV64A Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)
+{
+ TCGv src1 = tcg_temp_new();
+ /* Put addr in load_res, data in load_val. */
+ gen_get_gpr(src1, a->rs1);
+ if (a->rl) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+ }
+ tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
+ if (a->aq) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+ }
+ tcg_gen_mov_tl(load_res, src1);
+ gen_set_gpr(a->rd, load_val);
+
+ tcg_temp_free(src1);
+ return true;
+}
+
+static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)
+{
+ TCGv src1 = tcg_temp_new();
+ TCGv src2 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
+
+ gen_get_gpr(src1, a->rs1);
+ tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
+
+ gen_get_gpr(src2, a->rs2);
+ /* Note that the TCG atomic primitives are SC,
+ so we can ignore AQ/RL along this path. */
+ tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
+ ctx->mem_idx, mop);
+ tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
+ gen_set_gpr(a->rd, dat);
+ tcg_gen_br(l2);
+
+ gen_set_label(l1);
+ /* Address comparion failure. However, we still need to
+ provide the memory barrier implied by AQ/RL. */
+ tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
+ tcg_gen_movi_tl(dat, 1);
+ gen_set_gpr(a->rd, dat);
+
+ gen_set_label(l2);
+ tcg_temp_free(dat);
+ tcg_temp_free(src1);
+ tcg_temp_free(src2);
+ return true;
+}
+
+static bool gen_amo(DisasContext *ctx, arg_atomic *a,
+ void(*func)(TCGv, TCGv, TCGv, TCGArg, TCGMemOp),
+ TCGMemOp mop)
+{
+ TCGv src1 = tcg_temp_new();
+ TCGv src2 = tcg_temp_new();
+
+ gen_get_gpr(src1, a->rs1);
+ gen_get_gpr(src2, a->rs2);
+
+ (*func)(src2, src1, src2, ctx->mem_idx, mop);
+
+ gen_set_gpr(a->rd, src2);
+ tcg_temp_free(src1);
+ tcg_temp_free(src2);
+ return true;
+}
+
+static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a, uint32_t insn)
+{
+ return gen_lr(ctx, a, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a, uint32_t insn)
+{
+ return gen_sc(ctx, a, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a, uint32_t insn)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a, uint32_t insn)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a, uint32_t insn)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a, uint32_t insn)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a, uint32_t insn)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a, uint32_t insn)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a, uint32_t insn)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a, uint32_t insn)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a, uint32_t insn)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 17c4d79b18..d6e8d9700f 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1640,6 +1640,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
+#include "insn_trans/trans_rva.inc.c"
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 10/29] target/riscv: Convert RV64A insns to decodetree
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (8 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 09/29] target/riscv: Convert RV32A " Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 11/29] target/riscv: Convert RV32F " Bastian Koppelmann
` (19 subsequent siblings)
29 siblings, 0 replies; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v1 -> v2:
- use simplfied gen_amo() with function pointers
target/riscv/insn32.decode | 13 +++
target/riscv/insn_trans/trans_rva.inc.c | 99 +++++++++++++++++
target/riscv/translate.c | 140 ------------------------
3 files changed, 112 insertions(+), 140 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 687eadcaa5..0b75987855 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -147,3 +147,16 @@ amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st
amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
+
+# *** RV64A Standard Extension (in addition to RV32A) ***
+lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
+sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st
+amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st
+amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st
+amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st
+amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st
+amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
+amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_trans/trans_rva.inc.c
index dd0fb02b23..7e368dc321 100644
--- a/target/riscv/insn_trans/trans_rva.inc.c
+++ b/target/riscv/insn_trans/trans_rva.inc.c
@@ -143,3 +143,102 @@ static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a, uint32_t insn)
{
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
}
+
+static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a, uint32_t insn)
+{
+#ifdef TARGET_RISCV64
+ return gen_lr(ctx, a, MO_ALIGN | MO_TEQ);
+#else
+ return false;
+#endif
+}
+
+static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a, uint32_t insn)
+{
+#ifdef TARGET_RISCV64
+ return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ));
+#else
+ return false;
+#endif
+}
+
+static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a, uint32_t insn)
+{
+#ifdef TARGET_RISCV64
+ return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ));
+#else
+ return false;
+#endif
+}
+
+static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a, uint32_t insn)
+{
+#ifdef TARGET_RISCV64
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEQ));
+#else
+ return false;
+#endif
+}
+
+static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a, uint32_t insn)
+{
+#ifdef TARGET_RISCV64
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEQ));
+#else
+ return false;
+#endif
+}
+
+static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a, uint32_t insn)
+{
+#ifdef TARGET_RISCV64
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEQ));
+#else
+ return false;
+#endif
+}
+
+static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a, uint32_t insn)
+{
+#ifdef TARGET_RISCV64
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ));
+#else
+ return false;
+#endif
+}
+
+static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a, uint32_t insn)
+{
+#ifdef TARGET_RISCV64
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEQ));
+#else
+ return false;
+#endif
+}
+
+static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a, uint32_t insn)
+{
+#ifdef TARGET_RISCV64
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEQ));
+#else
+ return false;
+#endif
+}
+
+static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a, uint32_t insn)
+{
+#ifdef TARGET_RISCV64
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEQ));
+#else
+ return false;
+#endif
+}
+
+static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a, uint32_t insn)
+{
+#ifdef TARGET_RISCV64
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEQ));
+#else
+ return false;
+#endif
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d6e8d9700f..6a3d49b9b9 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -711,143 +711,6 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
tcg_temp_free(t0);
}
-static void gen_atomic(DisasContext *ctx, uint32_t opc,
- int rd, int rs1, int rs2)
-{
- TCGv src1, src2, dat;
- TCGLabel *l1, *l2;
- TCGMemOp mop;
- bool aq, rl;
-
- /* Extract the size of the atomic operation. */
- switch (extract32(opc, 12, 3)) {
- case 2: /* 32-bit */
- mop = MO_ALIGN | MO_TESL;
- break;
-#if defined(TARGET_RISCV64)
- case 3: /* 64-bit */
- mop = MO_ALIGN | MO_TEQ;
- break;
-#endif
- default:
- gen_exception_illegal(ctx);
- return;
- }
- rl = extract32(opc, 25, 1);
- aq = extract32(opc, 26, 1);
-
- src1 = tcg_temp_new();
- src2 = tcg_temp_new();
-
- switch (MASK_OP_ATOMIC_NO_AQ_RL_SZ(opc)) {
- case OPC_RISC_LR:
- /* Put addr in load_res, data in load_val. */
- gen_get_gpr(src1, rs1);
- if (rl) {
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
- }
- tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
- if (aq) {
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
- }
- tcg_gen_mov_tl(load_res, src1);
- gen_set_gpr(rd, load_val);
- break;
-
- case OPC_RISC_SC:
- l1 = gen_new_label();
- l2 = gen_new_label();
- dat = tcg_temp_new();
-
- gen_get_gpr(src1, rs1);
- tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
-
- gen_get_gpr(src2, rs2);
- /* Note that the TCG atomic primitives are SC,
- so we can ignore AQ/RL along this path. */
- tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
- ctx->mem_idx, mop);
- tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
- gen_set_gpr(rd, dat);
- tcg_gen_br(l2);
-
- gen_set_label(l1);
- /* Address comparion failure. However, we still need to
- provide the memory barrier implied by AQ/RL. */
- tcg_gen_mb(TCG_MO_ALL + aq * TCG_BAR_LDAQ + rl * TCG_BAR_STRL);
- tcg_gen_movi_tl(dat, 1);
- gen_set_gpr(rd, dat);
-
- gen_set_label(l2);
- tcg_temp_free(dat);
- break;
-
- case OPC_RISC_AMOSWAP:
- /* Note that the TCG atomic primitives are SC,
- so we can ignore AQ/RL along this path. */
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_xchg_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOADD:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_add_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOXOR:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_xor_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOAND:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_and_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOOR:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_or_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOMIN:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_smin_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOMAX:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_smax_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOMINU:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_umin_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOMAXU:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_umax_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
-
- default:
- gen_exception_illegal(ctx);
- break;
- }
-
- tcg_temp_free(src1);
- tcg_temp_free(src2);
-}
-
static void gen_set_rm(DisasContext *ctx, int rm)
{
TCGv_i32 t0;
@@ -1669,9 +1532,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
gen_fp_store(ctx, MASK_OP_FP_STORE(ctx->opcode), rs1, rs2,
GET_STORE_IMM(ctx->opcode));
break;
- case OPC_RISC_ATOMIC:
- gen_atomic(ctx, MASK_OP_ATOMIC(ctx->opcode), rd, rs1, rs2);
- break;
case OPC_RISC_FMADD:
gen_fp_fmadd(ctx, MASK_OP_FP_FMADD(ctx->opcode), rd, rs1, rs2,
GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 11/29] target/riscv: Convert RV32F insns to decodetree
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (9 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 10/29] target/riscv: Convert RV64A " Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 12/29] target/riscv: Convert RV64F " Bastian Koppelmann
` (18 subsequent siblings)
29 siblings, 0 replies; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v1 -> v2:
- REQUIRE_FPU uses do {} while (0)
- Add REQUIRE_FPU to arithm helpers
target/riscv/insn32.decode | 35 +++
target/riscv/insn_trans/trans_rvf.inc.c | 334 ++++++++++++++++++++++++
target/riscv/translate.c | 1 +
3 files changed, 370 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0b75987855..f27bdab245 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -17,6 +17,7 @@
# this program. If not, see <http://www.gnu.org/licenses/>.
# Fields:
+%rs3 27:5
%rs2 20:5
%rs1 15:5
%rd 7:5
@@ -24,6 +25,7 @@
%sh6 20:6
%sh5 20:5
%csr 20:12
+%rm 12:3
%pred 24:4
%succ 20:4
@@ -56,6 +58,11 @@
@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
+@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
+@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
+@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
+@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
+
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
auipc .................... ..... 0010111 @u
@@ -160,3 +167,31 @@ amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
+
+# *** RV32F Standard Extension ***
+flw ............ ..... 010 ..... 0000111 @i
+fsw ....... ..... ..... 010 ..... 0100111 @s
+fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm
+fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm
+fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm
+fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm
+fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm
+fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm
+fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm
+fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm
+fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm
+fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r
+fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r
+fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r
+fmin_s 0010100 ..... ..... 000 ..... 1010011 @r
+fmax_s 0010100 ..... ..... 001 ..... 1010011 @r
+fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm
+fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm
+fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2
+feq_s 1010000 ..... ..... 010 ..... 1010011 @r
+flt_s 1010000 ..... ..... 001 ..... 1010011 @r
+fle_s 1010000 ..... ..... 000 ..... 1010011 @r
+fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
+fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
+fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
+fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c
new file mode 100644
index 0000000000..3f806b8238
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -0,0 +1,334 @@
+/*
+ * RISC-V translation routines for the RV64F Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_FPU do {\
+ if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) \
+ return false; \
+} while (0)
+
+static bool trans_flw(DisasContext *ctx, arg_flw *a, uint32_t insn)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ REQUIRE_FPU;
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
+ /* RISC-V requires NaN-boxing of narrower width floating point values */
+ tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], 0xffffffff00000000ULL);
+
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fsw(DisasContext *ctx, arg_fsw *a, uint32_t insn)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ REQUIRE_FPU;
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
+
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fnmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fnmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fadd_s(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ return true;
+}
+
+static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsub_s(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ return true;
+}
+
+static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmul_s(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ return true;
+}
+
+static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fdiv_s(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ return true;
+}
+
+static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsqrt_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+ return true;
+}
+
+static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+ if (a->rs1 == a->rs2) { /* FMOV */
+ tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
+ } else { /* FSGNJ */
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1],
+ 0, 31);
+ }
+ return true;
+}
+
+static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+ if (a->rs1 == a->rs2) { /* FNEG */
+ tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT32_MIN);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ tcg_gen_not_i64(t0, cpu_fpr[a->rs2]);
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31);
+ tcg_temp_free_i64(t0);
+ }
+ return true;
+}
+
+static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+ if (a->rs1 == a->rs2) { /* FABS */
+ tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT32_MIN);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT32_MIN);
+ tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);
+ tcg_temp_free_i64(t0);
+ }
+ return true;
+}
+
+static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ gen_helper_fmin_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2]);
+ return true;
+}
+
+static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ gen_helper_fmax_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2]);
+ return true;
+}
+
+static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a, uint32_t insn)
+{
+ /* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+
+#if defined(TARGET_RISCV64)
+ tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]);
+#else
+ tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]);
+#endif
+
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+ TCGv t0 = tcg_temp_new();
+ gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+ TCGv t0 = tcg_temp_new();
+ gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+ TCGv t0 = tcg_temp_new();
+ gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+
+ gen_helper_fclass_s(t0, cpu_fpr[a->rs1]);
+
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0);
+
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0);
+
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a, uint32_t insn)
+{
+ /* NOTE: This was FMV.S.X in an earlier version of the ISA spec! */
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+#if defined(TARGET_RISCV64)
+ tcg_gen_mov_i64(cpu_fpr[a->rd], t0);
+#else
+ tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0);
+#endif
+
+ tcg_temp_free(t0);
+
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 6a3d49b9b9..a6ef398384 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1504,6 +1504,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
#include "insn_trans/trans_rva.inc.c"
+#include "insn_trans/trans_rvf.inc.c"
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 12/29] target/riscv: Convert RV64F insns to decodetree
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (10 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 11/29] target/riscv: Convert RV32F " Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 13/29] target/riscv: Convert RV32D " Bastian Koppelmann
` (17 subsequent siblings)
29 siblings, 0 replies; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v1 -> v2:
- RISCV32 now returns false instead of raising an exception
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvf.inc.c | 68 +++++++++++++++++++++++++
2 files changed, 74 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index f27bdab245..5d3d2a25ac 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -195,3 +195,9 @@ fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
+
+# *** RV64F Standard Extension (in addition to RV32F) ***
+fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
+fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c
index 3f806b8238..bd79ef96f8 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -332,3 +332,71 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a, uint32_t insn)
return true;
}
+
+static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
+
+ tcg_temp_free(t0);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
+
+ tcg_temp_free(t0);
+ return true;
+#else
+ return false;
+#endif
+}
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 13/29] target/riscv: Convert RV32D insns to decodetree
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (11 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 12/29] target/riscv: Convert RV64F " Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-23 8:21 ` Richard Henderson
2018-10-31 10:44 ` Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 14/29] target/riscv: Convert RV64D " Bastian Koppelmann
` (16 subsequent siblings)
29 siblings, 2 replies; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v1 -> v2:
- Add REQUIRE_FPU to arithm helpers
target/riscv/insn32.decode | 28 +++
target/riscv/insn_trans/trans_rvd.inc.c | 319 ++++++++++++++++++++++++
target/riscv/translate.c | 1 +
3 files changed, 348 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 5d3d2a25ac..fc55181e6f 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -201,3 +201,31 @@ fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
+
+# *** RV32D Standard Extension ***
+fld ............ ..... 011 ..... 0000111 @i
+fsd ....... ..... ..... 011 ..... 0100111 @s
+fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm
+fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm
+fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm
+fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm
+fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm
+fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm
+fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm
+fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm
+fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm
+fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r
+fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r
+fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r
+fmin_d 0010101 ..... ..... 000 ..... 1010011 @r
+fmax_d 0010101 ..... ..... 001 ..... 1010011 @r
+fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm
+fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm
+feq_d 1010001 ..... ..... 010 ..... 1010011 @r
+flt_d 1010001 ..... ..... 001 ..... 1010011 @r
+fle_d 1010001 ..... ..... 000 ..... 1010011 @r
+fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2
+fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm
+fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm
+fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
+fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c
new file mode 100644
index 0000000000..4eccdf72dc
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvd.inc.c
@@ -0,0 +1,319 @@
+/*
+ * RISC-V translation routines for the RV64D Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_fld(DisasContext *ctx, arg_fld *a, uint32_t insn)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ REQUIRE_FPU;
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
+
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fsd(DisasContext *ctx, arg_fsd *a, uint32_t insn)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ REQUIRE_FPU;
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
+
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fnmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fnmadd_d(DisasContext *ctx, arg_fnmadd_d *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fnmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fadd_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ return true;
+}
+
+static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsub_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ return true;
+}
+
+static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmul_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ return true;
+}
+
+static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fdiv_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ return true;
+}
+
+static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_d *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsqrt_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+
+ return true;
+}
+
+static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgnj_d *a, uint32_t insn)
+{
+ if (a->rs1 == a->rs2) { /* FMOV */
+ tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
+ } else {
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2],
+ cpu_fpr[a->rs1], 0, 63);
+ }
+ return true;
+}
+
+static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsgnjn_d *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+ if (a->rs1 == a->rs2) { /* FNEG */
+ tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT64_MIN);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ tcg_gen_not_i64(t0, cpu_fpr[a->rs2]);
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 63);
+ tcg_temp_free_i64(t0);
+ }
+ return true;
+}
+
+static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsgnjx_d *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+ if (a->rs1 == a->rs2) { /* FABS */
+ tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT64_MIN);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT64_MIN);
+ tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);
+ tcg_temp_free_i64(t0);
+ }
+ return true;
+}
+
+static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ gen_helper_fmin_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ return true;
+}
+
+static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ gen_helper_fmax_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ return true;
+}
+
+static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+
+ return true;
+}
+
+static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+
+ return true;
+}
+
+static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_helper_feq_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_helper_flt_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_helper_fle_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_helper_fclass_d(t0, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+#else
+ gen_exception_illegal(ctx);
+#endif
+ return true;
+}
+
+static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a, uint32_t insn)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a6ef398384..1c3fd3e7f3 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1505,6 +1505,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
#include "insn_trans/trans_rvm.inc.c"
#include "insn_trans/trans_rva.inc.c"
#include "insn_trans/trans_rvf.inc.c"
+#include "insn_trans/trans_rvd.inc.c"
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 14/29] target/riscv: Convert RV64D insns to decodetree
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (12 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 13/29] target/riscv: Convert RV32D " Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 15/29] target/riscv: Convert RV priv " Bastian Koppelmann
` (15 subsequent siblings)
29 siblings, 0 replies; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32.decode | 8 +
target/riscv/insn_trans/trans_rvd.inc.c | 94 +++++
target/riscv/translate.c | 484 +-----------------------
3 files changed, 103 insertions(+), 483 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index fc55181e6f..c347102378 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -229,3 +229,11 @@ fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm
fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm
fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
+
+# *** RV64D Standard Extension (in addition to RV32D) ***
+fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm
+fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
+fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
+fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c
index 4eccdf72dc..665cf54e25 100644
--- a/target/riscv/insn_trans/trans_rvd.inc.c
+++ b/target/riscv/insn_trans/trans_rvd.inc.c
@@ -317,3 +317,97 @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a, uint32_t insn)
return true;
}
+
+static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+#else
+ gen_exception_illegal(ctx);
+#endif
+ return true;
+}
+
+static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+#else
+ gen_exception_illegal(ctx);
+#endif
+ return true;
+}
+
+static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+ REQUIRE_FPU;
+
+ gen_set_gpr(a->rd, cpu_fpr[a->rs1]);
+#else
+ gen_exception_illegal(ctx);
+#endif
+ return true;
+}
+
+static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0);
+ tcg_temp_free(t0);
+#else
+ gen_exception_illegal(ctx);
+#endif
+ return true;
+}
+
+static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0);
+ tcg_temp_free(t0);
+#else
+ gen_exception_illegal(ctx);
+#endif
+ return true;
+}
+
+static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ tcg_gen_mov_tl(cpu_fpr[a->rd], t0);
+ tcg_temp_free(t0);
+#else
+ gen_exception_illegal(ctx);
+#endif
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1c3fd3e7f3..89d1278974 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -180,44 +180,6 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free(rh);
}
-static void gen_fsgnj(DisasContext *ctx, uint32_t rd, uint32_t rs1,
- uint32_t rs2, int rm, uint64_t min)
-{
- switch (rm) {
- case 0: /* fsgnj */
- if (rs1 == rs2) { /* FMOV */
- tcg_gen_mov_i64(cpu_fpr[rd], cpu_fpr[rs1]);
- } else {
- tcg_gen_deposit_i64(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1],
- 0, min == INT32_MIN ? 31 : 63);
- }
- break;
- case 1: /* fsgnjn */
- if (rs1 == rs2) { /* FNEG */
- tcg_gen_xori_i64(cpu_fpr[rd], cpu_fpr[rs1], min);
- } else {
- TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_not_i64(t0, cpu_fpr[rs2]);
- tcg_gen_deposit_i64(cpu_fpr[rd], t0, cpu_fpr[rs1],
- 0, min == INT32_MIN ? 31 : 63);
- tcg_temp_free_i64(t0);
- }
- break;
- case 2: /* fsgnjx */
- if (rs1 == rs2) { /* FABS */
- tcg_gen_andi_i64(cpu_fpr[rd], cpu_fpr[rs1], ~min);
- } else {
- TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_andi_i64(t0, cpu_fpr[rs2], min);
- tcg_gen_xor_i64(cpu_fpr[rd], cpu_fpr[rs1], t0);
- tcg_temp_free_i64(t0);
- }
- break;
- default:
- gen_exception_illegal(ctx);
- }
-}
-
static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
int rs2)
{
@@ -724,418 +686,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
tcg_temp_free_i32(t0);
}
-static void gen_fp_fmadd(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rs3, int rm)
-{
- switch (opc) {
- case OPC_RISC_FMADD_S:
- gen_set_rm(ctx, rm);
- gen_helper_fmadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- case OPC_RISC_FMADD_D:
- gen_set_rm(ctx, rm);
- gen_helper_fmadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
-static void gen_fp_fmsub(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rs3, int rm)
-{
- switch (opc) {
- case OPC_RISC_FMSUB_S:
- gen_set_rm(ctx, rm);
- gen_helper_fmsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- case OPC_RISC_FMSUB_D:
- gen_set_rm(ctx, rm);
- gen_helper_fmsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
-static void gen_fp_fnmsub(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rs3, int rm)
-{
- switch (opc) {
- case OPC_RISC_FNMSUB_S:
- gen_set_rm(ctx, rm);
- gen_helper_fnmsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- case OPC_RISC_FNMSUB_D:
- gen_set_rm(ctx, rm);
- gen_helper_fnmsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
-static void gen_fp_fnmadd(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rs3, int rm)
-{
- switch (opc) {
- case OPC_RISC_FNMADD_S:
- gen_set_rm(ctx, rm);
- gen_helper_fnmadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- case OPC_RISC_FNMADD_D:
- gen_set_rm(ctx, rm);
- gen_helper_fnmadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
-static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rm)
-{
- TCGv t0 = NULL;
-
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
- goto do_illegal;
- }
-
- switch (opc) {
- case OPC_RISC_FADD_S:
- gen_set_rm(ctx, rm);
- gen_helper_fadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FSUB_S:
- gen_set_rm(ctx, rm);
- gen_helper_fsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FMUL_S:
- gen_set_rm(ctx, rm);
- gen_helper_fmul_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FDIV_S:
- gen_set_rm(ctx, rm);
- gen_helper_fdiv_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FSQRT_S:
- gen_set_rm(ctx, rm);
- gen_helper_fsqrt_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
- break;
- case OPC_RISC_FSGNJ_S:
- gen_fsgnj(ctx, rd, rs1, rs2, rm, INT32_MIN);
- break;
-
- case OPC_RISC_FMIN_S:
- /* also handles: OPC_RISC_FMAX_S */
- switch (rm) {
- case 0x0:
- gen_helper_fmin_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 0x1:
- gen_helper_fmax_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- default:
- goto do_illegal;
- }
- break;
-
- case OPC_RISC_FEQ_S:
- /* also handles: OPC_RISC_FLT_S, OPC_RISC_FLE_S */
- t0 = tcg_temp_new();
- switch (rm) {
- case 0x0:
- gen_helper_fle_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 0x1:
- gen_helper_flt_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 0x2:
- gen_helper_feq_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FCVT_W_S:
- /* also OPC_RISC_FCVT_WU_S, OPC_RISC_FCVT_L_S, OPC_RISC_FCVT_LU_S */
- t0 = tcg_temp_new();
- switch (rs2) {
- case 0: /* FCVT_W_S */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[rs1]);
- break;
- case 1: /* FCVT_WU_S */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[rs1]);
- break;
-#if defined(TARGET_RISCV64)
- case 2: /* FCVT_L_S */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[rs1]);
- break;
- case 3: /* FCVT_LU_S */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[rs1]);
- break;
-#endif
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FCVT_S_W:
- /* also OPC_RISC_FCVT_S_WU, OPC_RISC_FCVT_S_L, OPC_RISC_FCVT_S_LU */
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- switch (rs2) {
- case 0: /* FCVT_S_W */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_w(cpu_fpr[rd], cpu_env, t0);
- break;
- case 1: /* FCVT_S_WU */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_wu(cpu_fpr[rd], cpu_env, t0);
- break;
-#if defined(TARGET_RISCV64)
- case 2: /* FCVT_S_L */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_l(cpu_fpr[rd], cpu_env, t0);
- break;
- case 3: /* FCVT_S_LU */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_lu(cpu_fpr[rd], cpu_env, t0);
- break;
-#endif
- default:
- goto do_illegal;
- }
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FMV_X_S:
- /* also OPC_RISC_FCLASS_S */
- t0 = tcg_temp_new();
- switch (rm) {
- case 0: /* FMV */
-#if defined(TARGET_RISCV64)
- tcg_gen_ext32s_tl(t0, cpu_fpr[rs1]);
-#else
- tcg_gen_extrl_i64_i32(t0, cpu_fpr[rs1]);
-#endif
- break;
- case 1:
- gen_helper_fclass_s(t0, cpu_fpr[rs1]);
- break;
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FMV_S_X:
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
-#if defined(TARGET_RISCV64)
- tcg_gen_mov_i64(cpu_fpr[rd], t0);
-#else
- tcg_gen_extu_i32_i64(cpu_fpr[rd], t0);
-#endif
- tcg_temp_free(t0);
- break;
-
- /* double */
- case OPC_RISC_FADD_D:
- gen_set_rm(ctx, rm);
- gen_helper_fadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FSUB_D:
- gen_set_rm(ctx, rm);
- gen_helper_fsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FMUL_D:
- gen_set_rm(ctx, rm);
- gen_helper_fmul_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FDIV_D:
- gen_set_rm(ctx, rm);
- gen_helper_fdiv_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FSQRT_D:
- gen_set_rm(ctx, rm);
- gen_helper_fsqrt_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
- break;
- case OPC_RISC_FSGNJ_D:
- gen_fsgnj(ctx, rd, rs1, rs2, rm, INT64_MIN);
- break;
-
- case OPC_RISC_FMIN_D:
- /* also OPC_RISC_FMAX_D */
- switch (rm) {
- case 0:
- gen_helper_fmin_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 1:
- gen_helper_fmax_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- default:
- goto do_illegal;
- }
- break;
-
- case OPC_RISC_FCVT_S_D:
- switch (rs2) {
- case 1:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
- break;
- default:
- goto do_illegal;
- }
- break;
-
- case OPC_RISC_FCVT_D_S:
- switch (rs2) {
- case 0:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
- break;
- default:
- goto do_illegal;
- }
- break;
-
- case OPC_RISC_FEQ_D:
- /* also OPC_RISC_FLT_D, OPC_RISC_FLE_D */
- t0 = tcg_temp_new();
- switch (rm) {
- case 0:
- gen_helper_fle_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 1:
- gen_helper_flt_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 2:
- gen_helper_feq_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FCVT_W_D:
- /* also OPC_RISC_FCVT_WU_D, OPC_RISC_FCVT_L_D, OPC_RISC_FCVT_LU_D */
- t0 = tcg_temp_new();
- switch (rs2) {
- case 0:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[rs1]);
- break;
- case 1:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[rs1]);
- break;
-#if defined(TARGET_RISCV64)
- case 2:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[rs1]);
- break;
- case 3:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[rs1]);
- break;
-#endif
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FCVT_D_W:
- /* also OPC_RISC_FCVT_D_WU, OPC_RISC_FCVT_D_L, OPC_RISC_FCVT_D_LU */
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- switch (rs2) {
- case 0:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_w(cpu_fpr[rd], cpu_env, t0);
- break;
- case 1:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_wu(cpu_fpr[rd], cpu_env, t0);
- break;
-#if defined(TARGET_RISCV64)
- case 2:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_l(cpu_fpr[rd], cpu_env, t0);
- break;
- case 3:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_lu(cpu_fpr[rd], cpu_env, t0);
- break;
-#endif
- default:
- goto do_illegal;
- }
- tcg_temp_free(t0);
- break;
-
-#if defined(TARGET_RISCV64)
- case OPC_RISC_FMV_X_D:
- /* also OPC_RISC_FCLASS_D */
- switch (rm) {
- case 0: /* FMV */
- gen_set_gpr(rd, cpu_fpr[rs1]);
- break;
- case 1:
- t0 = tcg_temp_new();
- gen_helper_fclass_d(t0, cpu_fpr[rs1]);
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- break;
- default:
- goto do_illegal;
- }
- break;
-
- case OPC_RISC_FMV_D_X:
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_mov_tl(cpu_fpr[rd], t0);
- tcg_temp_free(t0);
- break;
-#endif
-
- default:
- do_illegal:
- if (t0) {
- tcg_temp_free(t0);
- }
- gen_exception_illegal(ctx);
- break;
- }
-}
static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
int rd, int rs1, int csr)
@@ -1509,11 +1059,8 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
- int rs1;
- int rs2;
- int rd;
+ int rs1, rd;
uint32_t op;
- target_long imm;
/* We do not do misaligned address check here: the address should never be
* misaligned at this point. Instructions that set PC must do the check,
@@ -1522,38 +1069,9 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
op = MASK_OP_MAJOR(ctx->opcode);
rs1 = GET_RS1(ctx->opcode);
- rs2 = GET_RS2(ctx->opcode);
rd = GET_RD(ctx->opcode);
- imm = GET_IMM(ctx->opcode);
switch (op) {
- case OPC_RISC_FP_LOAD:
- gen_fp_load(ctx, MASK_OP_FP_LOAD(ctx->opcode), rd, rs1, imm);
- break;
- case OPC_RISC_FP_STORE:
- gen_fp_store(ctx, MASK_OP_FP_STORE(ctx->opcode), rs1, rs2,
- GET_STORE_IMM(ctx->opcode));
- break;
- case OPC_RISC_FMADD:
- gen_fp_fmadd(ctx, MASK_OP_FP_FMADD(ctx->opcode), rd, rs1, rs2,
- GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
- break;
- case OPC_RISC_FMSUB:
- gen_fp_fmsub(ctx, MASK_OP_FP_FMSUB(ctx->opcode), rd, rs1, rs2,
- GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
- break;
- case OPC_RISC_FNMSUB:
- gen_fp_fnmsub(ctx, MASK_OP_FP_FNMSUB(ctx->opcode), rd, rs1, rs2,
- GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
- break;
- case OPC_RISC_FNMADD:
- gen_fp_fnmadd(ctx, MASK_OP_FP_FNMADD(ctx->opcode), rd, rs1, rs2,
- GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
- break;
- case OPC_RISC_FP_ARITH:
- gen_fp_arith(ctx, MASK_OP_FP_ARITH(ctx->opcode), rd, rs1, rs2,
- GET_RM(ctx->opcode));
- break;
case OPC_RISC_SYSTEM:
gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
(ctx->opcode & 0xFFF00000) >> 20);
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 15/29] target/riscv: Convert RV priv insns to decodetree
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (13 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 14/29] target/riscv: Convert RV64D " Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 16/29] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
` (14 subsequent siblings)
29 siblings, 0 replies; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32.decode | 15 +++
.../riscv/insn_trans/trans_privileged.inc.c | 111 ++++++++++++++++++
target/riscv/translate.c | 49 +-------
3 files changed, 127 insertions(+), 48 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c347102378..ffb4f00274 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -63,6 +63,21 @@
@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
+@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
+@sfence_vm ....... ..... ..... ... ..... ....... %rs1
+
+
+# *** Privileged Instructions ***
+ecall 000000000000 00000 000 00000 1110011
+ebreak 000000000001 00000 000 00000 1110011
+uret 0000000 00010 00000 000 00000 1110011
+sret 0001000 00010 00000 000 00000 1110011
+hret 0010000 00010 00000 000 00000 1110011
+mret 0011000 00010 00000 000 00000 1110011
+wfi 0001000 00101 00000 000 00000 1110011
+sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
+sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
+
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
auipc .................... ..... 0010111 @u
diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c
new file mode 100644
index 0000000000..9534adb025
--- /dev/null
+++ b/target/riscv/insn_trans/trans_privileged.inc.c
@@ -0,0 +1,111 @@
+/*
+ * RISC-V translation routines for the RISC-V privileged instructions.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_ecall(DisasContext *ctx, arg_ecall *a, uint32_t insn)
+{
+ /* always generates U-level ECALL, fixed in do_interrupt handler */
+ generate_exception(ctx, RISCV_EXCP_U_ECALL);
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
+static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a, uint32_t insn)
+{
+ generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
+static bool trans_uret(DisasContext *ctx, arg_uret *a, uint32_t insn)
+{
+ gen_exception_illegal(ctx);
+ return true;
+}
+
+static bool trans_sret(DisasContext *ctx, arg_sret *a, uint32_t insn)
+{
+#ifndef CONFIG_USER_ONLY
+ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+ CPURISCVState *env = current_cpu->env_ptr;
+ if (riscv_has_ext(env, RVS)) {
+ gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ ctx->base.is_jmp = DISAS_NORETURN;
+ } else {
+ gen_exception_illegal(ctx);
+ }
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hret(DisasContext *ctx, arg_hret *a, uint32_t insn)
+{
+ gen_exception_illegal(ctx);
+ return true;
+}
+
+static bool trans_mret(DisasContext *ctx, arg_mret *a, uint32_t insn)
+{
+#ifndef CONFIG_USER_ONLY
+ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+ gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_wfi(DisasContext *ctx, arg_wfi *a, uint32_t insn)
+{
+#ifndef CONFIG_USER_ONLY
+ tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+ gen_helper_wfi(cpu_env);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a,
+ uint32_t insn)
+{
+#ifndef CONFIG_USER_ONLY
+ gen_helper_tlb_flush(cpu_env);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a, uint32_t insn)
+{
+#ifndef CONFIG_USER_ONLY
+ gen_helper_tlb_flush(cpu_env);
+ return true;
+#else
+ return false;
+#endif
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 89d1278974..1e0f517170 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -690,22 +690,8 @@ static void gen_set_rm(DisasContext *ctx, int rm)
static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
int rd, int rs1, int csr)
{
- TCGv source1, dest;
- source1 = tcg_temp_new();
- dest = tcg_temp_new();
- gen_get_gpr(source1, rs1);
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-#ifndef CONFIG_USER_ONLY
- /* Extract funct7 value and check whether it matches SFENCE.VMA */
- if ((opc == OPC_RISC_ECALL) && ((csr >> 5) == 9)) {
- /* sfence.vma */
- /* TODO: handle ASID specific fences */
- gen_helper_tlb_flush(cpu_env);
- return;
- }
-#endif
-
switch (opc) {
case OPC_RISC_ECALL:
switch (csr) {
@@ -720,46 +706,12 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
tcg_gen_exit_tb(NULL, 0); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
break;
-#ifndef CONFIG_USER_ONLY
- case 0x002: /* URET */
- gen_exception_illegal(ctx);
- break;
- case 0x102: /* SRET */
- if (riscv_has_ext(env, RVS)) {
- gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- } else {
- gen_exception_illegal(ctx);
- }
- break;
- case 0x202: /* HRET */
- gen_exception_illegal(ctx);
- break;
- case 0x302: /* MRET */
- gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
- case 0x7b2: /* DRET */
- gen_exception_illegal(ctx);
- break;
- case 0x105: /* WFI */
- tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- gen_helper_wfi(cpu_env);
- break;
- case 0x104: /* SFENCE.VM */
- gen_helper_tlb_flush(cpu_env);
- break;
-#endif
default:
gen_exception_illegal(ctx);
break;
}
break;
}
- tcg_temp_free(source1);
- tcg_temp_free(dest);
}
static void decode_RV32_64C0(DisasContext *ctx)
@@ -1056,6 +1008,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
#include "insn_trans/trans_rva.inc.c"
#include "insn_trans/trans_rvf.inc.c"
#include "insn_trans/trans_rvd.inc.c"
+#include "insn_trans/trans_privileged.inc.c"
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 16/29] target/riscv: Convert quadrant 0 of RVXC insns to decodetree
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (14 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 15/29] target/riscv: Convert RV priv " Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-23 8:31 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 17/29] target/riscv: Convert quadrant 1 " Bastian Koppelmann
` (13 subsequent siblings)
29 siblings, 1 reply; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v1 -> v2:
- Stack allocate arg_c_* structs
- ex_rvc_register returns int
- special case of trans_c_addi4spn() returns false
target/riscv/Makefile.objs | 9 ++-
target/riscv/insn16.decode | 55 +++++++++++++++
target/riscv/insn_trans/trans_rvc.inc.c | 89 +++++++++++++++++++++++++
target/riscv/translate.c | 88 +++++-------------------
4 files changed, 168 insertions(+), 73 deletions(-)
create mode 100644 target/riscv/insn16.decode
create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index ea02f9b9ef..ec7326f1c7 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -8,4 +8,11 @@ target/riscv/decode_insn32.inc.c: \
$(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $<, \
"GEN", $(TARGET_DIR)$@)
-target/riscv/translate.o: target/riscv/decode_insn32.inc.c
+target/riscv/decode_insn16.inc.c: \
+ $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
+ $(call quiet-command, \
+ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<, \
+ "GEN", $(TARGET_DIR)$@)
+
+target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
+ target/riscv/decode_insn16.inc.c
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
new file mode 100644
index 0000000000..558c0c41f0
--- /dev/null
+++ b/target/riscv/insn16.decode
@@ -0,0 +1,55 @@
+#
+# RISC-V translation routines for the RVXI Base Integer Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see <http://www.gnu.org/licenses/>.
+
+# Fields:
+%rd 7:5
+%rs1_3 7:3 !function=ex_rvc_register
+%rs2_3 2:3 !function=ex_rvc_register
+
+# Immediates:
+%nzuimm_ciw 7:4 11:2 5:1 6:1 !function=ex_shift_2
+%uimm_cl_d 5:2 10:3 !function=ex_shift_3
+%uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2
+
+
+# Argument sets:
+&cl rs1 rd
+&cl_dw uimm rs1 rd
+&ciw nzuimm rd
+&cs rs1 rs2
+&cs_dw uimm rs1 rs2
+
+
+# Formats 16:
+@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3
+@cl_d ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
+@cl_w ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
+@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3
+@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3
+@cs_d ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
+@cs_w ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
+
+
+# *** RV64C Standard Extension (Quadrant 0) ***
+c_addi4spn 000 ........ ... 00 @ciw
+c_fld 001 ... ... .. ... 00 @cl_d
+c_lw 010 ... ... .. ... 00 @cl_w
+c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually
+c_fsd 101 ... ... .. ... 00 @cs_d
+c_sw 110 ... ... .. ... 00 @cs_w
+c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
new file mode 100644
index 0000000000..a959f04421
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -0,0 +1,89 @@
+/*
+ * RISC-V translation routines for the RVC Compressed Instruction Set.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a,
+ uint16_t insn)
+{
+ if (a->nzuimm == 0) {
+ /* Reserved in ISA */
+ gen_exception_illegal(ctx);
+ return true;
+ }
+ arg_addi arg = { .rd = a->rd, .rs1 = 2, .imm = a->nzuimm };
+ return trans_addi(ctx, &arg, insn);
+}
+
+static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a, uint16_t insn)
+{
+ arg_fld arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
+ return trans_fld(ctx, &arg, insn);
+}
+
+static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a, uint16_t insn)
+{
+ arg_lw arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
+ return trans_lw(ctx, &arg, insn);
+}
+
+static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a, uint16_t insn)
+{
+#ifdef TARGET_RISCV32
+ /* C.FLW ( RV32FC-only ) */
+ arg_c_lw tmp;
+ extract_cl_w(&tmp, insn);
+ arg_flw arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
+ return trans_flw(ctx, &arg, insn);
+#else
+ /* C.LD ( RV64C/RV128C-only ) */
+ arg_c_fld tmp;
+ extract_cl_d(&tmp, insn);
+ arg_ld arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
+ return trans_ld(ctx, &arg, insn);
+#endif
+}
+
+static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a, uint16_t insn)
+{
+ arg_fsd arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
+ return trans_fsd(ctx, &arg, insn);
+}
+
+static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a, uint16_t insn)
+{
+ arg_sw arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
+ return trans_sw(ctx, &arg, insn);
+}
+
+static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a, uint16_t insn)
+{
+#ifdef TARGET_RISCV32
+ /* C.FSW ( RV32FC-only ) */
+ arg_c_sw tmp;
+ extract_cs_w(&tmp, insn);
+ arg_fsw arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
+ return trans_fsw(ctx, &arg, insn);
+#else
+ /* C.SD ( RV64C/RV128C-only ) */
+ arg_c_fsd tmp;
+ extract_cs_d(&tmp, insn);
+ arg_sd arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
+ return trans_sd(ctx, &arg, insn);
+#endif
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1e0f517170..8182946ee8 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -714,74 +714,6 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
}
}
-static void decode_RV32_64C0(DisasContext *ctx)
-{
- uint8_t funct3 = extract32(ctx->opcode, 13, 3);
- uint8_t rd_rs2 = GET_C_RS2S(ctx->opcode);
- uint8_t rs1s = GET_C_RS1S(ctx->opcode);
-
- switch (funct3) {
- case 0:
- /* illegal */
- if (ctx->opcode == 0) {
- gen_exception_illegal(ctx);
- } else {
- /* C.ADDI4SPN -> addi rd', x2, zimm[9:2]*/
- gen_arith_imm(ctx, OPC_RISC_ADDI, rd_rs2, 2,
- GET_C_ADDI4SPN_IMM(ctx->opcode));
- }
- break;
- case 1:
- /* C.FLD -> fld rd', offset[7:3](rs1')*/
- gen_fp_load(ctx, OPC_RISC_FLD, rd_rs2, rs1s,
- GET_C_LD_IMM(ctx->opcode));
- /* C.LQ(RV128) */
- break;
- case 2:
- /* C.LW -> lw rd', offset[6:2](rs1') */
- gen_load(ctx, OPC_RISC_LW, rd_rs2, rs1s,
- GET_C_LW_IMM(ctx->opcode));
- break;
- case 3:
-#if defined(TARGET_RISCV64)
- /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
- gen_load(ctx, OPC_RISC_LD, rd_rs2, rs1s,
- GET_C_LD_IMM(ctx->opcode));
-#else
- /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
- gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
- GET_C_LW_IMM(ctx->opcode));
-#endif
- break;
- case 4:
- /* reserved */
- gen_exception_illegal(ctx);
- break;
- case 5:
- /* C.FSD(RV32/64) -> fsd rs2', offset[7:3](rs1') */
- gen_fp_store(ctx, OPC_RISC_FSD, rs1s, rd_rs2,
- GET_C_LD_IMM(ctx->opcode));
- /* C.SQ (RV128) */
- break;
- case 6:
- /* C.SW -> sw rs2', offset[6:2](rs1')*/
- gen_store(ctx, OPC_RISC_SW, rs1s, rd_rs2,
- GET_C_LW_IMM(ctx->opcode));
- break;
- case 7:
-#if defined(TARGET_RISCV64)
- /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
- gen_store(ctx, OPC_RISC_SD, rs1s, rd_rs2,
- GET_C_LD_IMM(ctx->opcode));
-#else
- /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
- gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
- GET_C_LW_IMM(ctx->opcode));
-#endif
- break;
- }
-}
-
static void decode_RV32_64C1(CPURISCVState *env, DisasContext *ctx)
{
uint8_t funct3 = extract32(ctx->opcode, 13, 3);
@@ -979,9 +911,6 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
uint8_t op = extract32(ctx->opcode, 0, 2);
switch (op) {
- case 0:
- decode_RV32_64C0(ctx);
- break;
case 1:
decode_RV32_64C1(env, ctx);
break;
@@ -997,8 +926,15 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
return imm << amount; \
}
EX_SH(1)
+EX_SH(2)
+EX_SH(3)
EX_SH(12)
+static int ex_rvc_register(int reg)
+{
+ return 8 + reg;
+}
+
bool decode_insn32(DisasContext *ctx, uint32_t insn);
/* Include the auto-generated decoder for 32 bit insn */
#include "decode_insn32.inc.c"
@@ -1010,6 +946,11 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
#include "insn_trans/trans_rvd.inc.c"
#include "insn_trans/trans_privileged.inc.c"
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
+/* auto-generated decoder*/
+#include "decode_insn16.inc.c"
+#include "insn_trans/trans_rvc.inc.c"
+
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
int rs1, rd;
@@ -1043,7 +984,10 @@ static void decode_opc(DisasContext *ctx)
gen_exception_illegal(ctx);
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 2;
- decode_RV32_64C(ctx->env, ctx);
+ if (!decode_insn16(ctx, ctx->opcode)) {
+ /* fall back to old decoder */
+ decode_RV32_64C(ctx->env, ctx);
+ }
}
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 4;
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (15 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 16/29] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-23 8:35 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 18/29] target/riscv: Convert quadrant 2 " Bastian Koppelmann
` (12 subsequent siblings)
29 siblings, 1 reply; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v1 -> v2:
- consistently return false for reserved cases instead of raising an
exception
- simplified trans_c_srli by Richard's suggestion
- remove extract_cj() since its result isn't used
target/riscv/insn16.decode | 43 +++++++
target/riscv/insn_trans/trans_rvc.inc.c | 149 +++++++++++++++++++++++-
target/riscv/translate.c | 118 +------------------
3 files changed, 191 insertions(+), 119 deletions(-)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 558c0c41f0..29dade0fa1 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -22,28 +22,53 @@
%rs2_3 2:3 !function=ex_rvc_register
# Immediates:
+%imm_ci 12:s1 2:5
%nzuimm_ciw 7:4 11:2 5:1 6:1 !function=ex_shift_2
%uimm_cl_d 5:2 10:3 !function=ex_shift_3
%uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2
+%imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1
+%imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
+
+%nzuimm_6bit 12:1 2:5
+
+%imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4
+%imm_lui 12:s1 2:5 !function=ex_shift_12
+
# Argument sets:
&cl rs1 rd
&cl_dw uimm rs1 rd
+&ci imm rd
&ciw nzuimm rd
&cs rs1 rs2
&cs_dw uimm rs1 rs2
+&cb imm rs1
+&cr rd rs2
+&c_j imm
+&c_shift shamt rd
+
+&c_addi16sp_lui imm_lui imm_addi16sp rd
# Formats 16:
+@ci ... . ..... ..... .. &ci imm=%imm_ci %rd
@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3
@cl_d ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
@cl_w ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3
@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3
+@cs_2 ... ... ... .. ... .. &cr rd=%rs1_3 rs2=%rs2_3
@cs_d ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
@cs_w ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
+@cb ... ... ... .. ... .. &cb imm=%imm_cb rs1=%rs1_3
+@cj ... ........... .. &c_j imm=%imm_cj
+@c_addi16sp_lui ... . ..... ..... .. &c_addi16sp_lui %imm_lui %imm_addi16sp %rd
+
+@c_shift ... . .. ... ..... .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
+
+@c_andi ... . .. ... ..... .. &ci imm=%imm_ci rd=%rs1_3
# *** RV64C Standard Extension (Quadrant 0) ***
c_addi4spn 000 ........ ... 00 @ciw
@@ -53,3 +78,21 @@ c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually
c_fsd 101 ... ... .. ... 00 @cs_d
c_sw 110 ... ... .. ... 00 @cs_w
c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually
+
+# *** RV64C Standard Extension (Quadrant 1) ***
+c_addi 000 . ..... ..... 01 @ci
+c_jal_addiw 001 . ..... ..... 01 @ci #Note: parse rd and/or imm manually
+c_li 010 . ..... ..... 01 @ci
+c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with C.LUI
+c_srli 100 . 00 ... ..... 01 @c_shift
+c_srai 100 . 01 ... ..... 01 @c_shift
+c_andi 100 . 10 ... ..... 01 @c_andi
+c_sub 100 0 11 ... 00 ... 01 @cs_2
+c_xor 100 0 11 ... 01 ... 01 @cs_2
+c_or 100 0 11 ... 10 ... 01 @cs_2
+c_and 100 0 11 ... 11 ... 01 @cs_2
+c_subw 100 1 11 ... 00 ... 01 @cs_2
+c_addw 100 1 11 ... 01 ... 01 @cs_2
+c_j 101 ........... 01 @cj
+c_beqz 110 ... ... ..... 01 @cb
+c_bnez 111 ... ... ..... 01 @cb
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index a959f04421..dc7d9922f2 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -23,8 +23,7 @@ static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a,
{
if (a->nzuimm == 0) {
/* Reserved in ISA */
- gen_exception_illegal(ctx);
- return true;
+ return false;
}
arg_addi arg = { .rd = a->rd, .rs1 = 2, .imm = a->nzuimm };
return trans_addi(ctx, &arg, insn);
@@ -87,3 +86,149 @@ static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a, uint16_t insn)
return trans_sd(ctx, &arg, insn);
#endif
}
+
+static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a, uint16_t insn)
+{
+ if (a->imm == 0) {
+ /* Hint: insn is valid but does not affect state */
+ return true;
+ }
+ arg_addi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
+ return trans_addi(ctx, &arg, insn);
+}
+
+static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a,
+ uint16_t insn)
+{
+#ifdef TARGET_RISCV32
+ /* C.JAL */
+ arg_jal arg = { .rd = 1, .imm = a->imm };
+ return trans_jal(ctx, &arg, insn);
+#else
+ /* C.ADDIW */
+ arg_addiw arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
+ return trans_addiw(ctx, &arg, insn);
+#endif
+}
+
+static bool trans_c_li(DisasContext *ctx, arg_c_li *a, uint16_t insn)
+{
+ if (a->rd == 0) {
+ /* Hint: insn is valid but does not affect state */
+ return true;
+ }
+ arg_addi arg = { .rd = a->rd, .rs1 = 0, .imm = a->imm };
+ return trans_addi(ctx, &arg, insn);
+}
+
+static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a,
+ uint16_t insn)
+{
+ if (a->rd == 2) {
+ /* C.ADDI16SP */
+ arg_addi arg = { .rd = 2, .rs1 = 2, .imm = a->imm_addi16sp };
+ return trans_addi(ctx, &arg, insn);
+ } else if (a->imm_lui != 0) {
+ /* C.LUI */
+ if (a->rd == 0) {
+ /* Hint: insn is valid but does not affect state */
+ return true;
+ }
+ arg_lui arg = { .rd = a->rd, .imm = a->imm_lui };
+ return trans_lui(ctx, &arg, insn);
+ }
+ return false;
+}
+
+static bool trans_c_srli(DisasContext *ctx, arg_c_srli *a, uint16_t insn)
+{
+ int shamt = a->shamt;
+ if (shamt == 0) {
+ /* For RV128 a shamt of 0 means a shift by 64 */
+ shamt = 64;
+ }
+ /* Ensure, that shamt[5] is zero for RV32 */
+ if (shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ arg_srli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
+ return trans_srli(ctx, &arg, insn);
+}
+
+static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a, uint16_t insn)
+{
+ if (a->shamt == 0) {
+ /* Reserved in ISA */
+ return false;
+ }
+#ifdef TARGET_RISCV32
+ /* Ensure, that shamt[5] is zero for RV32 */
+ if (a->shamt >= 32) {
+ return false;
+ }
+#endif
+
+ arg_srai arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
+ return trans_srai(ctx, &arg, insn);
+}
+
+static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a, uint16_t insn)
+{
+ arg_andi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
+ return trans_andi(ctx, &arg, insn);
+}
+
+static bool trans_c_sub(DisasContext *ctx, arg_c_sub *a, uint16_t insn)
+{
+ arg_sub arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_sub(ctx, &arg, insn);
+}
+
+static bool trans_c_xor(DisasContext *ctx, arg_c_xor *a, uint16_t insn)
+{
+ arg_xor arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_xor(ctx, &arg, insn);
+}
+
+static bool trans_c_or(DisasContext *ctx, arg_c_or *a, uint16_t insn)
+{
+ arg_or arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_or(ctx, &arg, insn);
+}
+
+static bool trans_c_and(DisasContext *ctx, arg_c_and *a, uint16_t insn)
+{
+ arg_and arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_and(ctx, &arg, insn);
+}
+
+static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a, uint16_t insn)
+{
+ arg_subw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_subw(ctx, &arg, insn);
+}
+
+static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a, uint16_t insn)
+{
+ arg_addw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_addw(ctx, &arg, insn);
+}
+
+static bool trans_c_j(DisasContext *ctx, arg_c_j *a, uint16_t insn)
+{
+ arg_jal arg = { .rd = 0, .imm = a->imm };
+ return trans_jal(ctx, &arg, insn);
+}
+
+static bool trans_c_beqz(DisasContext *ctx, arg_c_beqz *a, uint16_t insn)
+{
+ arg_beq arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
+ return trans_beq(ctx, &arg, insn);
+}
+
+static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a, uint16_t insn)
+{
+ arg_bne arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
+ return trans_bne(ctx, &arg, insn);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8182946ee8..88aa355703 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -714,120 +714,6 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
}
}
-static void decode_RV32_64C1(CPURISCVState *env, DisasContext *ctx)
-{
- uint8_t funct3 = extract32(ctx->opcode, 13, 3);
- uint8_t rd_rs1 = GET_C_RS1(ctx->opcode);
- uint8_t rs1s, rs2s;
- uint8_t funct2;
-
- switch (funct3) {
- case 0:
- /* C.ADDI -> addi rd, rd, nzimm[5:0] */
- gen_arith_imm(ctx, OPC_RISC_ADDI, rd_rs1, rd_rs1,
- GET_C_IMM(ctx->opcode));
- break;
- case 1:
-#if defined(TARGET_RISCV64)
- /* C.ADDIW (RV64/128) -> addiw rd, rd, imm[5:0]*/
- gen_arith_imm(ctx, OPC_RISC_ADDIW, rd_rs1, rd_rs1,
- GET_C_IMM(ctx->opcode));
-#else
- /* C.JAL(RV32) -> jal x1, offset[11:1] */
- gen_jal(env, ctx, 1, GET_C_J_IMM(ctx->opcode));
-#endif
- break;
- case 2:
- /* C.LI -> addi rd, x0, imm[5:0]*/
- gen_arith_imm(ctx, OPC_RISC_ADDI, rd_rs1, 0, GET_C_IMM(ctx->opcode));
- break;
- case 3:
- if (rd_rs1 == 2) {
- /* C.ADDI16SP -> addi x2, x2, nzimm[9:4]*/
- gen_arith_imm(ctx, OPC_RISC_ADDI, 2, 2,
- GET_C_ADDI16SP_IMM(ctx->opcode));
- } else if (rd_rs1 != 0) {
- /* C.LUI (rs1/rd =/= {0,2}) -> lui rd, nzimm[17:12]*/
- tcg_gen_movi_tl(cpu_gpr[rd_rs1],
- GET_C_IMM(ctx->opcode) << 12);
- }
- break;
- case 4:
- funct2 = extract32(ctx->opcode, 10, 2);
- rs1s = GET_C_RS1S(ctx->opcode);
- switch (funct2) {
- case 0: /* C.SRLI(RV32) -> srli rd', rd', shamt[5:0] */
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, rs1s, rs1s,
- GET_C_ZIMM(ctx->opcode));
- /* C.SRLI64(RV128) */
- break;
- case 1:
- /* C.SRAI -> srai rd', rd', shamt[5:0]*/
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, rs1s, rs1s,
- GET_C_ZIMM(ctx->opcode) | 0x400);
- /* C.SRAI64(RV128) */
- break;
- case 2:
- /* C.ANDI -> andi rd', rd', imm[5:0]*/
- gen_arith_imm(ctx, OPC_RISC_ANDI, rs1s, rs1s,
- GET_C_IMM(ctx->opcode));
- break;
- case 3:
- funct2 = extract32(ctx->opcode, 5, 2);
- rs2s = GET_C_RS2S(ctx->opcode);
- switch (funct2) {
- case 0:
- /* C.SUB -> sub rd', rd', rs2' */
- if (extract32(ctx->opcode, 12, 1) == 0) {
- gen_arith(ctx, OPC_RISC_SUB, rs1s, rs1s, rs2s);
- }
-#if defined(TARGET_RISCV64)
- else {
- gen_arith(ctx, OPC_RISC_SUBW, rs1s, rs1s, rs2s);
- }
-#endif
- break;
- case 1:
- /* C.XOR -> xor rs1', rs1', rs2' */
- if (extract32(ctx->opcode, 12, 1) == 0) {
- gen_arith(ctx, OPC_RISC_XOR, rs1s, rs1s, rs2s);
- }
-#if defined(TARGET_RISCV64)
- else {
- /* C.ADDW (RV64/128) */
- gen_arith(ctx, OPC_RISC_ADDW, rs1s, rs1s, rs2s);
- }
-#endif
- break;
- case 2:
- /* C.OR -> or rs1', rs1', rs2' */
- gen_arith(ctx, OPC_RISC_OR, rs1s, rs1s, rs2s);
- break;
- case 3:
- /* C.AND -> and rs1', rs1', rs2' */
- gen_arith(ctx, OPC_RISC_AND, rs1s, rs1s, rs2s);
- break;
- }
- break;
- }
- break;
- case 5:
- /* C.J -> jal x0, offset[11:1]*/
- gen_jal(env, ctx, 0, GET_C_J_IMM(ctx->opcode));
- break;
- case 6:
- /* C.BEQZ -> beq rs1', x0, offset[8:1]*/
- rs1s = GET_C_RS1S(ctx->opcode);
- gen_branch(env, ctx, OPC_RISC_BEQ, rs1s, 0, GET_C_B_IMM(ctx->opcode));
- break;
- case 7:
- /* C.BNEZ -> bne rs1', x0, offset[8:1]*/
- rs1s = GET_C_RS1S(ctx->opcode);
- gen_branch(env, ctx, OPC_RISC_BNE, rs1s, 0, GET_C_B_IMM(ctx->opcode));
- break;
- }
-}
-
static void decode_RV32_64C2(CPURISCVState *env, DisasContext *ctx)
{
uint8_t rd, rs2;
@@ -911,9 +797,6 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
uint8_t op = extract32(ctx->opcode, 0, 2);
switch (op) {
- case 1:
- decode_RV32_64C1(env, ctx);
- break;
case 2:
decode_RV32_64C2(env, ctx);
break;
@@ -928,6 +811,7 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
EX_SH(1)
EX_SH(2)
EX_SH(3)
+EX_SH(4)
EX_SH(12)
static int ex_rvc_register(int reg)
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 18/29] target/riscv: Convert quadrant 2 of RVXC insns to decodetree
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (16 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 17/29] target/riscv: Convert quadrant 1 " Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-23 8:39 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 19/29] target/riscv: Remove gen_jalr() Bastian Koppelmann
` (11 subsequent siblings)
29 siblings, 1 reply; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
This also removes all functions that now became obsolete.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/riscv/insn16.decode | 34 +++++-
target/riscv/insn_trans/trans_rvc.inc.c | 103 ++++++++++++++++
target/riscv/translate.c | 151 +-----------------------
3 files changed, 135 insertions(+), 153 deletions(-)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 29dade0fa1..138290c450 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -20,6 +20,7 @@
%rd 7:5
%rs1_3 7:3 !function=ex_rvc_register
%rs2_3 2:3 !function=ex_rvc_register
+%rs2_5 2:5
# Immediates:
%imm_ci 12:s1 2:5
@@ -30,12 +31,14 @@
%imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
%nzuimm_6bit 12:1 2:5
+%uimm_6bit_ld 2:3 12:1 5:2 !function=ex_shift_3
+%uimm_6bit_lw 2:2 12:1 4:3 !function=ex_shift_2
+%uimm_6bit_sd 7:3 10:3 !function=ex_shift_3
+%uimm_6bit_sw 7:2 9:4 !function=ex_shift_2
%imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4
%imm_lui 12:s1 2:5 !function=ex_shift_12
-
-
# Argument sets:
&cl rs1 rd
&cl_dw uimm rs1 rd
@@ -47,11 +50,15 @@
&cr rd rs2
&c_j imm
&c_shift shamt rd
-
+&c_ld uimm rd
+&c_sd uimm rs2
&c_addi16sp_lui imm_lui imm_addi16sp rd
+&c_flwsp_ldsp uimm_flwsp uimm_ldsp rd
+&c_fswsp_sdsp uimm_fswsp uimm_sdsp rs2
# Formats 16:
+@cr .... ..... ..... .. &cr rs2=%rs2_5 %rd
@ci ... . ..... ..... .. &ci imm=%imm_ci %rd
@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3
@cl_d ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
@@ -64,9 +71,19 @@
@cb ... ... ... .. ... .. &cb imm=%imm_cb rs1=%rs1_3
@cj ... ........... .. &c_j imm=%imm_cj
+@c_ld ... . ..... ..... .. &c_ld uimm=%uimm_6bit_ld %rd
+@c_lw ... . ..... ..... .. &c_ld uimm=%uimm_6bit_lw %rd
+@c_sd ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sd rs2=%rs2_5
+@c_sw ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sw rs2=%rs2_5
+
@c_addi16sp_lui ... . ..... ..... .. &c_addi16sp_lui %imm_lui %imm_addi16sp %rd
+@c_flwsp_ldsp ... . ..... ..... .. &c_flwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
+ uimm_ldsp=%uimm_6bit_ld %rd
+@c_fswsp_sdsp ... . ..... ..... .. &c_fswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
+ uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
@c_shift ... . .. ... ..... .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
+@c_shift2 ... . .. ... ..... .. &c_shift rd=%rd shamt=%nzuimm_6bit
@c_andi ... . .. ... ..... .. &ci imm=%imm_ci rd=%rs1_3
@@ -96,3 +113,14 @@ c_addw 100 1 11 ... 01 ... 01 @cs_2
c_j 101 ........... 01 @cj
c_beqz 110 ... ... ..... 01 @cb
c_bnez 111 ... ... ..... 01 @cb
+
+# *** RV64C Standard Extension (Quadrant 2) ***
+c_slli 000 . ..... ..... 10 @c_shift2
+c_fldsp 001 . ..... ..... 10 @c_ld
+c_lwsp 010 . ..... ..... 10 @c_lw
+c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
+c_jr_mv 100 0 ..... ..... 10 @cr
+c_ebreak_jalr_add 100 1 ..... ..... 10 @cr
+c_fsdsp 101 ...... ..... 10 @c_sd
+c_swsp 110 . ..... ..... 10 @c_sw
+c_fswsp_sdsp 111 . ..... ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index dc7d9922f2..593dfb82a3 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -232,3 +232,106 @@ static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a, uint16_t insn)
arg_bne arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
return trans_bne(ctx, &arg, insn);
}
+
+static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a, uint16_t insn)
+{
+ int shamt = a->shamt;
+ if (shamt == 0) {
+ /* For RV128 a shamt of 0 means a shift by 64 */
+ shamt = 64;
+ }
+ /* Ensure, that shamt[5] is zero for RV32 */
+ if (shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ arg_slli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
+ return trans_slli(ctx, &arg, insn);
+}
+
+static bool trans_c_fldsp(DisasContext *ctx, arg_c_fldsp *a, uint16_t insn)
+{
+ arg_fld arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
+ return trans_fld(ctx, &arg, insn);
+}
+
+static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a, uint16_t insn)
+{
+ arg_lw arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
+ return trans_lw(ctx, &arg, insn);
+}
+
+static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a,
+ uint16_t insn)
+{
+#ifdef TARGET_RISCV32
+ /* C.FLWSP */
+ arg_flw arg_flw = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_flwsp };
+ return trans_flw(ctx, &arg_flw, insn);
+#else
+ /* C.LDSP */
+ arg_ld arg_ld = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_ldsp };
+ return trans_ld(ctx, &arg_ld, insn);
+#endif
+ return false;
+}
+
+static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a, uint16_t insn)
+{
+ if (a->rd != 0 && a->rs2 == 0) {
+ /* C.JR */
+ arg_jalr arg = { .rd = 0, .rs1 = a->rd, .imm = 0 };
+ return trans_jalr(ctx, &arg, insn);
+ } else if (a->rd != 0 && a->rs2 != 0) {
+ /* C.MV */
+ arg_add arg = { .rd = a->rd, .rs1 = 0, .rs2 = a->rs2 };
+ return trans_add(ctx, &arg, insn);
+ }
+ return false;
+}
+
+static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_add *a,
+ uint16_t insn)
+{
+ if (a->rd == 0 && a->rs2 == 0) {
+ /* C.EBREAK */
+ arg_ebreak arg = { };
+ return trans_ebreak(ctx, &arg, insn);
+ } else if (a->rd != 0) {
+ if (a->rs2 == 0) {
+ /* C.JALR */
+ arg_jalr arg = { .rd = 1, .rs1 = a->rd, .imm = 0 };
+ return trans_jalr(ctx, &arg, insn);
+ } else {
+ /* C.ADD */
+ arg_add arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_add(ctx, &arg, insn);
+ }
+ }
+ return false;
+}
+
+static bool trans_c_fsdsp(DisasContext *ctx, arg_c_fsdsp *a, uint16_t insn)
+{
+ arg_fsd arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
+ return trans_fsd(ctx, &arg, insn);
+}
+
+static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a, uint16_t insn)
+{
+ arg_sw arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
+ return trans_sw(ctx, &arg, insn);
+}
+
+static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a,
+ uint16_t insn)
+{
+#ifdef TARGET_RISCV32
+ /* C.FSWSP */
+ arg_fsw a_fsw = { .rs1 = a->rs2, .rs2 = 2, .imm = a->uimm_fswsp };
+ return trans_fsw(ctx, &a_fsw, insn);
+#endif
+ /* C.SDSP */
+ arg_sd a_sd = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_sdsp };
+ return trans_sd(ctx, &a_sd, insn);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 88aa355703..4f241a5e1e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -614,65 +614,6 @@ static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
tcg_temp_free(dat);
}
-static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, target_long imm)
-{
- TCGv t0;
-
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
- gen_exception_illegal(ctx);
- return;
- }
-
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_addi_tl(t0, t0, imm);
-
- switch (opc) {
- case OPC_RISC_FLW:
- tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
- /* RISC-V requires NaN-boxing of narrower width floating point values */
- tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
- break;
- case OPC_RISC_FLD:
- tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
- tcg_temp_free(t0);
-}
-
-static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
- int rs2, target_long imm)
-{
- TCGv t0;
-
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
- gen_exception_illegal(ctx);
- return;
- }
-
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_addi_tl(t0, t0, imm);
-
- switch (opc) {
- case OPC_RISC_FSW:
- tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
- break;
- case OPC_RISC_FSD:
- tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
-
- tcg_temp_free(t0);
-}
-
static void gen_set_rm(DisasContext *ctx, int rm)
{
TCGv_i32 t0;
@@ -714,95 +655,6 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
}
}
-static void decode_RV32_64C2(CPURISCVState *env, DisasContext *ctx)
-{
- uint8_t rd, rs2;
- uint8_t funct3 = extract32(ctx->opcode, 13, 3);
-
-
- rd = GET_RD(ctx->opcode);
-
- switch (funct3) {
- case 0: /* C.SLLI -> slli rd, rd, shamt[5:0]
- C.SLLI64 -> */
- gen_arith_imm(ctx, OPC_RISC_SLLI, rd, rd, GET_C_ZIMM(ctx->opcode));
- break;
- case 1: /* C.FLDSP(RV32/64DC) -> fld rd, offset[8:3](x2) */
- gen_fp_load(ctx, OPC_RISC_FLD, rd, 2, GET_C_LDSP_IMM(ctx->opcode));
- break;
- case 2: /* C.LWSP -> lw rd, offset[7:2](x2) */
- gen_load(ctx, OPC_RISC_LW, rd, 2, GET_C_LWSP_IMM(ctx->opcode));
- break;
- case 3:
-#if defined(TARGET_RISCV64)
- /* C.LDSP(RVC64) -> ld rd, offset[8:3](x2) */
- gen_load(ctx, OPC_RISC_LD, rd, 2, GET_C_LDSP_IMM(ctx->opcode));
-#else
- /* C.FLWSP(RV32FC) -> flw rd, offset[7:2](x2) */
- gen_fp_load(ctx, OPC_RISC_FLW, rd, 2, GET_C_LWSP_IMM(ctx->opcode));
-#endif
- break;
- case 4:
- rs2 = GET_C_RS2(ctx->opcode);
-
- if (extract32(ctx->opcode, 12, 1) == 0) {
- if (rs2 == 0) {
- /* C.JR -> jalr x0, rs1, 0*/
- gen_jalr(env, ctx, OPC_RISC_JALR, 0, rd, 0);
- } else {
- /* C.MV -> add rd, x0, rs2 */
- gen_arith(ctx, OPC_RISC_ADD, rd, 0, rs2);
- }
- } else {
- if (rd == 0) {
- /* C.EBREAK -> ebreak*/
- gen_system(env, ctx, OPC_RISC_ECALL, 0, 0, 0x1);
- } else {
- if (rs2 == 0) {
- /* C.JALR -> jalr x1, rs1, 0*/
- gen_jalr(env, ctx, OPC_RISC_JALR, 1, rd, 0);
- } else {
- /* C.ADD -> add rd, rd, rs2 */
- gen_arith(ctx, OPC_RISC_ADD, rd, rd, rs2);
- }
- }
- }
- break;
- case 5:
- /* C.FSDSP -> fsd rs2, offset[8:3](x2)*/
- gen_fp_store(ctx, OPC_RISC_FSD, 2, GET_C_RS2(ctx->opcode),
- GET_C_SDSP_IMM(ctx->opcode));
- /* C.SQSP */
- break;
- case 6: /* C.SWSP -> sw rs2, offset[7:2](x2)*/
- gen_store(ctx, OPC_RISC_SW, 2, GET_C_RS2(ctx->opcode),
- GET_C_SWSP_IMM(ctx->opcode));
- break;
- case 7:
-#if defined(TARGET_RISCV64)
- /* C.SDSP(Rv64/128) -> sd rs2, offset[8:3](x2)*/
- gen_store(ctx, OPC_RISC_SD, 2, GET_C_RS2(ctx->opcode),
- GET_C_SDSP_IMM(ctx->opcode));
-#else
- /* C.FSWSP(RV32) -> fsw rs2, offset[7:2](x2) */
- gen_fp_store(ctx, OPC_RISC_FSW, 2, GET_C_RS2(ctx->opcode),
- GET_C_SWSP_IMM(ctx->opcode));
-#endif
- break;
- }
-}
-
-static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
-{
- uint8_t op = extract32(ctx->opcode, 0, 2);
-
- switch (op) {
- case 2:
- decode_RV32_64C2(env, ctx);
- break;
- }
-}
-
#define EX_SH(amount) \
static int32_t ex_shift_##amount(int imm) \
{ \
@@ -869,8 +721,7 @@ static void decode_opc(DisasContext *ctx)
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 2;
if (!decode_insn16(ctx, ctx->opcode)) {
- /* fall back to old decoder */
- decode_RV32_64C(ctx->env, ctx);
+ gen_exception_illegal(ctx);
}
}
} else {
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 19/29] target/riscv: Remove gen_jalr()
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (17 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 18/29] target/riscv: Convert quadrant 2 " Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 20/29] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
` (10 subsequent siblings)
29 siblings, 0 replies; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
trans_jalr() is the only caller, so move the code into trans_jalr().
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn_trans/trans_rvi.inc.c | 28 +++++++++++++++++-
target/riscv/translate.c | 38 -------------------------
2 files changed, 27 insertions(+), 39 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 5d0b4627ae..69dceccb1a 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -42,7 +42,33 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a, uint32_t insn)
static bool trans_jalr(DisasContext *ctx, arg_jalr *a, uint32_t insn)
{
- gen_jalr(ctx->env, ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm);
+ /* no chaining with JALR */
+ TCGLabel *misaligned = NULL;
+ TCGv t0 = tcg_temp_new();
+
+
+ gen_get_gpr(cpu_pc, a->rs1);
+ tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
+ tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
+
+ if (!riscv_has_ext(ctx->env, RVC)) {
+ misaligned = gen_new_label();
+ tcg_gen_andi_tl(t0, cpu_pc, 0x2);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
+ }
+
+ if (a->rd != 0) {
+ tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
+ }
+ tcg_gen_lookup_and_goto_ptr();
+
+ if (misaligned) {
+ gen_set_label(misaligned);
+ gen_exception_inst_addr_mis(ctx);
+ }
+ ctx->base.is_jmp = DISAS_NORETURN;
+
+ tcg_temp_free(t0);
return true;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 4f241a5e1e..9161a58893 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -489,44 +489,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
- int rd, int rs1, target_long imm)
-{
- /* no chaining with JALR */
- TCGLabel *misaligned = NULL;
- TCGv t0 = tcg_temp_new();
-
- switch (opc) {
- case OPC_RISC_JALR:
- gen_get_gpr(cpu_pc, rs1);
- tcg_gen_addi_tl(cpu_pc, cpu_pc, imm);
- tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
-
- if (!riscv_has_ext(env, RVC)) {
- misaligned = gen_new_label();
- tcg_gen_andi_tl(t0, cpu_pc, 0x2);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
- }
-
- if (rd != 0) {
- tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
- }
- tcg_gen_lookup_and_goto_ptr();
-
- if (misaligned) {
- gen_set_label(misaligned);
- gen_exception_inst_addr_mis(ctx);
- }
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
-
- default:
- gen_exception_illegal(ctx);
- break;
- }
- tcg_temp_free(t0);
-}
-
static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
int rs1, int rs2, target_long bimm)
{
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 20/29] target/riscv: Remove manual decoding from gen_branch()
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (18 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 19/29] target/riscv: Remove gen_jalr() Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 21/29] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
` (9 subsequent siblings)
29 siblings, 0 replies; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
We now utilizes argument-sets of decodetree such that no manual
decoding is necessary.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v1 -> v2:
- trans_branch -> gen_branch
target/riscv/insn_trans/trans_rvi.inc.c | 46 +++++++++++++++++-------
target/riscv/translate.c | 47 -------------------------
2 files changed, 33 insertions(+), 60 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 69dceccb1a..411b4bfd42 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -72,41 +72,61 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a, uint32_t insn)
return true;
}
-static bool trans_beq(DisasContext *ctx, arg_beq *a, uint32_t insn)
+static bool gen_branch(DisasContext *ctx, arg_branch *a, TCGCond cond)
{
- gen_branch(ctx->env, ctx, OPC_RISC_BEQ, a->rs1, a->rs2, a->imm);
+ TCGLabel *l = gen_new_label();
+ TCGv source1, source2;
+ source1 = tcg_temp_new();
+ source2 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_brcond_tl(cond, source1, source2, l);
+ gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
+ gen_set_label(l); /* branch taken */
+
+ if (!riscv_has_ext(ctx->env, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
+ /* misaligned */
+ gen_exception_inst_addr_mis(ctx);
+ } else {
+ gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
+ }
+ ctx->base.is_jmp = DISAS_NORETURN;
+
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+
return true;
}
+static bool trans_beq(DisasContext *ctx, arg_beq *a, uint32_t insn)
+{
+ return gen_branch(ctx, a, TCG_COND_EQ);
+}
+
static bool trans_bne(DisasContext *ctx, arg_bne *a, uint32_t insn)
{
- gen_branch(ctx->env, ctx, OPC_RISC_BNE, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_branch(ctx, a, TCG_COND_NE);
}
static bool trans_blt(DisasContext *ctx, arg_blt *a, uint32_t insn)
{
- gen_branch(ctx->env, ctx, OPC_RISC_BLT, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_branch(ctx, a, TCG_COND_LT);
}
static bool trans_bge(DisasContext *ctx, arg_bge *a, uint32_t insn)
{
- gen_branch(ctx->env, ctx, OPC_RISC_BGE, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_branch(ctx, a, TCG_COND_GE);
}
static bool trans_bltu(DisasContext *ctx, arg_bltu *a, uint32_t insn)
{
- gen_branch(ctx->env, ctx, OPC_RISC_BLTU, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_branch(ctx, a, TCG_COND_LTU);
}
static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a, uint32_t insn)
{
-
- gen_branch(ctx->env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_branch(ctx, a, TCG_COND_GEU);
}
static bool trans_lb(DisasContext *ctx, arg_lb *a, uint32_t insn)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9161a58893..52dbbd8ac8 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -489,53 +489,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
- int rs1, int rs2, target_long bimm)
-{
- TCGLabel *l = gen_new_label();
- TCGv source1, source2;
- source1 = tcg_temp_new();
- source2 = tcg_temp_new();
- gen_get_gpr(source1, rs1);
- gen_get_gpr(source2, rs2);
-
- switch (opc) {
- case OPC_RISC_BEQ:
- tcg_gen_brcond_tl(TCG_COND_EQ, source1, source2, l);
- break;
- case OPC_RISC_BNE:
- tcg_gen_brcond_tl(TCG_COND_NE, source1, source2, l);
- break;
- case OPC_RISC_BLT:
- tcg_gen_brcond_tl(TCG_COND_LT, source1, source2, l);
- break;
- case OPC_RISC_BGE:
- tcg_gen_brcond_tl(TCG_COND_GE, source1, source2, l);
- break;
- case OPC_RISC_BLTU:
- tcg_gen_brcond_tl(TCG_COND_LTU, source1, source2, l);
- break;
- case OPC_RISC_BGEU:
- tcg_gen_brcond_tl(TCG_COND_GEU, source1, source2, l);
- break;
- default:
- gen_exception_illegal(ctx);
- return;
- }
- tcg_temp_free(source1);
- tcg_temp_free(source2);
-
- gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
- gen_set_label(l); /* branch taken */
- if (!riscv_has_ext(env, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) {
- /* misaligned */
- gen_exception_inst_addr_mis(ctx);
- } else {
- gen_goto_tb(ctx, 0, ctx->base.pc_next + bimm);
- }
- ctx->base.is_jmp = DISAS_NORETURN;
-}
-
static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
target_long imm)
{
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 21/29] target/riscv: Remove manual decoding from gen_load()
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (19 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 20/29] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 22/29] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
` (8 subsequent siblings)
29 siblings, 0 replies; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_load() did.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v1 -> v2:
- trans_load -> gen_load
- removed negative memop check
target/riscv/insn_trans/trans_rvi.inc.c | 35 +++++++++++++++----------
target/riscv/translate.c | 20 --------------
2 files changed, 21 insertions(+), 34 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 411b4bfd42..77fa66b7cd 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -129,41 +129,49 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a, uint32_t insn)
return gen_branch(ctx, a, TCG_COND_GEU);
}
+static bool gen_load(DisasContext *ctx, arg_lb *a, int memop)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ return true;
+}
+
static bool trans_lb(DisasContext *ctx, arg_lb *a, uint32_t insn)
{
- gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_SB);
}
static bool trans_lh(DisasContext *ctx, arg_lh *a, uint32_t insn)
{
- gen_load(ctx, OPC_RISC_LH, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_TESW);
}
static bool trans_lw(DisasContext *ctx, arg_lw *a, uint32_t insn)
{
- gen_load(ctx, OPC_RISC_LW, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_TESL);
}
static bool trans_lbu(DisasContext *ctx, arg_lbu *a, uint32_t insn)
{
- gen_load(ctx, OPC_RISC_LBU, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_UB);
}
static bool trans_lhu(DisasContext *ctx, arg_lhu *a, uint32_t insn)
{
- gen_load(ctx, OPC_RISC_LHU, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_TEUW);
}
static bool trans_lwu(DisasContext *ctx, arg_lwu *a, uint32_t insn)
{
#ifdef TARGET_RISCV64
- gen_load(ctx, OPC_RISC_LWU, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_TEUL);
#else
return false;
#endif
@@ -172,8 +180,7 @@ static bool trans_lwu(DisasContext *ctx, arg_lwu *a, uint32_t insn)
static bool trans_ld(DisasContext *ctx, arg_ld *a, uint32_t insn)
{
#ifdef TARGET_RISCV64
- gen_load(ctx, OPC_RISC_LD, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_TEQ);
#else
return false;
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 52dbbd8ac8..947fb9345b 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -489,26 +489,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
- target_long imm)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_addi_tl(t0, t0, imm);
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
- if (memop < 0) {
- gen_exception_illegal(ctx);
- return;
- }
-
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
- gen_set_gpr(rd, t1);
- tcg_temp_free(t0);
- tcg_temp_free(t1);
-}
-
static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
target_long imm)
{
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 22/29] target/riscv: Remove manual decoding from gen_store()
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (20 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 21/29] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
` (7 subsequent siblings)
29 siblings, 0 replies; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_store() did.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v1 -> v2:
- trans_store -> gen_store
- removed negative memop check
target/riscv/insn_trans/trans_rvi.inc.c | 27 ++++++++++++++------
target/riscv/translate.c | 34 -------------------------
2 files changed, 19 insertions(+), 42 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 77fa66b7cd..48cc50d35f 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -186,29 +186,40 @@ static bool trans_ld(DisasContext *ctx, arg_ld *a, uint32_t insn)
#endif
}
-static bool trans_sb(DisasContext *ctx, arg_sb *a, uint32_t insn)
+static bool gen_store(DisasContext *ctx, arg_sb *a, int memop)
{
- gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm);
+ TCGv t0 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_get_gpr(dat, a->rs2);
+
+ tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
+ tcg_temp_free(t0);
+ tcg_temp_free(dat);
return true;
}
+
+static bool trans_sb(DisasContext *ctx, arg_sb *a, uint32_t insn)
+{
+ return gen_store(ctx, a, MO_SB);
+}
+
static bool trans_sh(DisasContext *ctx, arg_sh *a, uint32_t insn)
{
- gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_store(ctx, a, MO_TESW);
}
static bool trans_sw(DisasContext *ctx, arg_sw *a, uint32_t insn)
{
- gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_store(ctx, a, MO_TESL);
}
static bool trans_sd(DisasContext *ctx, arg_sd *a, uint32_t insn)
{
#ifdef TARGET_RISCV64
- gen_store(ctx, OPC_RISC_SD, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_store(ctx, a, MO_TEQ);
#else
return false;
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 947fb9345b..a8dbd00b99 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -55,20 +55,6 @@ typedef struct DisasContext {
CPURISCVState *env;
} DisasContext;
-/* convert riscv funct3 to qemu memop for load/store */
-static const int tcg_memop_lookup[8] = {
- [0 ... 7] = -1,
- [0] = MO_SB,
- [1] = MO_TESW,
- [2] = MO_TESL,
- [4] = MO_UB,
- [5] = MO_TEUW,
-#ifdef TARGET_RISCV64
- [3] = MO_TEQ,
- [6] = MO_TEUL,
-#endif
-};
-
#ifdef TARGET_RISCV64
#define CASE_OP_32_64(X) case X: case glue(X, W)
#else
@@ -489,26 +475,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
- target_long imm)
-{
- TCGv t0 = tcg_temp_new();
- TCGv dat = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_addi_tl(t0, t0, imm);
- gen_get_gpr(dat, rs2);
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
- if (memop < 0) {
- gen_exception_illegal(ctx);
- return;
- }
-
- tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
- tcg_temp_free(t0);
- tcg_temp_free(dat);
-}
-
static void gen_set_rm(DisasContext *ctx, int rm)
{
TCGv_i32 t0;
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (21 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 22/29] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-23 8:46 ` Richard Henderson
2018-10-24 9:07 ` Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
` (6 subsequent siblings)
29 siblings, 2 replies; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
gen_arith_imm() does a lot of decoding manually, which was hard to read in
case of the shift instructions and is not necessary anymore with decodetree.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v1 -> v2:
- trans_arith_imm -> gen_arith_imm
- Add missing TARGET_RISC64 checks
- Reimplement shift translators that were omited in [0004/0028]
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvi.inc.c | 111 ++++++++++++++++++++----
target/riscv/translate.c | 99 ++++-----------------
3 files changed, 113 insertions(+), 100 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index ffb4f00274..7c045d354c 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -39,13 +39,14 @@
# Argument sets:
&branch imm rs2 rs1
+&arith_imm imm rs1 rd
&shift shamt rs1 rd
&atomic aq rl rs2 rs1 rd
# Formats 32:
@r ....... ..... ..... ... ..... ....... %rs2 %rs1 %rd
-@i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd
+@i ............ ..... ... ..... ....... &arith_imm imm=%imm_i %rs1 %rd
@b ....... ..... ..... ... ..... ....... &branch imm=%imm_b %rs2 %rs1
@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1
@u .................... ..... ....... imm=%imm_u %rd
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 48cc50d35f..c82606f058 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -227,52 +227,89 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a, uint32_t insn)
static bool trans_addi(DisasContext *ctx, arg_addi *a, uint32_t insn)
{
- gen_arith_imm(ctx, OPC_RISC_ADDI, a->rd, a->rs1, a->imm);
- return true;
+ return gen_arith_imm(ctx, a, &tcg_gen_add_tl);
}
static bool trans_slti(DisasContext *ctx, arg_slti *a, uint32_t insn)
{
- gen_arith_imm(ctx, OPC_RISC_SLTI, a->rd, a->rs1, a->imm);
+ TCGv source1;
+ source1 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+
+ tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, a->imm);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
return true;
}
static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a, uint32_t insn)
{
- gen_arith_imm(ctx, OPC_RISC_SLTIU, a->rd, a->rs1, a->imm);
+ TCGv source1;
+ source1 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+
+ tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, a->imm);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
return true;
}
static bool trans_xori(DisasContext *ctx, arg_xori *a, uint32_t insn)
{
- gen_arith_imm(ctx, OPC_RISC_XORI, a->rd, a->rs1, a->imm);
- return true;
+ return gen_arith_imm(ctx, a, &tcg_gen_xor_tl);
}
+
static bool trans_ori(DisasContext *ctx, arg_ori *a, uint32_t insn)
{
- gen_arith_imm(ctx, OPC_RISC_ORI, a->rd, a->rs1, a->imm);
- return true;
+ return gen_arith_imm(ctx, a, &tcg_gen_or_tl);
}
+
static bool trans_andi(DisasContext *ctx, arg_andi *a, uint32_t insn)
{
- gen_arith_imm(ctx, OPC_RISC_ANDI, a->rd, a->rs1, a->imm);
- return true;
+ return gen_arith_imm(ctx, a, &tcg_gen_and_tl);
}
+
static bool trans_slli(DisasContext *ctx, arg_slli *a, uint32_t insn)
{
- gen_arith_imm(ctx, OPC_RISC_SLLI, a->rd, a->rs1, a->shamt);
+ if (a->rd != 0) {
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+
+ if (a->shamt >= TARGET_LONG_BITS) {
+ gen_exception_illegal(ctx);
+ return true;
+ }
+ tcg_gen_shli_tl(t, t, a->shamt);
+
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ } /* NOP otherwise */
return true;
}
static bool trans_srli(DisasContext *ctx, arg_srli *a, uint32_t insn)
{
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt);
+ if (a->rd != 0) {
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+ tcg_gen_extract_tl(t, t, a->shamt, 64 - a->shamt);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ } /* NOP otherwise */
return true;
}
static bool trans_srai(DisasContext *ctx, arg_srai *a, uint32_t insn)
{
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt | 0x400);
+ if (a->rd != 0) {
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+ tcg_gen_sextract_tl(t, t, a->shamt, 64 - a->shamt);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ } /* NOP otherwise */
return true;
}
@@ -338,27 +375,63 @@ static bool trans_and(DisasContext *ctx, arg_and *a, uint32_t insn)
static bool trans_addiw(DisasContext *ctx, arg_addiw *a, uint32_t insn)
{
- gen_arith_imm(ctx, OPC_RISC_ADDIW, a->rd, a->rs1, a->imm);
- return true;
+#ifdef TARGET_RISCV64
+ bool res = gen_arith_imm(ctx, a, &tcg_gen_add_tl);
+ tcg_gen_ext32s_tl(cpu_gpr[a->rd], cpu_gpr[a->rd]);
+ return res;
+#else
+ return false;
+#endif
}
static bool trans_slliw(DisasContext *ctx, arg_slliw *a, uint32_t insn)
{
- gen_arith_imm(ctx, OPC_RISC_SLLIW, a->rd, a->rs1, a->shamt);
+#ifdef TARGET_RISCV64
+ TCGv source1;
+ source1 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+
+ tcg_gen_shli_tl(source1, source1, a->shamt);
+ tcg_gen_ext32s_tl(source1, source1);
+ gen_set_gpr(a->rd, source1);
+
+ tcg_temp_free(source1);
return true;
+#else
+ return false;
+#endif
}
static bool trans_srliw(DisasContext *ctx, arg_srliw *a, uint32_t insn)
{
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW, a->rd, a->rs1, a->shamt);
+#ifdef TARGET_RISCV64
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+ tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt);
+ /* sign-extend for W instructions */
+ tcg_gen_ext32s_tl(t, t);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
return true;
+#else
+ return false;
+#endif
}
static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a, uint32_t insn)
{
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW , a->rd, a->rs1,
- a->shamt | 0x400);
+#ifdef TARGET_RISCV64
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+ tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt);
+ /* sign-extend for W instructions */
+ tcg_gen_ext32s_tl(t, t);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
return true;
+#else
+ return false;
+#endif
}
static bool trans_addw(DisasContext *ctx, arg_addw *a, uint32_t insn)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a8dbd00b99..dfd401fe74 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -374,86 +374,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_temp_free(source2);
}
-static void gen_arith_imm(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, target_long imm)
-{
- TCGv source1 = tcg_temp_new();
- int shift_len = TARGET_LONG_BITS;
- int shift_a;
-
- gen_get_gpr(source1, rs1);
-
- switch (opc) {
- case OPC_RISC_ADDI:
-#if defined(TARGET_RISCV64)
- case OPC_RISC_ADDIW:
-#endif
- tcg_gen_addi_tl(source1, source1, imm);
- break;
- case OPC_RISC_SLTI:
- tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, imm);
- break;
- case OPC_RISC_SLTIU:
- tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, imm);
- break;
- case OPC_RISC_XORI:
- tcg_gen_xori_tl(source1, source1, imm);
- break;
- case OPC_RISC_ORI:
- tcg_gen_ori_tl(source1, source1, imm);
- break;
- case OPC_RISC_ANDI:
- tcg_gen_andi_tl(source1, source1, imm);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SLLIW:
- shift_len = 32;
- /* FALLTHRU */
-#endif
- case OPC_RISC_SLLI:
- if (imm >= shift_len) {
- goto do_illegal;
- }
- tcg_gen_shli_tl(source1, source1, imm);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SHIFT_RIGHT_IW:
- shift_len = 32;
- /* FALLTHRU */
-#endif
- case OPC_RISC_SHIFT_RIGHT_I:
- /* differentiate on IMM */
- shift_a = imm & 0x400;
- imm &= 0x3ff;
- if (imm >= shift_len) {
- goto do_illegal;
- }
- if (imm != 0) {
- if (shift_a) {
- /* SRAI[W] */
- tcg_gen_sextract_tl(source1, source1, imm, shift_len - imm);
- } else {
- /* SRLI[W] */
- tcg_gen_extract_tl(source1, source1, imm, shift_len - imm);
- }
- /* No further sign-extension needed for W instructions. */
- opc &= ~0x8;
- }
- break;
- default:
- do_illegal:
- gen_exception_illegal(ctx);
- return;
- }
-
- if (opc & 0x8) { /* sign-extend for W instructions */
- tcg_gen_ext32s_tl(source1, source1);
- }
-
- gen_set_gpr(rd, source1);
- tcg_temp_free(source1);
-}
-
static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
target_ulong imm)
{
@@ -535,6 +455,25 @@ static int ex_rvc_register(int reg)
bool decode_insn32(DisasContext *ctx, uint32_t insn);
/* Include the auto-generated decoder for 32 bit insn */
#include "decode_insn32.inc.c"
+
+static bool gen_arith_imm(DisasContext *ctx, arg_arith_imm *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1, source2;
+ source1 = tcg_temp_new();
+ source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ tcg_gen_movi_tl(source2, a->imm);
+
+ (*func)(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (22 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-23 8:53 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 25/29] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
` (5 subsequent siblings)
29 siblings, 1 reply; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
manual decoding in gen_arith() is not necessary with decodetree. For now
the function is called trans_arith as the original gen_arith still
exisits. The former will be renamed to gen_arith as soon as the old
gen_arith can be removed.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32.decode | 3 ++-
target/riscv/insn_trans/trans_rvi.inc.c | 21 ++++++----------
target/riscv/translate.c | 33 ++++++++++++++-----------
3 files changed, 27 insertions(+), 30 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 7c045d354c..1541c254df 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -40,12 +40,13 @@
# Argument sets:
&branch imm rs2 rs1
&arith_imm imm rs1 rd
+&arith rd rs1 rs2
&shift shamt rs1 rd
&atomic aq rl rs2 rs1 rd
# Formats 32:
-@r ....... ..... ..... ... ..... ....... %rs2 %rs1 %rd
+@r ....... ..... ..... ... ..... ....... &arith %rs2 %rs1 %rd
@i ............ ..... ... ..... ....... &arith_imm imm=%imm_i %rs1 %rd
@b ....... ..... ..... ... ..... ....... &branch imm=%imm_b %rs2 %rs1
@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index c82606f058..c4a928705a 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -315,14 +315,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a, uint32_t insn)
static bool trans_add(DisasContext *ctx, arg_add *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_ADD, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_add_tl);
}
static bool trans_sub(DisasContext *ctx, arg_sub *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_SUB, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_sub_tl);
}
static bool trans_sll(DisasContext *ctx, arg_sll *a, uint32_t insn)
@@ -345,8 +343,7 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a, uint32_t insn)
static bool trans_xor(DisasContext *ctx, arg_xor *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_XOR, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_xor_tl);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a, uint32_t insn)
@@ -363,14 +360,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a, uint32_t insn)
static bool trans_or(DisasContext *ctx, arg_or *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_OR, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_or_tl);
}
static bool trans_and(DisasContext *ctx, arg_and *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_AND, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_and_tl);
}
static bool trans_addiw(DisasContext *ctx, arg_addiw *a, uint32_t insn)
@@ -439,8 +434,7 @@ static bool trans_addw(DisasContext *ctx, arg_addw *a, uint32_t insn)
#if !defined(TARGET_RISCV64)
return false;
#endif
- gen_arith(ctx, OPC_RISC_ADDW, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_add_tl);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a, uint32_t insn)
@@ -448,8 +442,7 @@ static bool trans_subw(DisasContext *ctx, arg_subw *a, uint32_t insn)
#if !defined(TARGET_RISCV64)
return false;
#endif
- gen_arith(ctx, OPC_RISC_SUBW, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_sub_tl);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a, uint32_t insn)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index dfd401fe74..fc1ed73784 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -176,12 +176,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
gen_get_gpr(source2, rs2);
switch (opc) {
- CASE_OP_32_64(OPC_RISC_ADD):
- tcg_gen_add_tl(source1, source1, source2);
- break;
- CASE_OP_32_64(OPC_RISC_SUB):
- tcg_gen_sub_tl(source1, source1, source2);
- break;
#if defined(TARGET_RISCV64)
case OPC_RISC_SLLW:
tcg_gen_andi_tl(source2, source2, 0x1F);
@@ -198,9 +192,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
case OPC_RISC_SLTU:
tcg_gen_setcond_tl(TCG_COND_LTU, source1, source1, source2);
break;
- case OPC_RISC_XOR:
- tcg_gen_xor_tl(source1, source1, source2);
- break;
#if defined(TARGET_RISCV64)
case OPC_RISC_SRLW:
/* clear upper 32 */
@@ -226,12 +217,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
tcg_gen_sar_tl(source1, source1, source2);
break;
- case OPC_RISC_OR:
- tcg_gen_or_tl(source1, source1, source2);
- break;
- case OPC_RISC_AND:
- tcg_gen_and_tl(source1, source1, source2);
- break;
CASE_OP_32_64(OPC_RISC_MUL):
tcg_gen_mul_tl(source1, source1, source2);
break;
@@ -474,6 +459,24 @@ static bool gen_arith_imm(DisasContext *ctx, arg_arith_imm *a,
return true;
}
+static bool trans_arith(DisasContext *ctx, arg_arith *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1, source2;
+ source1 = tcg_temp_new();
+ source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ (*func)(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 25/29] target/riscv: Remove shift and slt insn manual decoding
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (23 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 26/29] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
` (4 subsequent siblings)
29 siblings, 0 replies; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v1 -> v2:
- trans_shift -> gen_shift
target/riscv/insn_trans/trans_rvi.inc.c | 79 +++++++++++++++++++++----
target/riscv/translate.c | 59 ++++++------------
2 files changed, 86 insertions(+), 52 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index c4a928705a..5ece5e2f6a 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -325,19 +325,39 @@ static bool trans_sub(DisasContext *ctx, arg_sub *a, uint32_t insn)
static bool trans_sll(DisasContext *ctx, arg_sll *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_SLL, a->rd, a->rs1, a->rs2);
- return true;
+
+ return gen_shift(ctx, a, &tcg_gen_shl_tl);
}
static bool trans_slt(DisasContext *ctx, arg_slt *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_SLT, a->rd, a->rs1, a->rs2);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_setcond_tl(TCG_COND_LT, source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
return true;
}
static bool trans_sltu(DisasContext *ctx, arg_sltu *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_SLTU, a->rd, a->rs1, a->rs2);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_setcond_tl(TCG_COND_LTU, source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
return true;
}
@@ -346,16 +366,15 @@ static bool trans_xor(DisasContext *ctx, arg_xor *a, uint32_t insn)
return trans_arith(ctx, a, &tcg_gen_xor_tl);
}
+
static bool trans_srl(DisasContext *ctx, arg_srl *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_SRL, a->rd, a->rs1, a->rs2);
- return true;
+ return gen_shift(ctx, a, &tcg_gen_shr_tl);
}
static bool trans_sra(DisasContext *ctx, arg_sra *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_SRA, a->rd, a->rs1, a->rs2);
- return true;
+ return gen_shift(ctx, a, &tcg_gen_sar_tl);
}
static bool trans_or(DisasContext *ctx, arg_or *a, uint32_t insn)
@@ -450,7 +469,18 @@ static bool trans_sllw(DisasContext *ctx, arg_sllw *a, uint32_t insn)
#if !defined(TARGET_RISCV64)
return false;
#endif
- gen_arith(ctx, OPC_RISC_SLLW, a->rd, a->rs1, a->rs2);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_andi_tl(source2, source2, 0x1F);
+ tcg_gen_shl_tl(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
return true;
}
@@ -459,7 +489,20 @@ static bool trans_srlw(DisasContext *ctx, arg_srlw *a, uint32_t insn)
#if !defined(TARGET_RISCV64)
return false;
#endif
- gen_arith(ctx, OPC_RISC_SRLW, a->rd, a->rs1, a->rs2);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ /* clear upper 32 */
+ tcg_gen_ext32u_tl(source1, source1);
+ tcg_gen_andi_tl(source2, source2, 0x1F);
+ tcg_gen_shr_tl(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
return true;
}
@@ -468,7 +511,21 @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a, uint32_t insn)
#if !defined(TARGET_RISCV64)
return false;
#endif
- gen_arith(ctx, OPC_RISC_SRAW, a->rd, a->rs1, a->rs2);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ /* first, trick to get it to act like working on 32 bits (get rid of
+ upper 32, sign extend to fill space) */
+ tcg_gen_ext32s_tl(source1, source1);
+ tcg_gen_andi_tl(source2, source2, 0x1F);
+ tcg_gen_sar_tl(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
return true;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index fc1ed73784..d85c21ee91 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -176,47 +176,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
gen_get_gpr(source2, rs2);
switch (opc) {
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SLLW:
- tcg_gen_andi_tl(source2, source2, 0x1F);
- tcg_gen_shl_tl(source1, source1, source2);
- break;
-#endif
- case OPC_RISC_SLL:
- tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
- tcg_gen_shl_tl(source1, source1, source2);
- break;
- case OPC_RISC_SLT:
- tcg_gen_setcond_tl(TCG_COND_LT, source1, source1, source2);
- break;
- case OPC_RISC_SLTU:
- tcg_gen_setcond_tl(TCG_COND_LTU, source1, source1, source2);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SRLW:
- /* clear upper 32 */
- tcg_gen_ext32u_tl(source1, source1);
- tcg_gen_andi_tl(source2, source2, 0x1F);
- tcg_gen_shr_tl(source1, source1, source2);
- break;
-#endif
- case OPC_RISC_SRL:
- tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
- tcg_gen_shr_tl(source1, source1, source2);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SRAW:
- /* first, trick to get it to act like working on 32 bits (get rid of
- upper 32, sign extend to fill space) */
- tcg_gen_ext32s_tl(source1, source1);
- tcg_gen_andi_tl(source2, source2, 0x1F);
- tcg_gen_sar_tl(source1, source1, source2);
- break;
-#endif
- case OPC_RISC_SRA:
- tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
- tcg_gen_sar_tl(source1, source1, source2);
- break;
CASE_OP_32_64(OPC_RISC_MUL):
tcg_gen_mul_tl(source1, source1, source2);
break;
@@ -477,6 +436,24 @@ static bool trans_arith(DisasContext *ctx, arg_arith *a,
return true;
}
+static bool gen_shift(DisasContext *ctx, arg_arith *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
+ (*func)(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 26/29] target/riscv: Remove manual decoding of RV32/64M insn
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (24 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 25/29] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-23 9:02 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 27/29] target/riscv: Remove gen_system() Bastian Koppelmann
` (3 subsequent siblings)
29 siblings, 1 reply; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v1 -> v2:
- Add missing TARGET_RISCV64 conditions
- trans_arith_w -> gen_arith_w
target/riscv/insn_trans/trans_rvm.inc.c | 75 ++++---
target/riscv/translate.c | 268 +++++++++++-------------
2 files changed, 173 insertions(+), 170 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_trans/trans_rvm.inc.c
index ffeae57a36..93859745b8 100644
--- a/target/riscv/insn_trans/trans_rvm.inc.c
+++ b/target/riscv/insn_trans/trans_rvm.inc.c
@@ -21,78 +21,105 @@
static bool trans_mul(DisasContext *ctx, arg_mul *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_MUL, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_mul_tl);
}
static bool trans_mulh(DisasContext *ctx, arg_mulh *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_MULH, a->rd, a->rs1, a->rs2);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_muls2_tl(source2, source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
return true;
}
static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_MULHSU, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_mulhsu);
}
static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_MULHU, a->rd, a->rs1, a->rs2);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_mulu2_tl(source2, source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
return true;
}
static bool trans_div(DisasContext *ctx, arg_div *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_DIV, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_div);
}
static bool trans_divu(DisasContext *ctx, arg_divu *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_DIVU, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_divu);
}
static bool trans_rem(DisasContext *ctx, arg_rem *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_REM, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_rem);
}
static bool trans_remu(DisasContext *ctx, arg_remu *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_REMU, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_remu);
}
static bool trans_mulw(DisasContext *ctx, arg_mulw *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_MULW, a->rd, a->rs1, a->rs2);
- return true;
+#ifdef TARGET_RISCV64
+ return trans_arith(ctx, a, &tcg_gen_mul_tl);
+#else
+ return false;
+#endif
}
static bool trans_divw(DisasContext *ctx, arg_divw *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_DIVW, a->rd, a->rs1, a->rs2);
- return true;
+#ifdef TARGET_RISCV64
+ return gen_arith_w(ctx, a, &gen_div);
+#else
+ return false;
+#endif
}
static bool trans_divuw(DisasContext *ctx, arg_divuw *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_DIVUW, a->rd, a->rs1, a->rs2);
- return true;
+#ifdef TARGET_RISCV64
+ return gen_arith_w(ctx, a, &gen_divu);
+#else
+ return false;
+#endif
}
static bool trans_remw(DisasContext *ctx, arg_remw *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_REMW, a->rd, a->rs1, a->rs2);
- return true;
+#ifdef TARGET_RISCV64
+ return gen_arith_w(ctx, a, &gen_rem);
+#else
+ return false;
+#endif
}
static bool trans_remuw(DisasContext *ctx, arg_remuw *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_REMUW, a->rd, a->rs1, a->rs2);
- return true;
+#ifdef TARGET_RISCV64
+ return gen_arith_w(ctx, a, &gen_remu);
+#else
+ return false;
+#endif
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d85c21ee91..b542daf844 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -166,156 +166,110 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free(rh);
}
-static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
- int rs2)
+static void gen_div(TCGv ret, TCGv source1, TCGv source2)
{
- TCGv source1, source2, cond1, cond2, zeroreg, resultopt1;
- source1 = tcg_temp_new();
- source2 = tcg_temp_new();
- gen_get_gpr(source1, rs1);
- gen_get_gpr(source2, rs2);
+ TCGv cond1, cond2, zeroreg, resultopt1;
+ /* Handle by altering args to tcg_gen_div to produce req'd results:
+ * For overflow: want source1 in source1 and 1 in source2
+ * For div by zero: want -1 in source1 and 1 in source2 -> -1 result */
+ cond1 = tcg_temp_new();
+ cond2 = tcg_temp_new();
+ zeroreg = tcg_const_tl(0);
+ resultopt1 = tcg_temp_new();
+
+ tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L));
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
+ ((target_ulong)1) << (TARGET_LONG_BITS - 1));
+ tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */
+ /* if div by zero, set source1 to -1, otherwise don't change */
+ tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1,
+ resultopt1);
+ /* if overflow or div by zero, set source2 to 1, else don't change */
+ tcg_gen_or_tl(cond1, cond1, cond2);
+ tcg_gen_movi_tl(resultopt1, (target_ulong)1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
+ resultopt1);
+ tcg_gen_div_tl(ret, source1, source2);
+
+ tcg_temp_free(cond1);
+ tcg_temp_free(cond2);
+ tcg_temp_free(zeroreg);
+ tcg_temp_free(resultopt1);
+}
- switch (opc) {
- CASE_OP_32_64(OPC_RISC_MUL):
- tcg_gen_mul_tl(source1, source1, source2);
- break;
- case OPC_RISC_MULH:
- tcg_gen_muls2_tl(source2, source1, source1, source2);
- break;
- case OPC_RISC_MULHSU:
- gen_mulhsu(source1, source1, source2);
- break;
- case OPC_RISC_MULHU:
- tcg_gen_mulu2_tl(source2, source1, source1, source2);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_DIVW:
- tcg_gen_ext32s_tl(source1, source1);
- tcg_gen_ext32s_tl(source2, source2);
- /* fall through to DIV */
-#endif
- case OPC_RISC_DIV:
- /* Handle by altering args to tcg_gen_div to produce req'd results:
- * For overflow: want source1 in source1 and 1 in source2
- * For div by zero: want -1 in source1 and 1 in source2 -> -1 result */
- cond1 = tcg_temp_new();
- cond2 = tcg_temp_new();
- zeroreg = tcg_const_tl(0);
- resultopt1 = tcg_temp_new();
-
- tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L));
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
- ((target_ulong)1) << (TARGET_LONG_BITS - 1));
- tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */
- /* if div by zero, set source1 to -1, otherwise don't change */
- tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1,
- resultopt1);
- /* if overflow or div by zero, set source2 to 1, else don't change */
- tcg_gen_or_tl(cond1, cond1, cond2);
- tcg_gen_movi_tl(resultopt1, (target_ulong)1);
- tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
- resultopt1);
- tcg_gen_div_tl(source1, source1, source2);
-
- tcg_temp_free(cond1);
- tcg_temp_free(cond2);
- tcg_temp_free(zeroreg);
- tcg_temp_free(resultopt1);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_DIVUW:
- tcg_gen_ext32u_tl(source1, source1);
- tcg_gen_ext32u_tl(source2, source2);
- /* fall through to DIVU */
-#endif
- case OPC_RISC_DIVU:
- cond1 = tcg_temp_new();
- zeroreg = tcg_const_tl(0);
- resultopt1 = tcg_temp_new();
-
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
- tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
- tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1,
- resultopt1);
- tcg_gen_movi_tl(resultopt1, (target_ulong)1);
- tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
- resultopt1);
- tcg_gen_divu_tl(source1, source1, source2);
-
- tcg_temp_free(cond1);
- tcg_temp_free(zeroreg);
- tcg_temp_free(resultopt1);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_REMW:
- tcg_gen_ext32s_tl(source1, source1);
- tcg_gen_ext32s_tl(source2, source2);
- /* fall through to REM */
-#endif
- case OPC_RISC_REM:
- cond1 = tcg_temp_new();
- cond2 = tcg_temp_new();
- zeroreg = tcg_const_tl(0);
- resultopt1 = tcg_temp_new();
-
- tcg_gen_movi_tl(resultopt1, 1L);
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1);
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
- (target_ulong)1 << (TARGET_LONG_BITS - 1));
- tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */
- /* if overflow or div by zero, set source2 to 1, else don't change */
- tcg_gen_or_tl(cond2, cond1, cond2);
- tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2,
- resultopt1);
- tcg_gen_rem_tl(resultopt1, source1, source2);
- /* if div by zero, just return the original dividend */
- tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, resultopt1,
- source1);
-
- tcg_temp_free(cond1);
- tcg_temp_free(cond2);
- tcg_temp_free(zeroreg);
- tcg_temp_free(resultopt1);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_REMUW:
- tcg_gen_ext32u_tl(source1, source1);
- tcg_gen_ext32u_tl(source2, source2);
- /* fall through to REMU */
-#endif
- case OPC_RISC_REMU:
- cond1 = tcg_temp_new();
- zeroreg = tcg_const_tl(0);
- resultopt1 = tcg_temp_new();
-
- tcg_gen_movi_tl(resultopt1, (target_ulong)1);
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
- tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
- resultopt1);
- tcg_gen_remu_tl(resultopt1, source1, source2);
- /* if div by zero, just return the original dividend */
- tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, resultopt1,
- source1);
-
- tcg_temp_free(cond1);
- tcg_temp_free(zeroreg);
- tcg_temp_free(resultopt1);
- break;
- default:
- gen_exception_illegal(ctx);
- return;
- }
+static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
+{
+ TCGv cond1, zeroreg, resultopt1;
+ cond1 = tcg_temp_new();
+
+ zeroreg = tcg_const_tl(0);
+ resultopt1 = tcg_temp_new();
+
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
+ tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1,
+ resultopt1);
+ tcg_gen_movi_tl(resultopt1, (target_ulong)1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
+ resultopt1);
+ tcg_gen_divu_tl(ret, source1, source2);
+
+ tcg_temp_free(cond1);
+ tcg_temp_free(zeroreg);
+ tcg_temp_free(resultopt1);
+}
- if (opc & 0x8) { /* sign extend for W instructions */
- tcg_gen_ext32s_tl(source1, source1);
- }
+static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
+{
+ TCGv cond1, cond2, zeroreg, resultopt1;
+
+ cond1 = tcg_temp_new();
+ cond2 = tcg_temp_new();
+ zeroreg = tcg_const_tl(0);
+ resultopt1 = tcg_temp_new();
+
+ tcg_gen_movi_tl(resultopt1, 1L);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
+ (target_ulong)1 << (TARGET_LONG_BITS - 1));
+ tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */
+ /* if overflow or div by zero, set source2 to 1, else don't change */
+ tcg_gen_or_tl(cond2, cond1, cond2);
+ tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2,
+ resultopt1);
+ tcg_gen_rem_tl(resultopt1, source1, source2);
+ /* if div by zero, just return the original dividend */
+ tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
+ source1);
+
+ tcg_temp_free(cond1);
+ tcg_temp_free(cond2);
+ tcg_temp_free(zeroreg);
+ tcg_temp_free(resultopt1);
+}
- gen_set_gpr(rd, source1);
- tcg_temp_free(source1);
- tcg_temp_free(source2);
+static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
+{
+ TCGv cond1, zeroreg, resultopt1;
+ cond1 = tcg_temp_new();
+ zeroreg = tcg_const_tl(0);
+ resultopt1 = tcg_temp_new();
+
+ tcg_gen_movi_tl(resultopt1, (target_ulong)1);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
+ tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
+ resultopt1);
+ tcg_gen_remu_tl(resultopt1, source1, source2);
+ /* if div by zero, just return the original dividend */
+ tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
+ source1);
+
+ tcg_temp_free(cond1);
+ tcg_temp_free(zeroreg);
+ tcg_temp_free(resultopt1);
}
static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
@@ -436,6 +390,28 @@ static bool trans_arith(DisasContext *ctx, arg_arith *a,
return true;
}
+#ifdef TARGET_RISCV64
+static bool gen_arith_w(DisasContext *ctx, arg_arith *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1, source2;
+ source1 = tcg_temp_new();
+ source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+ tcg_gen_ext32s_tl(source1, source1);
+ tcg_gen_ext32s_tl(source2, source2);
+
+ (*func)(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+#endif
+
static bool gen_shift(DisasContext *ctx, arg_arith *a,
void(*func)(TCGv, TCGv, TCGv))
{
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 27/29] target/riscv: Remove gen_system()
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (25 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 26/29] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 28/29] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
` (2 subsequent siblings)
29 siblings, 0 replies; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/translate.c | 32 --------------------------------
1 file changed, 32 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b542daf844..a3b8792a1a 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -306,34 +306,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
tcg_temp_free_i32(t0);
}
-
-static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
- int rd, int rs1, int csr)
-{
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-
- switch (opc) {
- case OPC_RISC_ECALL:
- switch (csr) {
- case 0x0: /* ECALL */
- /* always generates U-level ECALL, fixed in do_interrupt handler */
- generate_exception(ctx, RISCV_EXCP_U_ECALL);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
- case 0x1: /* EBREAK */
- generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
- break;
- }
-}
-
#define EX_SH(amount) \
static int32_t ex_shift_##amount(int imm) \
{ \
@@ -458,10 +430,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
rd = GET_RD(ctx->opcode);
switch (op) {
- case OPC_RISC_SYSTEM:
- gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
- (ctx->opcode & 0xFFF00000) >> 20);
- break;
default:
gen_exception_illegal(ctx);
break;
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 28/29] target/riscv: Remove decode_RV32_64G()
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (26 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 27/29] target/riscv: Remove gen_system() Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-23 9:04 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 29/29] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
2018-10-24 22:21 ` [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Palmer Dabbelt
29 siblings, 1 reply; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
decodetree handles all instructions now so the fallback is not necessary
anymore.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v1 -> v2:
- Add missing gen_exception_illegal
target/riscv/translate.c | 24 +-----------------------
1 file changed, 1 insertion(+), 23 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a3b8792a1a..66241ecf33 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -415,27 +415,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn);
#include "decode_insn16.inc.c"
#include "insn_trans/trans_rvc.inc.c"
-static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
-{
- int rs1, rd;
- uint32_t op;
-
- /* We do not do misaligned address check here: the address should never be
- * misaligned at this point. Instructions that set PC must do the check,
- * since epc must be the address of the instruction that caused us to
- * perform the misaligned instruction fetch */
-
- op = MASK_OP_MAJOR(ctx->opcode);
- rs1 = GET_RS1(ctx->opcode);
- rd = GET_RD(ctx->opcode);
-
- switch (op) {
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
static void decode_opc(DisasContext *ctx)
{
/* check for compressed insn */
@@ -451,8 +430,7 @@ static void decode_opc(DisasContext *ctx)
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 4;
if (!decode_insn32(ctx, ctx->opcode)) {
- /* fallback to old decoder */
- decode_RV32_64G(ctx->env, ctx);
+ gen_exception_illegal(ctx);
}
}
}
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH v2 29/29] target/riscv: Rename trans_arith to gen_arith
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (27 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 28/29] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
@ 2018-10-20 7:14 ` Bastian Koppelmann
2018-10-23 9:04 ` Richard Henderson
2018-10-24 22:21 ` [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Palmer Dabbelt
29 siblings, 1 reply; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-20 7:14 UTC (permalink / raw)
To: mjc, sagark, palmer, kbastian
Cc: peer.adelt, Alistair.Francis, richard.henderson, qemu-devel
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/riscv/insn_trans/trans_rvi.inc.c | 14 +++++++-------
target/riscv/insn_trans/trans_rvm.inc.c | 14 +++++++-------
target/riscv/translate.c | 4 ++--
3 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 5ece5e2f6a..0455f0bf91 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -315,12 +315,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a, uint32_t insn)
static bool trans_add(DisasContext *ctx, arg_add *a, uint32_t insn)
{
- return trans_arith(ctx, a, &tcg_gen_add_tl);
+ return gen_arith(ctx, a, &tcg_gen_add_tl);
}
static bool trans_sub(DisasContext *ctx, arg_sub *a, uint32_t insn)
{
- return trans_arith(ctx, a, &tcg_gen_sub_tl);
+ return gen_arith(ctx, a, &tcg_gen_sub_tl);
}
static bool trans_sll(DisasContext *ctx, arg_sll *a, uint32_t insn)
@@ -363,7 +363,7 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a, uint32_t insn)
static bool trans_xor(DisasContext *ctx, arg_xor *a, uint32_t insn)
{
- return trans_arith(ctx, a, &tcg_gen_xor_tl);
+ return gen_arith(ctx, a, &tcg_gen_xor_tl);
}
@@ -379,12 +379,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a, uint32_t insn)
static bool trans_or(DisasContext *ctx, arg_or *a, uint32_t insn)
{
- return trans_arith(ctx, a, &tcg_gen_or_tl);
+ return gen_arith(ctx, a, &tcg_gen_or_tl);
}
static bool trans_and(DisasContext *ctx, arg_and *a, uint32_t insn)
{
- return trans_arith(ctx, a, &tcg_gen_and_tl);
+ return gen_arith(ctx, a, &tcg_gen_and_tl);
}
static bool trans_addiw(DisasContext *ctx, arg_addiw *a, uint32_t insn)
@@ -453,7 +453,7 @@ static bool trans_addw(DisasContext *ctx, arg_addw *a, uint32_t insn)
#if !defined(TARGET_RISCV64)
return false;
#endif
- return trans_arith(ctx, a, &tcg_gen_add_tl);
+ return gen_arith(ctx, a, &tcg_gen_add_tl);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a, uint32_t insn)
@@ -461,7 +461,7 @@ static bool trans_subw(DisasContext *ctx, arg_subw *a, uint32_t insn)
#if !defined(TARGET_RISCV64)
return false;
#endif
- return trans_arith(ctx, a, &tcg_gen_sub_tl);
+ return gen_arith(ctx, a, &tcg_gen_sub_tl);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a, uint32_t insn)
diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_trans/trans_rvm.inc.c
index 93859745b8..0bc9b4347a 100644
--- a/target/riscv/insn_trans/trans_rvm.inc.c
+++ b/target/riscv/insn_trans/trans_rvm.inc.c
@@ -21,7 +21,7 @@
static bool trans_mul(DisasContext *ctx, arg_mul *a, uint32_t insn)
{
- return trans_arith(ctx, a, &tcg_gen_mul_tl);
+ return gen_arith(ctx, a, &tcg_gen_mul_tl);
}
static bool trans_mulh(DisasContext *ctx, arg_mulh *a, uint32_t insn)
@@ -41,7 +41,7 @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a, uint32_t insn)
static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a, uint32_t insn)
{
- return trans_arith(ctx, a, &gen_mulhsu);
+ return gen_arith(ctx, a, &gen_mulhsu);
}
static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a, uint32_t insn)
@@ -61,28 +61,28 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a, uint32_t insn)
static bool trans_div(DisasContext *ctx, arg_div *a, uint32_t insn)
{
- return trans_arith(ctx, a, &gen_div);
+ return gen_arith(ctx, a, &gen_div);
}
static bool trans_divu(DisasContext *ctx, arg_divu *a, uint32_t insn)
{
- return trans_arith(ctx, a, &gen_divu);
+ return gen_arith(ctx, a, &gen_divu);
}
static bool trans_rem(DisasContext *ctx, arg_rem *a, uint32_t insn)
{
- return trans_arith(ctx, a, &gen_rem);
+ return gen_arith(ctx, a, &gen_rem);
}
static bool trans_remu(DisasContext *ctx, arg_remu *a, uint32_t insn)
{
- return trans_arith(ctx, a, &gen_remu);
+ return gen_arith(ctx, a, &gen_remu);
}
static bool trans_mulw(DisasContext *ctx, arg_mulw *a, uint32_t insn)
{
#ifdef TARGET_RISCV64
- return trans_arith(ctx, a, &tcg_gen_mul_tl);
+ return gen_arith(ctx, a, &tcg_gen_mul_tl);
#else
return false;
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 66241ecf33..ece163e69f 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -344,8 +344,8 @@ static bool gen_arith_imm(DisasContext *ctx, arg_arith_imm *a,
return true;
}
-static bool trans_arith(DisasContext *ctx, arg_arith *a,
- void(*func)(TCGv, TCGv, TCGv))
+static bool gen_arith(DisasContext *ctx, arg_arith *a,
+ void(*func)(TCGv, TCGv, TCGv))
{
TCGv source1, source2;
source1 = tcg_temp_new();
--
2.19.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 02/29] targer/riscv: Activate decodetree and implemnt LUI & AUIPC
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 02/29] targer/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
@ 2018-10-20 19:32 ` Richard Henderson
2018-10-25 16:58 ` Palmer Dabbelt
1 sibling, 0 replies; 60+ messages in thread
From: Richard Henderson @ 2018-10-20 19:32 UTC (permalink / raw)
To: Bastian Koppelmann, mjc, sagark, palmer
Cc: peer.adelt, Alistair.Francis, qemu-devel
On 10/20/18 12:14 AM, Bastian Koppelmann wrote:
> + static int32_t ex_shift_##amount(int imm) \
Not that it'll matter in practice, but s/int32_t/int/.
That's the type that's passed in, and it's the type that
is stored in the argument set structures.
r~
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 03/29] target/riscv: Convert RVXI branch insns to decodetree
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 03/29] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
@ 2018-10-20 19:34 ` Richard Henderson
2018-10-25 20:24 ` Palmer Dabbelt
1 sibling, 0 replies; 60+ messages in thread
From: Richard Henderson @ 2018-10-20 19:34 UTC (permalink / raw)
To: Bastian Koppelmann, mjc, sagark, palmer
Cc: peer.adelt, Alistair.Francis, qemu-devel
On 10/20/18 12:14 AM, Bastian Koppelmann wrote:
> - case OPC_RISC_AUIPC:
> - if (rd == 0) {
> - break; /* NOP */
> - }
> - tcg_gen_movi_tl(cpu_gpr[rd], (sextract64(ctx->opcode, 12, 20) << 12) +
> - ctx->base.pc_next);
> - break;
This should have been in the previous patch. Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 06/29] target/riscv: Convert RVXI fence insns to decodetree
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 06/29] target/riscv: Convert RVXI fence " Bastian Koppelmann
@ 2018-10-21 14:05 ` Richard Henderson
0 siblings, 0 replies; 60+ messages in thread
From: Richard Henderson @ 2018-10-21 14:05 UTC (permalink / raw)
To: Bastian Koppelmann, mjc, sagark, palmer
Cc: peer.adelt, Alistair.Francis, qemu-devel
On 10/20/18 8:14 AM, Bastian Koppelmann wrote:
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
> ---
> v1 -> v2:
> - simplified fence/fence_i as suggested by Richard
>
> target/riscv/insn32.decode | 6 ++++++
> target/riscv/insn_trans/trans_rvi.inc.c | 20 ++++++++++++++++++++
> target/riscv/translate.c | 14 --------------
> 3 files changed, 26 insertions(+), 14 deletions(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index cb7622e223..00e30dbc71 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -24,6 +24,9 @@
> %sh6 20:6
> %sh5 20:5
>
> +%pred 24:4
> +%succ 20:4
Unused.
> +static bool trans_fence(DisasContext *ctx, arg_fence *a, uint32_t insn)
> +{
> +#ifndef CONFIG_USER_ONLY
> + /* FENCE is a full memory barrier. */
> + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
> +#endif
> + return true;
> +}
> +static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a, uint32_t insn)
Spacing.
> +{
> +#ifndef CONFIG_USER_ONLY
> + /* FENCE_I is a no-op in QEMU,
> + * however we need to end the translation block */
> + tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
> + tcg_gen_exit_tb(NULL, 0);
> + ctx->base.is_jmp = DISAS_NORETURN;
> +#endif
> + return true;
> +}
I will note that both of these should apply to user-only as well...
> - case OPC_RISC_FENCE:
> -#ifndef CONFIG_USER_ONLY
> - if (ctx->opcode & 0x1000) {
> - /* FENCE_I is a no-op in QEMU,
> - * however we need to end the translation block */
> - tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
> - tcg_gen_exit_tb(NULL, 0);
> - ctx->base.is_jmp = DISAS_NORETURN;
> - } else {
> - /* FENCE is a full memory barrier. */
> - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
> - }
> -#endif
... even though you're simply copying the bug.
I mentioned this twice during initial review of risc-v, but it seems to have
been missed during commit.
Also note that one can do better than TCG_MO_ALL by actually using the
pred/succ bits to select TCG_MO_{LD,ST}_{LD,ST}.
That said, no new bugs with this patch, so
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 09/29] target/riscv: Convert RV32A insns to decodetree
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 09/29] target/riscv: Convert RV32A " Bastian Koppelmann
@ 2018-10-23 8:19 ` Richard Henderson
0 siblings, 0 replies; 60+ messages in thread
From: Richard Henderson @ 2018-10-23 8:19 UTC (permalink / raw)
To: Bastian Koppelmann, mjc, sagark, palmer
Cc: peer.adelt, Alistair.Francis, qemu-devel
On 10/20/18 8:14 AM, Bastian Koppelmann wrote:
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
> ---
> v1 -> v2:
> - simplified gen_amo() with function pointers
> - rs2 @atom_ld is now decimal
>
> target/riscv/insn32.decode | 17 +++
> target/riscv/insn_trans/trans_rva.inc.c | 145 ++++++++++++++++++++++++
> target/riscv/translate.c | 1 +
> 3 files changed, 163 insertions(+)
> create mode 100644 target/riscv/insn_trans/trans_rva.inc.c
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 13/29] target/riscv: Convert RV32D insns to decodetree
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 13/29] target/riscv: Convert RV32D " Bastian Koppelmann
@ 2018-10-23 8:21 ` Richard Henderson
2018-10-31 10:44 ` Bastian Koppelmann
1 sibling, 0 replies; 60+ messages in thread
From: Richard Henderson @ 2018-10-23 8:21 UTC (permalink / raw)
To: Bastian Koppelmann, mjc, sagark, palmer
Cc: peer.adelt, Alistair.Francis, qemu-devel
On 10/20/18 8:14 AM, Bastian Koppelmann wrote:
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
> ---
> v1 -> v2:
> - Add REQUIRE_FPU to arithm helpers
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 16/29] target/riscv: Convert quadrant 0 of RVXC insns to decodetree
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 16/29] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
@ 2018-10-23 8:31 ` Richard Henderson
0 siblings, 0 replies; 60+ messages in thread
From: Richard Henderson @ 2018-10-23 8:31 UTC (permalink / raw)
To: Bastian Koppelmann, mjc, sagark, palmer
Cc: peer.adelt, Alistair.Francis, qemu-devel
On 10/20/18 8:14 AM, Bastian Koppelmann wrote:
> v1 -> v2:
> - Stack allocate arg_c_* structs
> - ex_rvc_register returns int
> - special case of trans_c_addi4spn() returns false
...
> +static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a,
> + uint16_t insn)
> +{
> + if (a->nzuimm == 0) {
> + /* Reserved in ISA */
> + gen_exception_illegal(ctx);
> + return true;
> + }
That doesn't seem to have actually happened.
But otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 17/29] target/riscv: Convert quadrant 1 " Bastian Koppelmann
@ 2018-10-23 8:35 ` Richard Henderson
0 siblings, 0 replies; 60+ messages in thread
From: Richard Henderson @ 2018-10-23 8:35 UTC (permalink / raw)
To: Bastian Koppelmann, mjc, sagark, palmer
Cc: peer.adelt, Alistair.Francis, qemu-devel
On 10/20/18 8:14 AM, Bastian Koppelmann wrote:
> --- a/target/riscv/insn_trans/trans_rvc.inc.c
> +++ b/target/riscv/insn_trans/trans_rvc.inc.c
> @@ -23,8 +23,7 @@ static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a,
> {
> if (a->nzuimm == 0) {
> /* Reserved in ISA */
> - gen_exception_illegal(ctx);
> - return true;
> + return false;
Ah, the change for patch 16 got squished to the wrong patch.
> +static bool trans_c_srli(DisasContext *ctx, arg_c_srli *a, uint16_t insn)
> +{
> + int shamt = a->shamt;
> + if (shamt == 0) {
> + /* For RV128 a shamt of 0 means a shift by 64 */
> + shamt = 64;
> + }
> + /* Ensure, that shamt[5] is zero for RV32 */
> + if (shamt >= TARGET_LONG_BITS) {
> + return false;
> + }
> +
> + arg_srli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
> + return trans_srli(ctx, &arg, insn);
> +}
> +
> +static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a, uint16_t insn)
> +{
> + if (a->shamt == 0) {
> + /* Reserved in ISA */
> + return false;
> + }
> +#ifdef TARGET_RISCV32
> + /* Ensure, that shamt[5] is zero for RV32 */
> + if (a->shamt >= 32) {
> + return false;
> + }
> +#endif
Same change as srli. Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 18/29] target/riscv: Convert quadrant 2 of RVXC insns to decodetree
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 18/29] target/riscv: Convert quadrant 2 " Bastian Koppelmann
@ 2018-10-23 8:39 ` Richard Henderson
0 siblings, 0 replies; 60+ messages in thread
From: Richard Henderson @ 2018-10-23 8:39 UTC (permalink / raw)
To: Bastian Koppelmann, mjc, sagark, palmer
Cc: peer.adelt, Alistair.Francis, qemu-devel
On 10/20/18 8:14 AM, Bastian Koppelmann wrote:
> This also removes all functions that now became obsolete.
>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> ---
> target/riscv/insn16.decode | 34 +++++-
> target/riscv/insn_trans/trans_rvc.inc.c | 103 ++++++++++++++++
> target/riscv/translate.c | 151 +-----------------------
> 3 files changed, 135 insertions(+), 153 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
@ 2018-10-23 8:46 ` Richard Henderson
2018-10-24 9:07 ` Bastian Koppelmann
1 sibling, 0 replies; 60+ messages in thread
From: Richard Henderson @ 2018-10-23 8:46 UTC (permalink / raw)
To: Bastian Koppelmann, mjc, sagark, palmer
Cc: peer.adelt, Alistair.Francis, qemu-devel
On 10/20/18 8:14 AM, Bastian Koppelmann wrote:
> static bool trans_srli(DisasContext *ctx, arg_srli *a, uint32_t insn)
> {
> - gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt);
> + if (a->rd != 0) {
> + TCGv t = tcg_temp_new();
> + gen_get_gpr(t, a->rs1);
> + tcg_gen_extract_tl(t, t, a->shamt, 64 - a->shamt);
tcg_gen_shri_tl(t, t, a->shamt);
This is a mis-translation of the original code which handled srliw too.
You should be able to see this assert on riscv32.
> static bool trans_srai(DisasContext *ctx, arg_srai *a, uint32_t insn)
> {
> - gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt | 0x400);
> + if (a->rd != 0) {
> + TCGv t = tcg_temp_new();
> + gen_get_gpr(t, a->rs1);
> + tcg_gen_sextract_tl(t, t, a->shamt, 64 - a->shamt);
Similarly.
r~
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
@ 2018-10-23 8:53 ` Richard Henderson
2018-10-23 8:55 ` Richard Henderson
0 siblings, 1 reply; 60+ messages in thread
From: Richard Henderson @ 2018-10-23 8:53 UTC (permalink / raw)
To: Bastian Koppelmann, mjc, sagark, palmer
Cc: peer.adelt, Alistair.Francis, qemu-devel
On 10/20/18 8:14 AM, Bastian Koppelmann wrote:
> +static bool trans_arith(DisasContext *ctx, arg_arith *a,
> + void(*func)(TCGv, TCGv, TCGv))
gen_arith.
r~
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
2018-10-23 8:53 ` Richard Henderson
@ 2018-10-23 8:55 ` Richard Henderson
0 siblings, 0 replies; 60+ messages in thread
From: Richard Henderson @ 2018-10-23 8:55 UTC (permalink / raw)
To: Bastian Koppelmann, mjc, sagark, palmer
Cc: peer.adelt, Alistair.Francis, qemu-devel
On 10/23/18 9:53 AM, Richard Henderson wrote:
> On 10/20/18 8:14 AM, Bastian Koppelmann wrote:
>> +static bool trans_arith(DisasContext *ctx, arg_arith *a,
>> + void(*func)(TCGv, TCGv, TCGv))
>
> gen_arith.
Oh, right, last patch.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 26/29] target/riscv: Remove manual decoding of RV32/64M insn
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 26/29] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
@ 2018-10-23 9:02 ` Richard Henderson
0 siblings, 0 replies; 60+ messages in thread
From: Richard Henderson @ 2018-10-23 9:02 UTC (permalink / raw)
To: Bastian Koppelmann, mjc, sagark, palmer
Cc: peer.adelt, Alistair.Francis, qemu-devel
On 10/20/18 8:14 AM, Bastian Koppelmann wrote:
> static bool trans_mulh(DisasContext *ctx, arg_mulh *a, uint32_t insn)
> {
> - gen_arith(ctx, OPC_RISC_MULH, a->rd, a->rs1, a->rs2);
> + TCGv source1 = tcg_temp_new();
> + TCGv source2 = tcg_temp_new();
> + gen_get_gpr(source1, a->rs1);
> + gen_get_gpr(source2, a->rs2);
> +
> + tcg_gen_muls2_tl(source2, source1, source1, source2);
If you wanted, you could probably put this line into a function to keep using
trans_arith. But this is ok too.
> static bool trans_mulw(DisasContext *ctx, arg_mulw *a, uint32_t insn)
> {
> - gen_arith(ctx, OPC_RISC_MULW, a->rd, a->rs1, a->rs2);
> - return true;
> +#ifdef TARGET_RISCV64
> + return trans_arith(ctx, a, &tcg_gen_mul_tl);
> +#else
> + return false;
> +#endif
This is wrong; you need a final sign-extend.
> +#ifdef TARGET_RISCV64
> +static bool gen_arith_w(DisasContext *ctx, arg_arith *a,
> + void(*func)(TCGv, TCGv, TCGv))
> +{
> + TCGv source1, source2;
> + source1 = tcg_temp_new();
> + source2 = tcg_temp_new();
> +
> + gen_get_gpr(source1, a->rs1);
> + gen_get_gpr(source2, a->rs2);
> + tcg_gen_ext32s_tl(source1, source1);
> + tcg_gen_ext32s_tl(source2, source2);
> +
> + (*func)(source1, source1, source2);
> +
> + gen_set_gpr(a->rd, source1);
> + tcg_temp_free(source1);
> + tcg_temp_free(source2);
> + return true;
> +}
> +#endif
This appears to have been extracted only from, and is only applicable to, the
word division routines. It probably should be renamed lest someone think that
it could be used for addw and mulw, which require the output be extended.
r~
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 28/29] target/riscv: Remove decode_RV32_64G()
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 28/29] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
@ 2018-10-23 9:04 ` Richard Henderson
0 siblings, 0 replies; 60+ messages in thread
From: Richard Henderson @ 2018-10-23 9:04 UTC (permalink / raw)
To: Bastian Koppelmann, mjc, sagark, palmer
Cc: peer.adelt, Alistair.Francis, qemu-devel
On 10/20/18 8:14 AM, Bastian Koppelmann wrote:
> decodetree handles all instructions now so the fallback is not necessary
> anymore.
>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
> ---
> v1 -> v2:
> - Add missing gen_exception_illegal
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 29/29] target/riscv: Rename trans_arith to gen_arith
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 29/29] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
@ 2018-10-23 9:04 ` Richard Henderson
0 siblings, 0 replies; 60+ messages in thread
From: Richard Henderson @ 2018-10-23 9:04 UTC (permalink / raw)
To: Bastian Koppelmann, mjc, sagark, palmer
Cc: peer.adelt, Alistair.Francis, qemu-devel
On 10/20/18 8:14 AM, Bastian Koppelmann wrote:
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> ---
> target/riscv/insn_trans/trans_rvi.inc.c | 14 +++++++-------
> target/riscv/insn_trans/trans_rvm.inc.c | 14 +++++++-------
> target/riscv/translate.c | 4 ++--
> 3 files changed, 16 insertions(+), 16 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2018-10-23 8:46 ` Richard Henderson
@ 2018-10-24 9:07 ` Bastian Koppelmann
1 sibling, 0 replies; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-24 9:07 UTC (permalink / raw)
To: mjc, sagark, palmer
Cc: richard.henderson, peer.adelt, Alistair.Francis, qemu-devel
On 10/20/18 9:14 AM, Bastian Koppelmann wrote:
> @@ -338,27 +375,63 @@ static bool trans_and(DisasContext *ctx, arg_and *a, uint32_t insn)
>
> static bool trans_addiw(DisasContext *ctx, arg_addiw *a, uint32_t insn)
> {
> - gen_arith_imm(ctx, OPC_RISC_ADDIW, a->rd, a->rs1, a->imm);
> - return true;
> +#ifdef TARGET_RISCV64
> + bool res = gen_arith_imm(ctx, a, &tcg_gen_add_tl);
> + tcg_gen_ext32s_tl(cpu_gpr[a->rd], cpu_gpr[a->rd]);
This obviously does not work if a->rd is register zero which is never
allocated.
Cheers,
Bastian
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
` (28 preceding siblings ...)
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 29/29] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
@ 2018-10-24 22:21 ` Palmer Dabbelt
2018-10-26 10:53 ` Bastian Koppelmann
29 siblings, 1 reply; 60+ messages in thread
From: Palmer Dabbelt @ 2018-10-24 22:21 UTC (permalink / raw)
Cc: Michael Clark, sagark, kbastian, peer.adelt, Alistair Francis,
richard.henderson, qemu-devel
On Sat, 20 Oct 2018 00:14:22 PDT (-0700), kbastian@mail.uni-paderborn.de wrote:
> Hi,
>
> this patchset converts the RISC-V decoder to decodetree in three major steps:
>
> 1) Convert 32-bit instructions to decodetree [Patch 1-14]:
> Many of the gen_* functions are called by the decode functions for 16-bit
> and 32-bit functions. If we move translation code from the gen_*
> functions to the generated trans_* functions of decode-tree, we get a lot of
> duplication. Therefore, we mostly generate calls to the old gen_* function
> which are properly replaced after step 2).
>
> Each of the trans_ functions are grouped into files corresponding to their
> ISA extension, e.g. addi which is in RV32I is translated in the file
> 'trans_rvi.inc.c'.
>
> 2) Convert 16-bit instructions to decodetree [Patch 15-17]:
> All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
> we convert the arguments in the 16 bit trans_ function to the arguments of
> the corresponding 32 bit instruction and call the 32 bit trans_ function.
>
> 3) Remove old manual decoding in gen_* function [Patch 17-28]:
> this move all manual translation code into the trans_* instructions of
> decode tree, such that we can remove the old decode_* functions.
>
> the full tree can be found here:
> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v2
Thanks!
I dropped this on top of master and it appears I'm getting a bunch of oops when
trying to boot Linux. They're fairly far into the boot process and may be a
mistake on my end, I was just wondering if you'd booted Linux?
I'll go through the patches and review them.
>
> Cheers,
> Bastian
>
> v1->v2:
> - ex_shift_amount returns uint32_t
> - use ctx->env instead of current_cpu->env_ptr
> - fixed functionspacing
> - RISCV32 now returns false instead of raising an exception
> - shift translators now also use gen_arithm_imm()
> - simplified fence/fence_i as suggested by Richard
> - simplified gen_amo() with function pointers
> - rs2 @atom_ld is now decimal
> - use simplfied gen_amo() with function pointers
> - REQUIRE_FPU uses do {} while (0)
> - Add REQUIRE_FPU to arithm helpers
> - RISCV32 now returns false instead of raising an exception
> - Add REQUIRE_FPU to arithm helpers
> - Stack allocate arg_c_* structs
> - ex_rvc_register returns int
> - special case of trans_c_addi4spn() returns false
> - consistently return false for reserved cases instead of raising an
> exception
> - simplified trans_c_srli by Richard's suggestion
> - remove extract_cj() since its result isn't used
> - trans_branch -> gen_branch
> - trans_load -> gen_load
> - removed negative memop check
> - trans_store -> gen_store
> - removed negative memop check
> - trans_arith_imm -> gen_arith_imm
> - Add missing TARGET_RISC64 checks
> - Reimplement shift translators that were omited in [0004/0028]
> - trans_shift -> gen_shift
> - Add missing TARGET_RISCV64 conditions
> - trans_arith_w -> gen_arith_w
> - Add missing gen_exception_illegal
> - dropped 0028
>
>
> Bastian Koppelmann (29):
> target/riscv: Move CPURISCVState pointer to DisasContext
> targer/riscv: Activate decodetree and implemnt LUI & AUIPC
> target/riscv: Convert RVXI branch insns to decodetree
> target/riscv: Convert RVXI load/store insns to decodetree
> target/riscv: Convert RVXI arithmetic insns to decodetree
> target/riscv: Convert RVXI fence insns to decodetree
> target/riscv: Convert RVXI csr insns to decodetree
> target/riscv: Convert RVXM insns to decodetree
> target/riscv: Convert RV32A insns to decodetree
> target/riscv: Convert RV64A insns to decodetree
> target/riscv: Convert RV32F insns to decodetree
> target/riscv: Convert RV64F insns to decodetree
> target/riscv: Convert RV32D insns to decodetree
> target/riscv: Convert RV64D insns to decodetree
> target/riscv: Convert RV priv insns to decodetree
> target/riscv: Convert quadrant 0 of RVXC insns to decodetree
> target/riscv: Convert quadrant 1 of RVXC insns to decodetree
> target/riscv: Convert quadrant 2 of RVXC insns to decodetree
> target/riscv: Remove gen_jalr()
> target/riscv: Remove manual decoding from gen_branch()
> target/riscv: Remove manual decoding from gen_load()
> target/riscv: Remove manual decoding from gen_store()
> target/riscv: Move gen_arith_imm() decoding into trans_* functions
> target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
> target/riscv: Remove shift and slt insn manual decoding
> target/riscv: Remove manual decoding of RV32/64M insn
> target/riscv: Remove gen_system()
> target/riscv: Remove decode_RV32_64G()
> target/riscv: Rename trans_arith to gen_arith
>
> target/riscv/Makefile.objs | 17 +
> target/riscv/insn16.decode | 126 ++
> target/riscv/insn32.decode | 256 +++
> .../riscv/insn_trans/trans_privileged.inc.c | 111 ++
> target/riscv/insn_trans/trans_rva.inc.c | 244 +++
> target/riscv/insn_trans/trans_rvc.inc.c | 337 ++++
> target/riscv/insn_trans/trans_rvd.inc.c | 413 ++++
> target/riscv/insn_trans/trans_rvf.inc.c | 402 ++++
> target/riscv/insn_trans/trans_rvi.inc.c | 629 ++++++
> target/riscv/insn_trans/trans_rvm.inc.c | 125 ++
> target/riscv/translate.c | 1756 ++---------------
> 11 files changed, 2853 insertions(+), 1563 deletions(-)
> create mode 100644 target/riscv/insn16.decode
> create mode 100644 target/riscv/insn32.decode
> create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c
> create mode 100644 target/riscv/insn_trans/trans_rva.inc.c
> create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
> create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c
> create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c
> create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c
> create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 01/29] target/riscv: Move CPURISCVState pointer to DisasContext
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 01/29] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann
@ 2018-10-25 16:38 ` Palmer Dabbelt
2018-10-25 16:54 ` Peter Maydell
0 siblings, 1 reply; 60+ messages in thread
From: Palmer Dabbelt @ 2018-10-25 16:38 UTC (permalink / raw)
Cc: Michael Clark, sagark, kbastian, peer.adelt, Alistair Francis,
richard.henderson, qemu-devel
On Sat, 20 Oct 2018 00:14:23 PDT (-0700), kbastian@mail.uni-paderborn.de wrote:
> CPURISCVState is rarely used, so there is no need to pass it to every
> translate function. This paves the way for decodetree which only passes
> DisasContext to translate functions.
>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> ---
> target/riscv/translate.c | 15 ++++++++-------
> 1 file changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 18d7b6d147..e81b9f097e 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -52,6 +52,7 @@ typedef struct DisasContext {
> to any system register, which includes CSR_FRM, so we do not have
> to reset this known value. */
> int frm;
> + CPURISCVState *env;
> } DisasContext;
>
> /* convert riscv funct3 to qemu memop for load/store */
> @@ -1789,19 +1790,19 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
> }
> }
>
> -static void decode_opc(CPURISCVState *env, DisasContext *ctx)
> +static void decode_opc(DisasContext *ctx)
> {
> /* check for compressed insn */
> if (extract32(ctx->opcode, 0, 2) != 3) {
> - if (!riscv_has_ext(env, RVC)) {
> + if (!riscv_has_ext(ctx->env, RVC)) {
> gen_exception_illegal(ctx);
> } else {
> ctx->pc_succ_insn = ctx->base.pc_next + 2;
> - decode_RV32_64C(env, ctx);
> + decode_RV32_64C(ctx->env, ctx);
> }
> } else {
> ctx->pc_succ_insn = ctx->base.pc_next + 4;
> - decode_RV32_64G(env, ctx);
> + decode_RV32_64G(ctx->env, ctx);
> }
> }
>
> @@ -1846,10 +1847,10 @@ static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
> static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
> {
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
> - CPURISCVState *env = cpu->env_ptr;
> + ctx->env = cpu->env_ptr;
>
> - ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
> - decode_opc(env, ctx);
> + ctx->opcode = cpu_ldl_code(ctx->env, ctx->base.pc_next);
> + decode_opc(ctx);
> ctx->base.pc_next = ctx->pc_succ_insn;
>
> if (ctx->base.is_jmp == DISAS_NEXT) {
I think this is OK, but I'm not sure. All the other ports do this in a
different way: rather than including the CPU state structure in DisasContext
they explicitly call out the state that can change instruction decoding by
duplicating it within DisasContext. Michael's patch queue handles this in the
canonical way, but I think it's a bit cleaner to avoid duplicating the state.
My worry is that, since changing the CPU state changes the legal instructions,
we will paint ourselves into a corner when it comes to faithfully implementing
a writeable MISA register.
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 01/29] target/riscv: Move CPURISCVState pointer to DisasContext
2018-10-25 16:38 ` Palmer Dabbelt
@ 2018-10-25 16:54 ` Peter Maydell
2018-10-25 17:05 ` Palmer Dabbelt
0 siblings, 1 reply; 60+ messages in thread
From: Peter Maydell @ 2018-10-25 16:54 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Bastian Koppelmann, Sagar Karandikar, Richard Henderson,
QEMU Developers, peer.adelt, Alistair Francis, Michael Clark
On 25 October 2018 at 17:38, Palmer Dabbelt <palmer@sifive.com> wrote:
> On Sat, 20 Oct 2018 00:14:23 PDT (-0700), kbastian@mail.uni-paderborn.de
> wrote:
>>
>> CPURISCVState is rarely used, so there is no need to pass it to every
>> translate function. This paves the way for decodetree which only passes
>> DisasContext to translate functions.
>> --- a/target/riscv/translate.c
>> +++ b/target/riscv/translate.c
>> @@ -52,6 +52,7 @@ typedef struct DisasContext {
>> to any system register, which includes CSR_FRM, so we do not have
>> to reset this known value. */
>> int frm;
>> + CPURISCVState *env;
>> } DisasContext;
> I think this is OK, but I'm not sure. All the other ports do this in a
> different way: rather than including the CPU state structure in DisasContext
> they explicitly call out the state that can change instruction decoding by
> duplicating it within DisasContext.
Yes. The reason for doing this is that it makes it easier to avoid
a particular class of bug. Any target CPU state that we "bake into"
the generated TCG code needs to be one of:
* constant for the life of the CPU (eg ID register values, or
feature bits)
* encoded into the TB flags (which are filled in by
the target's cpu_get_tb_cpu_state())
If you generate code that depends on some other target CPU state
by accident, then this will cause hard to track down bugs when
we reuse the generated TB in an executed context where that
target CPU state has changed from what it was when the TB was
generated.
By not allowing the code generation parts of translate.c to get
hold of the CPUState pointer, we can make this kind of bug much
easier to spot at compile time, because any new state that we
want to use in codegen has to be copied into the DisasContext.
It's then fairly easy to check that we only copy into the
DisasContext state that is constant-for-the-CPU or which we've
got from the TB flags.
That said, at the moment the riscv frontend code does not
use this pattern -- it passes the CPURISCVState pointer
directly into (some of) the leaf functions, like gen_jal().
So putting the CPURISCVState into DisasContext is no worse
than passing it around all these translate.c functions as
a function parameter.
I would prefer it if the riscv code was cleaned up to
do the explicit passing of only the required bits of state
in DisasContext (as for instance target/arm/ does). But I
don't have a strong opinion on the ordering of doing that
versus doing this conversion to decodetree.
thanks
-- PMM
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 02/29] targer/riscv: Activate decodetree and implemnt LUI & AUIPC
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 02/29] targer/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2018-10-20 19:32 ` Richard Henderson
@ 2018-10-25 16:58 ` Palmer Dabbelt
2018-10-26 10:49 ` Bastian Koppelmann
1 sibling, 1 reply; 60+ messages in thread
From: Palmer Dabbelt @ 2018-10-25 16:58 UTC (permalink / raw)
Cc: Michael Clark, sagark, kbastian, peer.adelt, Alistair Francis,
richard.henderson, qemu-devel
On Sat, 20 Oct 2018 00:14:24 PDT (-0700), kbastian@mail.uni-paderborn.de wrote:
> for now only LUI & AUIPC are decoded and translated. If decodetree fails, we
> fall back to the old decoder.
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
> ---
> v1 -> v2:
> - ex_shift_amount returns uint32_t
You mean int32_t, right? That's what the code does, and I believe that's
what it's supposed to do according to the ISA.
>
> target/riscv/Makefile.objs | 10 +++++++
> target/riscv/insn32.decode | 30 +++++++++++++++++++++
> target/riscv/insn_trans/trans_rvi.inc.c | 35 +++++++++++++++++++++++++
> target/riscv/translate.c | 24 ++++++++++++-----
> 4 files changed, 92 insertions(+), 7 deletions(-)
> create mode 100644 target/riscv/insn32.decode
> create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c
>
> diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
> index abd0a7cde3..ea02f9b9ef 100644
> --- a/target/riscv/Makefile.objs
> +++ b/target/riscv/Makefile.objs
> @@ -1 +1,11 @@
> obj-y += translate.o op_helper.o helper.o cpu.o fpu_helper.o gdbstub.o pmp.o
> +
> +DECODETREE = $(SRC_PATH)/scripts/decodetree.py
> +
> +target/riscv/decode_insn32.inc.c: \
> + $(SRC_PATH)/target/riscv/insn32.decode $(DECODETREE)
> + $(call quiet-command, \
> + $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $<, \
> + "GEN", $(TARGET_DIR)$@)
> +
> +target/riscv/translate.o: target/riscv/decode_insn32.inc.c
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> new file mode 100644
> index 0000000000..44d4e922b6
> --- /dev/null
> +++ b/target/riscv/insn32.decode
> @@ -0,0 +1,30 @@
> +#
> +# RISC-V translation routines for the RVXI Base Integer Instruction Set.
> +#
> +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> +#
> +# This program is free software; you can redistribute it and/or modify it
> +# under the terms and conditions of the GNU General Public License,
> +# version 2 or later, as published by the Free Software Foundation.
> +#
> +# This program is distributed in the hope it will be useful, but WITHOUT
> +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> +# more details.
> +#
> +# You should have received a copy of the GNU General Public License along with
> +# this program. If not, see <http://www.gnu.org/licenses/>.
> +
> +# Fields:
> +%rd 7:5
> +
> +# immediates:
> +%imm_u 12:s20 !function=ex_shift_12
> +
> +# Formats 32:
> +@u .................... ..... ....... imm=%imm_u %rd
> +
> +# *** RV32I Base Instruction Set ***
> +lui .................... ..... 0110111 @u
> +auipc .................... ..... 0010111 @u
> diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
> new file mode 100644
> index 0000000000..aee0d1637d
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_rvi.inc.c
> @@ -0,0 +1,35 @@
> +/*
> + * RISC-V translation routines for the RVXI Base Integer Instruction Set.
> + *
> + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
> + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +static bool trans_lui(DisasContext *ctx, arg_lui *a, uint32_t insn)
> +{
> + if (a->rd != 0) {
> + tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
> + }
> + return true;
> +}
> +
> +static bool trans_auipc(DisasContext *ctx, arg_auipc *a, uint32_t insn)
> +{
> + if (a->rd != 0) {
> + tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next);
> + }
> + return true;
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index e81b9f097e..65a323a201 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1667,6 +1667,19 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
> }
> }
>
> +#define EX_SH(amount) \
> + static int32_t ex_shift_##amount(int imm) \
> + { \
> + return imm << amount; \
> + }
> +EX_SH(12)
> +
> +bool decode_insn32(DisasContext *ctx, uint32_t insn);
> +/* Include the auto-generated decoder for 32 bit insn */
> +#include "decode_insn32.inc.c"
> +/* Include insn module translation function */
> +#include "insn_trans/trans_rvi.inc.c"
> +
> static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
> {
> int rs1;
> @@ -1687,12 +1700,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
> imm = GET_IMM(ctx->opcode);
>
> switch (op) {
> - case OPC_RISC_LUI:
> - if (rd == 0) {
> - break; /* NOP */
> - }
> - tcg_gen_movi_tl(cpu_gpr[rd], sextract64(ctx->opcode, 12, 20) << 12);
> - break;
> case OPC_RISC_AUIPC:
> if (rd == 0) {
> break; /* NOP */
> @@ -1802,7 +1809,10 @@ static void decode_opc(DisasContext *ctx)
> }
> } else {
> ctx->pc_succ_insn = ctx->base.pc_next + 4;
> - decode_RV32_64G(ctx->env, ctx);
> + if (!decode_insn32(ctx, ctx->opcode)) {
> + /* fallback to old decoder */
> + decode_RV32_64G(ctx->env, ctx);
> + }
> }
> }
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
How do you want to go about merging these? It looks like it should be possible
to merge the patch set piecemeal, which I'd actually be happy doing as it'll be
easier to get these out for testing that way. That way we can avoid having one
day where everyone changes over to a new decoder. If that's OK then I'll start
slurping up this up into my weekly pull requests as I can review them, with the
idea being that I won't re-order anything (in other words, I'll start at the
first patch and take patches until I find one that isn't ready to go).
Thanks!
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 01/29] target/riscv: Move CPURISCVState pointer to DisasContext
2018-10-25 16:54 ` Peter Maydell
@ 2018-10-25 17:05 ` Palmer Dabbelt
0 siblings, 0 replies; 60+ messages in thread
From: Palmer Dabbelt @ 2018-10-25 17:05 UTC (permalink / raw)
To: Peter Maydell
Cc: kbastian, sagark, richard.henderson, qemu-devel, peer.adelt,
Alistair Francis, Michael Clark
On Thu, 25 Oct 2018 09:54:56 PDT (-0700), Peter Maydell wrote:
> On 25 October 2018 at 17:38, Palmer Dabbelt <palmer@sifive.com> wrote:
>> On Sat, 20 Oct 2018 00:14:23 PDT (-0700), kbastian@mail.uni-paderborn.de
>> wrote:
>>>
>>> CPURISCVState is rarely used, so there is no need to pass it to every
>>> translate function. This paves the way for decodetree which only passes
>>> DisasContext to translate functions.
>
>>> --- a/target/riscv/translate.c
>>> +++ b/target/riscv/translate.c
>>> @@ -52,6 +52,7 @@ typedef struct DisasContext {
>>> to any system register, which includes CSR_FRM, so we do not have
>>> to reset this known value. */
>>> int frm;
>>> + CPURISCVState *env;
>>> } DisasContext;
>
>
>> I think this is OK, but I'm not sure. All the other ports do this in a
>> different way: rather than including the CPU state structure in DisasContext
>> they explicitly call out the state that can change instruction decoding by
>> duplicating it within DisasContext.
>
> Yes. The reason for doing this is that it makes it easier to avoid
> a particular class of bug. Any target CPU state that we "bake into"
> the generated TCG code needs to be one of:
> * constant for the life of the CPU (eg ID register values, or
> feature bits)
> * encoded into the TB flags (which are filled in by
> the target's cpu_get_tb_cpu_state())
> If you generate code that depends on some other target CPU state
> by accident, then this will cause hard to track down bugs when
> we reuse the generated TB in an executed context where that
> target CPU state has changed from what it was when the TB was
> generated.
>
> By not allowing the code generation parts of translate.c to get
> hold of the CPUState pointer, we can make this kind of bug much
> easier to spot at compile time, because any new state that we
> want to use in codegen has to be copied into the DisasContext.
> It's then fairly easy to check that we only copy into the
> DisasContext state that is constant-for-the-CPU or which we've
> got from the TB flags.
>
> That said, at the moment the riscv frontend code does not
> use this pattern -- it passes the CPURISCVState pointer
> directly into (some of) the leaf functions, like gen_jal().
> So putting the CPURISCVState into DisasContext is no worse
> than passing it around all these translate.c functions as
> a function parameter.
>
> I would prefer it if the riscv code was cleaned up to
> do the explicit passing of only the required bits of state
> in DisasContext (as for instance target/arm/ does). But I
> don't have a strong opinion on the ordering of doing that
> versus doing this conversion to decodetree.
OK, that makes sense. Since our port is already broken WRT this behavior and
the decode tree stuff will be nice to have, I'm happy taking this change now
and fixing this later -- that way we won't have to couple two major changes
into a single patch set.
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Thanks!
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 03/29] target/riscv: Convert RVXI branch insns to decodetree
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 03/29] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2018-10-20 19:34 ` Richard Henderson
@ 2018-10-25 20:24 ` Palmer Dabbelt
1 sibling, 0 replies; 60+ messages in thread
From: Palmer Dabbelt @ 2018-10-25 20:24 UTC (permalink / raw)
Cc: Michael Clark, sagark, Bastian Koppelmann, peer.adelt,
Alistair Francis, richard.henderson, qemu-devel
On Sat, 20 Oct 2018 00:14:25 PDT (-0700), Bastian Koppelmann wrote:
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
> ---
> v1 -> v2:
> - use ctx->env instead of current_cpu->env_ptr
>
> target/riscv/insn32.decode | 19 ++++++++++
> target/riscv/insn_trans/trans_rvi.inc.c | 49 +++++++++++++++++++++++++
> target/riscv/translate.c | 19 +---------
> 3 files changed, 69 insertions(+), 18 deletions(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 44d4e922b6..b49913416d 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -17,14 +17,33 @@
> # this program. If not, see <http://www.gnu.org/licenses/>.
>
> # Fields:
> +%rs2 20:5
> +%rs1 15:5
> %rd 7:5
>
> # immediates:
> +%imm_i 20:s12
> +%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
> +%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
> %imm_u 12:s20 !function=ex_shift_12
>
> +# Argument sets:
> +&branch imm rs2 rs1
> +
> # Formats 32:
> +@i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd
> +@b ....... ..... ..... ... ..... ....... &branch imm=%imm_b %rs2 %rs1
> @u .................... ..... ....... imm=%imm_u %rd
> +@j .................... ..... ....... imm=%imm_j %rd
>
> # *** RV32I Base Instruction Set ***
> lui .................... ..... 0110111 @u
> auipc .................... ..... 0010111 @u
> +jal .................... ..... 1101111 @j
> +jalr ............ ..... 000 ..... 1100111 @i
> +beq ....... ..... ..... 000 ..... 1100011 @b
> +bne ....... ..... ..... 001 ..... 1100011 @b
> +blt ....... ..... ..... 100 ..... 1100011 @b
> +bge ....... ..... ..... 101 ..... 1100011 @b
> +bltu ....... ..... ..... 110 ..... 1100011 @b
> +bgeu ....... ..... ..... 111 ..... 1100011 @b
> diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
> index aee0d1637d..3935a80ba5 100644
> --- a/target/riscv/insn_trans/trans_rvi.inc.c
> +++ b/target/riscv/insn_trans/trans_rvi.inc.c
> @@ -33,3 +33,52 @@ static bool trans_auipc(DisasContext *ctx, arg_auipc *a, uint32_t insn)
> }
> return true;
> }
> +
> +static bool trans_jal(DisasContext *ctx, arg_jal *a, uint32_t insn)
> +{
> + gen_jal(ctx->env, ctx, a->rd, a->imm);
> + return true;
> +}
> +
> +static bool trans_jalr(DisasContext *ctx, arg_jalr *a, uint32_t insn)
> +{
> + gen_jalr(ctx->env, ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm);
> + return true;
> +}
> +
> +static bool trans_beq(DisasContext *ctx, arg_beq *a, uint32_t insn)
> +{
> + gen_branch(ctx->env, ctx, OPC_RISC_BEQ, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> +
> +static bool trans_bne(DisasContext *ctx, arg_bne *a, uint32_t insn)
> +{
> + gen_branch(ctx->env, ctx, OPC_RISC_BNE, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> +
> +static bool trans_blt(DisasContext *ctx, arg_blt *a, uint32_t insn)
> +{
> + gen_branch(ctx->env, ctx, OPC_RISC_BLT, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> +
> +static bool trans_bge(DisasContext *ctx, arg_bge *a, uint32_t insn)
> +{
> + gen_branch(ctx->env, ctx, OPC_RISC_BGE, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> +
> +static bool trans_bltu(DisasContext *ctx, arg_bltu *a, uint32_t insn)
> +{
> + gen_branch(ctx->env, ctx, OPC_RISC_BLTU, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> +
> +static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a, uint32_t insn)
> +{
> +
> + gen_branch(ctx->env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 65a323a201..9b6848e666 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1672,6 +1672,7 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
> { \
> return imm << amount; \
> }
> +EX_SH(1)
> EX_SH(12)
>
> bool decode_insn32(DisasContext *ctx, uint32_t insn);
> @@ -1700,24 +1701,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
> imm = GET_IMM(ctx->opcode);
>
> switch (op) {
> - case OPC_RISC_AUIPC:
> - if (rd == 0) {
> - break; /* NOP */
> - }
> - tcg_gen_movi_tl(cpu_gpr[rd], (sextract64(ctx->opcode, 12, 20) << 12) +
> - ctx->base.pc_next);
> - break;
This should go with the previous patch. I can move it if you want me to start
merging this patch set.
> - case OPC_RISC_JAL:
> - imm = GET_JAL_IMM(ctx->opcode);
> - gen_jal(env, ctx, rd, imm);
> - break;
> - case OPC_RISC_JALR:
> - gen_jalr(env, ctx, MASK_OP_JALR(ctx->opcode), rd, rs1, imm);
> - break;
> - case OPC_RISC_BRANCH:
> - gen_branch(env, ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2,
> - GET_B_IMM(ctx->opcode));
> - break;
> case OPC_RISC_LOAD:
> gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm);
> break;
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 02/29] targer/riscv: Activate decodetree and implemnt LUI & AUIPC
2018-10-25 16:58 ` Palmer Dabbelt
@ 2018-10-26 10:49 ` Bastian Koppelmann
2018-10-26 13:58 ` Richard Henderson
0 siblings, 1 reply; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-26 10:49 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: sagark, richard.henderson, qemu-devel, peer.adelt,
Alistair Francis, Michael Clark
On 10/25/18 6:58 PM, Palmer Dabbelt wrote:
>
> Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
>
> How do you want to go about merging these? It looks like it should be
> possible to merge the patch set piecemeal, which I'd actually be happy
> doing as it'll be easier to get these out for testing that way. That
> way we can avoid having one day where everyone changes over to a new
> decoder. If that's OK then I'll start slurping up this up into my
> weekly pull requests as I can review them, with the idea being that I
> won't re-order anything (in other words, I'll start at the first patch
> and take patches until I find one that isn't ready to go).
I think you can pick up everything up to the RVC conversion which still
needs the work suggested by Richard. Thanks, for picking it up :)
Cheers,
Bastian
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree
2018-10-24 22:21 ` [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Palmer Dabbelt
@ 2018-10-26 10:53 ` Bastian Koppelmann
2018-10-27 6:20 ` Palmer Dabbelt
0 siblings, 1 reply; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-26 10:53 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: sagark, richard.henderson, qemu-devel, peer.adelt,
Alistair Francis, Michael Clark
On 10/25/18 12:21 AM, Palmer Dabbelt wrote:
> On Sat, 20 Oct 2018 00:14:22 PDT (-0700),
> kbastian@mail.uni-paderborn.de wrote:
>> Hi,
>>
>> this patchset converts the RISC-V decoder to decodetree in three
>> major steps:
>>
>> 1) Convert 32-bit instructions to decodetree [Patch 1-14]:
>> Many of the gen_* functions are called by the decode functions
>> for 16-bit
>> and 32-bit functions. If we move translation code from the gen_*
>> functions to the generated trans_* functions of decode-tree, we
>> get a lot of
>> duplication. Therefore, we mostly generate calls to the old gen_*
>> function
>> which are properly replaced after step 2).
>>
>> Each of the trans_ functions are grouped into files corresponding
>> to their
>> ISA extension, e.g. addi which is in RV32I is translated in the file
>> 'trans_rvi.inc.c'.
>>
>> 2) Convert 16-bit instructions to decodetree [Patch 15-17]:
>> All 16 bit instructions have a direct mapping to a 32 bit
>> instruction. Thus,
>> we convert the arguments in the 16 bit trans_ function to the
>> arguments of
>> the corresponding 32 bit instruction and call the 32 bit trans_
>> function.
>>
>> 3) Remove old manual decoding in gen_* function [Patch 17-28]:
>> this move all manual translation code into the trans_*
>> instructions of
>> decode tree, such that we can remove the old decode_* functions.
>>
>> the full tree can be found here:
>> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v2
>
> Thanks!
>
> I dropped this on top of master and it appears I'm getting a bunch of
> oops when trying to boot Linux. They're fairly far into the boot
> process and may be a mistake on my end, I was just wondering if you'd
> booted Linux?
Are there non fatal oops in booting Linux? I only checked whether I
could get a terminal on Fedora Linux.
Cheers,
Bastian
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 02/29] targer/riscv: Activate decodetree and implemnt LUI & AUIPC
2018-10-26 10:49 ` Bastian Koppelmann
@ 2018-10-26 13:58 ` Richard Henderson
2018-10-26 14:53 ` Bastian Koppelmann
0 siblings, 1 reply; 60+ messages in thread
From: Richard Henderson @ 2018-10-26 13:58 UTC (permalink / raw)
To: Bastian Koppelmann, Palmer Dabbelt
Cc: sagark, qemu-devel, peer.adelt, Alistair Francis, Michael Clark
On 10/26/18 11:49 AM, Bastian Koppelmann wrote:
> I think you can pick up everything up to the RVC conversion which still needs
> the work suggested by Richard. Thanks, for picking it up :)
Even then I thought we were talking about splitting the RV64 insns
into a separate file, reducing the ifdefs, and renaming the arg-sets
to match the instruction formats described in the riscv spec.
r~
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 02/29] targer/riscv: Activate decodetree and implemnt LUI & AUIPC
2018-10-26 13:58 ` Richard Henderson
@ 2018-10-26 14:53 ` Bastian Koppelmann
2018-10-26 15:42 ` Palmer Dabbelt
0 siblings, 1 reply; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-26 14:53 UTC (permalink / raw)
To: Richard Henderson, Palmer Dabbelt
Cc: sagark, qemu-devel, peer.adelt, Alistair Francis, Michael Clark
On 10/26/18 3:58 PM, Richard Henderson wrote:
> On 10/26/18 11:49 AM, Bastian Koppelmann wrote:
>> I think you can pick up everything up to the RVC conversion which still needs
>> the work suggested by Richard. Thanks, for picking it up :)
> Even then I thought we were talking about splitting the RV64 insns
> into a separate file, reducing the ifdefs, and renaming the arg-sets
> to match the instruction formats described in the riscv spec.
Yes, you are right I forgot that.
Cheers,
Bastian
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 02/29] targer/riscv: Activate decodetree and implemnt LUI & AUIPC
2018-10-26 14:53 ` Bastian Koppelmann
@ 2018-10-26 15:42 ` Palmer Dabbelt
0 siblings, 0 replies; 60+ messages in thread
From: Palmer Dabbelt @ 2018-10-26 15:42 UTC (permalink / raw)
To: Bastian Koppelmann
Cc: richard.henderson, sagark, qemu-devel, peer.adelt,
Alistair Francis, Michael Clark
On Fri, 26 Oct 2018 07:53:17 PDT (-0700), Bastian Koppelmann wrote:
>
> On 10/26/18 3:58 PM, Richard Henderson wrote:
>> On 10/26/18 11:49 AM, Bastian Koppelmann wrote:
>>> I think you can pick up everything up to the RVC conversion which still needs
>>> the work suggested by Richard. Thanks, for picking it up :)
>> Even then I thought we were talking about splitting the RV64 insns
>> into a separate file, reducing the ifdefs, and renaming the arg-sets
>> to match the instruction formats described in the riscv spec.
>
>
> Yes, you are right I forgot that.
OK, so I think I'll hold off for a v3, then.
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree
2018-10-26 10:53 ` Bastian Koppelmann
@ 2018-10-27 6:20 ` Palmer Dabbelt
0 siblings, 0 replies; 60+ messages in thread
From: Palmer Dabbelt @ 2018-10-27 6:20 UTC (permalink / raw)
To: kbastian
Cc: sagark, richard.henderson, qemu-devel, peer.adelt,
Alistair.Francis, Michael Clark
On Fri, 26 Oct 2018 03:53:11 PDT (-0700), kbastian@mail.uni-paderborn.de wrote:
>
> On 10/25/18 12:21 AM, Palmer Dabbelt wrote:
>> On Sat, 20 Oct 2018 00:14:22 PDT (-0700),
>> kbastian@mail.uni-paderborn.de wrote:
>>> Hi,
>>>
>>> this patchset converts the RISC-V decoder to decodetree in three
>>> major steps:
>>>
>>> 1) Convert 32-bit instructions to decodetree [Patch 1-14]:
>>> Many of the gen_* functions are called by the decode functions
>>> for 16-bit
>>> and 32-bit functions. If we move translation code from the gen_*
>>> functions to the generated trans_* functions of decode-tree, we
>>> get a lot of
>>> duplication. Therefore, we mostly generate calls to the old gen_*
>>> function
>>> which are properly replaced after step 2).
>>>
>>> Each of the trans_ functions are grouped into files corresponding
>>> to their
>>> ISA extension, e.g. addi which is in RV32I is translated in the file
>>> 'trans_rvi.inc.c'.
>>>
>>> 2) Convert 16-bit instructions to decodetree [Patch 15-17]:
>>> All 16 bit instructions have a direct mapping to a 32 bit
>>> instruction. Thus,
>>> we convert the arguments in the 16 bit trans_ function to the
>>> arguments of
>>> the corresponding 32 bit instruction and call the 32 bit trans_
>>> function.
>>>
>>> 3) Remove old manual decoding in gen_* function [Patch 17-28]:
>>> this move all manual translation code into the trans_*
>>> instructions of
>>> decode tree, such that we can remove the old decode_* functions.
>>>
>>> the full tree can be found here:
>>> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v2
>>
>> Thanks!
>>
>> I dropped this on top of master and it appears I'm getting a bunch of
>> oops when trying to boot Linux. They're fairly far into the boot
>> process and may be a mistake on my end, I was just wondering if you'd
>> booted Linux?
>
> Are there non fatal oops in booting Linux? I only checked whether I
> could get a terminal on Fedora Linux.
Most of the stuff past early boot is, as if it's in a userspace process or
kernel thread you can recover. My system eventually made it to a shell, but
there was a lot of carnage on the way in -- most system services blew up.
I tested the same kernel+rootfs on master and it booted cleanly.
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 13/29] target/riscv: Convert RV32D insns to decodetree
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 13/29] target/riscv: Convert RV32D " Bastian Koppelmann
2018-10-23 8:21 ` Richard Henderson
@ 2018-10-31 10:44 ` Bastian Koppelmann
2018-10-31 10:47 ` Bastian Koppelmann
2018-10-31 17:21 ` Palmer Dabbelt
1 sibling, 2 replies; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-31 10:44 UTC (permalink / raw)
To: mjc, sagark, palmer
Cc: richard.henderson, peer.adelt, Alistair.Francis, qemu-devel
On 10/20/18 9:14 AM, Bastian Koppelmann wrote:
[...]
> +static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a, uint32_t insn)
> +{
> +#if defined(TARGET_RISCV64)
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_helper_fclass_d(t0, cpu_fpr[a->rs1]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +#else
> + gen_exception_illegal(ctx);
> +#endif
> + return true;
> +}
I'm a bit confused here. According to the spec fclass_d is a RV32F
instruction but according to the original qemu code it is not?
Cheers,
Bastian
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 13/29] target/riscv: Convert RV32D insns to decodetree
2018-10-31 10:44 ` Bastian Koppelmann
@ 2018-10-31 10:47 ` Bastian Koppelmann
2018-10-31 17:21 ` Palmer Dabbelt
1 sibling, 0 replies; 60+ messages in thread
From: Bastian Koppelmann @ 2018-10-31 10:47 UTC (permalink / raw)
To: mjc, sagark, palmer
Cc: richard.henderson, peer.adelt, Alistair.Francis, qemu-devel
On 10/31/18 11:44 AM, Bastian Koppelmann wrote:
>
> On 10/20/18 9:14 AM, Bastian Koppelmann wrote:
> [...]
>> +static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a,
>> uint32_t insn)
>> +{
>> +#if defined(TARGET_RISCV64)
>> + REQUIRE_FPU;
>> +
>> + TCGv t0 = tcg_temp_new();
>> + gen_helper_fclass_d(t0, cpu_fpr[a->rs1]);
>> + gen_set_gpr(a->rd, t0);
>> + tcg_temp_free(t0);
>> +#else
>> + gen_exception_illegal(ctx);
>> +#endif
>> + return true;
>> +}
>
>
> I'm a bit confused here. According to the spec fclass_d is a RV32F
> instruction but according to the original qemu code it is not?
I meant RV32D, of course...
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v2 13/29] target/riscv: Convert RV32D insns to decodetree
2018-10-31 10:44 ` Bastian Koppelmann
2018-10-31 10:47 ` Bastian Koppelmann
@ 2018-10-31 17:21 ` Palmer Dabbelt
1 sibling, 0 replies; 60+ messages in thread
From: Palmer Dabbelt @ 2018-10-31 17:21 UTC (permalink / raw)
To: Bastian Koppelmann
Cc: Michael Clark, sagark, richard.henderson, peer.adelt,
Alistair Francis, qemu-devel
On Wed, 31 Oct 2018 03:44:27 PDT (-0700), Bastian Koppelmann wrote:
>
> On 10/20/18 9:14 AM, Bastian Koppelmann wrote:
> [...]
>> +static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a, uint32_t insn)
>> +{
>> +#if defined(TARGET_RISCV64)
>> + REQUIRE_FPU;
>> +
>> + TCGv t0 = tcg_temp_new();
>> + gen_helper_fclass_d(t0, cpu_fpr[a->rs1]);
>> + gen_set_gpr(a->rd, t0);
>> + tcg_temp_free(t0);
>> +#else
>> + gen_exception_illegal(ctx);
>> +#endif
>> + return true;
>> +}
>
>
> I'm a bit confused here. According to the spec fclass_d is a RV32F
> instruction but according to the original qemu code it is not?
fclass.d is part of the D extension, see section 9.7 of the user spec. It
should be present for all base ISAs when the D extension is present. The above
code is incorrect, but appears to be trivially fixable.
It looks like master is also incorrect, which I'm somewhat surprised about.
This might explain a whole host of 32-bit glibc floating-point test suite
failures...
^ permalink raw reply [flat|nested] 60+ messages in thread
end of thread, other threads:[~2018-10-31 17:21 UTC | newest]
Thread overview: 60+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 01/29] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann
2018-10-25 16:38 ` Palmer Dabbelt
2018-10-25 16:54 ` Peter Maydell
2018-10-25 17:05 ` Palmer Dabbelt
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 02/29] targer/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2018-10-20 19:32 ` Richard Henderson
2018-10-25 16:58 ` Palmer Dabbelt
2018-10-26 10:49 ` Bastian Koppelmann
2018-10-26 13:58 ` Richard Henderson
2018-10-26 14:53 ` Bastian Koppelmann
2018-10-26 15:42 ` Palmer Dabbelt
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 03/29] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2018-10-20 19:34 ` Richard Henderson
2018-10-25 20:24 ` Palmer Dabbelt
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 04/29] target/riscv: Convert RVXI load/store " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 05/29] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 06/29] target/riscv: Convert RVXI fence " Bastian Koppelmann
2018-10-21 14:05 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 07/29] target/riscv: Convert RVXI csr " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 08/29] target/riscv: Convert RVXM " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 09/29] target/riscv: Convert RV32A " Bastian Koppelmann
2018-10-23 8:19 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 10/29] target/riscv: Convert RV64A " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 11/29] target/riscv: Convert RV32F " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 12/29] target/riscv: Convert RV64F " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 13/29] target/riscv: Convert RV32D " Bastian Koppelmann
2018-10-23 8:21 ` Richard Henderson
2018-10-31 10:44 ` Bastian Koppelmann
2018-10-31 10:47 ` Bastian Koppelmann
2018-10-31 17:21 ` Palmer Dabbelt
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 14/29] target/riscv: Convert RV64D " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 15/29] target/riscv: Convert RV priv " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 16/29] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2018-10-23 8:31 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 17/29] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2018-10-23 8:35 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 18/29] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2018-10-23 8:39 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 19/29] target/riscv: Remove gen_jalr() Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 20/29] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 21/29] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 22/29] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2018-10-23 8:46 ` Richard Henderson
2018-10-24 9:07 ` Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2018-10-23 8:53 ` Richard Henderson
2018-10-23 8:55 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 25/29] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 26/29] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2018-10-23 9:02 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 27/29] target/riscv: Remove gen_system() Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 28/29] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2018-10-23 9:04 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 29/29] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
2018-10-23 9:04 ` Richard Henderson
2018-10-24 22:21 ` [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Palmer Dabbelt
2018-10-26 10:53 ` Bastian Koppelmann
2018-10-27 6:20 ` Palmer Dabbelt
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