From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753813AbbIAU7Z (ORCPT ); Tue, 1 Sep 2015 16:59:25 -0400 Received: from gloria.sntech.de ([95.129.55.99]:34564 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751218AbbIAU7X (ORCPT ); Tue, 1 Sep 2015 16:59:23 -0400 From: Heiko Stuebner To: Yakir Yang Cc: Thierry Reding , Jingoo Han , Inki Dae , joe@perches.com, Kukjin Kim , Krzysztof Kozlowski , Mark Yao , Russell King , djkurtz@chromium.com, dianders@chromium.com, seanpaul@chromium.com, ajaynumb@gmail.com, Andrzej Hajda , Kyungmin Park , David Airlie , Gustavo Padovan , Andy Yan , Kumar Gala , Ian Campbell , Rob Herring , Pawel Moll , Kishon Vijay Abraham I , architt@codeaurora.org, robherring2@gmail.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY Date: Tue, 01 Sep 2015 22:58:59 +0200 Message-ID: <3270549.qIHk1CAA0Y@phil> User-Agent: KMail/4.14.1 (Linux/4.1.0-1-amd64; KDE/4.14.2; x86_64; ; ) In-Reply-To: <5077044.NGUl9gjQon@phil> References: <1441086371-24838-1-git-send-email-ykk@rock-chips.com> <1441087455-25533-1-git-send-email-ykk@rock-chips.com> <5077044.NGUl9gjQon@phil> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Yakir, small nit more below Am Dienstag, 1. September 2015, 18:51:16 schrieb Heiko Stuebner: > Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang: > > +- clocks: from common clock binding: handle to dp clock. > > + of memory mapped region. > > +- clock-names: from common clock binding: > > + Required elements: "sclk_dp" "sclk_dp_24m" > > + > > +- rockchip,grf: this soc should set GRF regs, so need get grf here. > > +- #phy-cells : from the generic PHY bindings, must be 0; > > + > > +Example: > > + > > +edp_phy: phy@ff770274 { > > edp_phy: edp-phy { > > > + compatilble = "rockchip,rk3288-dp-phy"; typo: compatible From mboxrd@z Thu Jan 1 00:00:00 1970 From: Heiko Stuebner Subject: Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY Date: Tue, 01 Sep 2015 22:58:59 +0200 Message-ID: <3270549.qIHk1CAA0Y@phil> References: <1441086371-24838-1-git-send-email-ykk@rock-chips.com> <1441087455-25533-1-git-send-email-ykk@rock-chips.com> <5077044.NGUl9gjQon@phil> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Return-path: In-Reply-To: <5077044.NGUl9gjQon@phil> Sender: linux-samsung-soc-owner@vger.kernel.org To: Yakir Yang Cc: Thierry Reding , Jingoo Han , Inki Dae , joe@perches.com, Kukjin Kim , Krzysztof Kozlowski , Mark Yao , Russell King , djkurtz@chromium.com, dianders@chromium.com, seanpaul@chromium.com, ajaynumb@gmail.com, Andrzej Hajda , Kyungmin Park , David Airlie , Gustavo Padovan , Andy Yan , Kumar Gala , Ian Campbell , Rob Herring , Pawel Moll , Kishon Vijay Abraham I , architt@codeaurora.org, robherring2@gmail.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel List-Id: devicetree@vger.kernel.org Hi Yakir, small nit more below Am Dienstag, 1. September 2015, 18:51:16 schrieb Heiko Stuebner: > Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang: > > +- clocks: from common clock binding: handle to dp clock. > > + of memory mapped region. > > +- clock-names: from common clock binding: > > + Required elements: "sclk_dp" "sclk_dp_24m" > > + > > +- rockchip,grf: this soc should set GRF regs, so need get grf here. > > +- #phy-cells : from the generic PHY bindings, must be 0; > > + > > +Example: > > + > > +edp_phy: phy@ff770274 { > > edp_phy: edp-phy { > > > + compatilble = "rockchip,rk3288-dp-phy"; typo: compatible From mboxrd@z Thu Jan 1 00:00:00 1970 From: heiko@sntech.de (Heiko Stuebner) Date: Tue, 01 Sep 2015 22:58:59 +0200 Subject: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY In-Reply-To: <5077044.NGUl9gjQon@phil> References: <1441086371-24838-1-git-send-email-ykk@rock-chips.com> <1441087455-25533-1-git-send-email-ykk@rock-chips.com> <5077044.NGUl9gjQon@phil> Message-ID: <3270549.qIHk1CAA0Y@phil> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Yakir, small nit more below Am Dienstag, 1. September 2015, 18:51:16 schrieb Heiko Stuebner: > Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang: > > +- clocks: from common clock binding: handle to dp clock. > > + of memory mapped region. > > +- clock-names: from common clock binding: > > + Required elements: "sclk_dp" "sclk_dp_24m" > > + > > +- rockchip,grf: this soc should set GRF regs, so need get grf here. > > +- #phy-cells : from the generic PHY bindings, must be 0; > > + > > +Example: > > + > > +edp_phy: phy at ff770274 { > > edp_phy: edp-phy { > > > + compatilble = "rockchip,rk3288-dp-phy"; typo: compatible