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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id u5sm2746985pfu.198.2020.05.15.14.26.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 May 2020 14:26:46 -0700 (PDT) Subject: Re: [PATCH] target/arm: Allow user-mode code to write CPSR.E via MSR To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20200515185026.30080-1-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <327074ea-2c2f-ad45-b53f-1c4dcb69f9bf@linaro.org> Date: Fri, 15 May 2020 14:26:44 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <20200515185026.30080-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/15/20 11:50 AM, Peter Maydell wrote: > Using the MSR instruction to write to CPSR.E is deprecated, but it is > required to work from any mode including unprivileged code. We were > incorrectly forbidding usermode code from writing it because > CPSR_USER did not include the CPSR_E bit. > > We use CPSR_USER in only three places: > * as the mask of what to allow userspace MSR to write to CPSR > * when deciding what bits a linux-user signal-return should be > able to write from the sigcontext structure > * in target_user_copy_regs() when we set up the initial > registers for the linux-user process > > In the first two cases not being able to update CPSR.E is a > bug, and in the third case it doesn't matter because CPSR.E > is always 0 there. So we can fix both bugs by adding CPSR_E > to CPSR_EXEC. Wrong variable in description here. Otherwise, Reviewed-by: Richard Henderson r~ > > (The recommended way to change CPSR.E is to use the 'SETEND' > instruction, which we do correctly allow from usermode code.) > > Signed-off-by: Peter Maydell > --- > Bug reported on IRC. Quick-and-dirty test case at: > https://people.linaro.org/~peter.maydell/msr-setend.c > > target/arm/cpu.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 5d995368d4f..677584e5da0 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1230,7 +1230,7 @@ void pmu_init(ARMCPU *cpu); > #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ > | CPSR_NZCV) > /* Bits writable in user mode. */ > -#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) > +#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) > /* Execution state bits. MRS read as zero, MSR writes ignored. */ > #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) > >