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Wed, 10 Jun 2020 08:06:50 +0000 From: Bertrand Marquis To: Marc Zyngier Subject: Re: Keystone Issue Thread-Topic: Keystone Issue Thread-Index: AQHWOBaIAfEL/lLkK0WiNSn4kZcZc6jDwRQAgAAfVYCAACZwgIACvmKAgABfPYCAAA+JgIAA6NEAgAAP9wCAAAJxgIAAEuGAgAAfEwCAAGmFAIAAh2UAgABV34CAAFCtAIAAAUSAgAADZQCAAAGKgIAAJpOAgABE7QCABAZcAIAAQRIAgAA9oACAAXYtAIAAD3sAgAAFaoCAABUzgIAAB/uAgAAD1ICAAPCKAA== Date: Wed, 10 Jun 2020 08:06:50 +0000 Message-ID: <32FA85C2-7685-49D2-875B-9FA1C138C92A@arm.com> References: <8C6A23AE-6C2B-411F-ACAD-F5574211E8ED@arm.com> <14244e49-e1ac-a29d-bbd9-bd4c202bf186@xen.org> <77006AAF-BC3B-4C6E-BDFC-577CF87DE64E@arm.com> <99E77330-049F-4471-ABF9-13F9AB4E95B5@arm.com> <363A05E0-61C6-4AE4-9C84-EEAC466989D8@arm.com> <03607739-A4FF-486A-899A-F5F36870225A@arm.com> <2ec6255c-9d28-92e7-bd0a-59edb9fc078a@xen.org> <6033f9cecbf10f50f4a713ce52105426@kernel.org> In-Reply-To: <6033f9cecbf10f50f4a713ce52105426@kernel.org> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: Authentication-Results-Original: kernel.org; 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DIR:OUT; SFP:1101; X-MS-Office365-Filtering-Correlation-Id-Prvs: 7b025cdf-801b-4b4b-cd6c-08d80d153b17 X-Forefront-PRVS: 0430FA5CB7 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: m/s24uxI07p4jZdewxC5+2HyLKAdQezj1KYOI3GI4/1OQRt5lRVuQ5f7gbSY5fy/XVfSg7YNgqz3/8WExgl/FGcn0nKr743yyiSINSGG6xgIjxOaKDP1FkDjvGA1vY5BobQYBPNPG0coSV15lnGBS+PatzWslLClTV8G2rmrMMjjiTESptYmuhw3O/5dk/5iIyWR0TiwU91kPk1tXsseQC504YQuiiYzuQf9NTvSzhgTqTTZ1XyRUQkGc6k2ziVpXyYbo7Xurd4jTmr99xgCklRIbktFsXEk/HrkhmVGdm70cLnCs4PJkzRA1Kmiy/LDJDWLhB6wd5zcLF9TzLcj/Bj25UQP+hSI5gj6LTywdVuamVw9BNxZrrkSxvq+xgqVdo8op3OOW6i7c++Sw6/QZw== X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jun 2020 08:06:58.4239 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7ddc80b5-908b-420b-d251-08d80d153f8f X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0801MB1768 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel , nd , Stefano Stabellini , Julien Grall , CodeWiz2280 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Hi, > On 9 Jun 2020, at 18:45, Marc Zyngier wrote: >=20 > Hi Julien, >=20 > On 2020-06-09 18:32, Julien Grall wrote: >> (+ Marc) >> On 09/06/2020 18:03, Bertrand Marquis wrote: >>> Hi >>>> On 9 Jun 2020, at 16:47, Julien Grall wrote: >>>> On 09/06/2020 16:28, Bertrand Marquis wrote: >>>>> Hi, >>>>>> On 9 Jun 2020, at 15:33, CodeWiz2280 wrote: >>>>>> There does appear to be a secondary (CIC) controller that can forwar= d >>>>>> events to the GIC-400 and EDMA controllers for the keystone 2 family= . >>>>>> Admittedly, i'm not sure how it is being used with regards to the >>>>>> peripherals. I only see mention of the GIC-400 parent for the devic= es >>>>>> in the device tree. Maybe Bertrand has a better idea on whether any >>>>>> peripherals go through the CIC first? I see that gic_interrupt () >>>>>> fires once in Xen, which calls doIRQ to push out the virtual interru= pt >>>>>> to the dom0 kernel. The dom0 kernel then handles the interrupt and >>>>>> returns, but gic_interrupt() never fires again in Xen. >>>>> I do not remember of any CIC but the behaviour definitely look like a= n interrupt acknowledge problem. >>>>> Could you try the following: >>>>> --- a/xen/arch/arm/gic-v2.c >>>>> +++ b/xen/arch/arm/gic-v2.c >>>>> @@ -667,6 +667,9 @@ static void gicv2_guest_irq_end(struct irq_desc *= desc) >>>>> /* Lower the priority of the IRQ */ >>>>> gicv2_eoi_irq(desc); >>>>> /* Deactivation happens in maintenance interrupt / via GICV */ >>>>> + >>>>> + /* Test for Keystone2 */ >>>>> + gicv2_dir_irq(desc); >>>>> } >>>>> I think the problem I had was related to the vgic not deactivating pr= operly the interrupt. >>>> Are you suggesting the guest EOI is not properly forwarded to the hard= ware when LR.HW is set? If so, this could possibly be workaround in Xen by = raising a maintenance interrupt every time a guest EOI an interrupt. >>> Agree the maintenance interrupt would definitely be the right solution >> I would like to make sure we aren't missing anything in Xen first. >> From what you said, you have encountered this issue in the past with a >> different hypervisor. So it doesn't look like to be Xen related. >> Was there any official statement from TI? If not, can we try to get >> some input from them first? >> @Marc, I know you dropped 32-bit support in KVM recently :). Although, >=20 > Yes! Victory is mine! Freedom from the shackles of 32bit, at last! :D >=20 >> I was wondering if you heard about any potential issue with guest EOI >> not forwarded to the host. This is on TI Keystone (Cortex A-15). >=20 > Not that I know of. A-15 definitely works (TC2, Tegra-K1, Calxeda Midway = all run just fine with guest EOI), and GIC-400 is a pretty solid piece of k= it (it is just sloooooow...). >=20 > Thinking of it, you would see something like that if the GIC was seeing t= he writes coming from the guest as secure instead of NS (cue the early firm= ware on XGene that exposed the wrong side of GIC-400). >=20 > Is there some kind of funky bridge between the CPU and the GIC? Yes the behaviour I had was coherent with the GIC seeing the processor in s= ecure mode and not in non secure hence making the VGIC ack non functional. So the only way to solve this is actually to do the interrupt deactivate in= side Xen (using a maintenance interrupt). I remember that I also had to do something specific for the configuration o= f edge/level and priorities to have an almost proper behaviour. Sadly I have no access to the code anymore, so I would need to guess back w= hat that was.. Bertrand >=20 > M. > --=20 > Jazz is not dead. It just smells funny...