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From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
To: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
	horms@verge.net.au, magnus.damm@gmail.com
Cc: linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH 1/2] arm64: dts: renesas: r8a77990: Revise the cache controller node
Date: Wed, 25 Apr 2018 19:15:31 +0300	[thread overview]
Message-ID: <32b91531-20a4-4831-faaf-e03a35238db3@cogentembedded.com> (raw)
In-Reply-To: <1524644410-12465-2-git-send-email-yoshihiro.shimoda.uh@renesas.com>

On 04/25/2018 11:20 AM, Yoshihiro Shimoda wrote:

> The cache controller node should not have unit-addresses and reg
> properties. So, this patch revises them.

   Removes?

> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a77990.dtsi | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> index 3a19b9e..ba902a2 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> @@ -27,9 +27,8 @@
>  			enable-method = "psci";
>  		};
>  
> -		L2_CA53: cache-controller@0 {
> +		L2_CA53: cache-controller-0 {
>  			compatible = "cache";
> -			reg = <0>;
>  			power-domains = <&sysc 21>;
>  			cache-unified;
>  			cache-level = <2>;
> 

MBR, Sergei

  parent reply	other threads:[~2018-04-25 16:15 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-25  8:20 [PATCH 0/2] arm64: dts: renesas: r8a77990: Revise some nodes Yoshihiro Shimoda
2018-04-25  8:20 ` [PATCH 1/2] arm64: dts: renesas: r8a77990: Revise the cache controller node Yoshihiro Shimoda
2018-04-25  9:13   ` Geert Uytterhoeven
2018-04-26  8:43     ` Simon Horman
2018-04-25 16:15   ` Sergei Shtylyov [this message]
2018-04-25  8:20 ` [PATCH 2/2] arm64: dts: renesas: r8a77990: Revise the psci node Yoshihiro Shimoda
2018-04-25  9:13   ` Geert Uytterhoeven
2018-04-26  8:41     ` Simon Horman

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