From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:23694 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729982AbgFHOZV (ORCPT ); Mon, 8 Jun 2020 10:25:21 -0400 Subject: Re: [kvm-unit-tests PATCH v8 02/12] s390x: Move control register bit definitions and add AFP to them References: <1591603981-16879-1-git-send-email-pmorel@linux.ibm.com> <1591603981-16879-3-git-send-email-pmorel@linux.ibm.com> From: Pierre Morel Message-ID: <33625241-be13-f823-a3bb-27f7daca2934@linux.ibm.com> Date: Mon, 8 Jun 2020 16:25:13 +0200 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-s390-owner@vger.kernel.org List-ID: To: Thomas Huth , kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, frankja@linux.ibm.com, david@redhat.com, cohuck@redhat.com On 2020-06-08 10:45, Thomas Huth wrote: > On 08/06/2020 10.12, Pierre Morel wrote: >> While adding the definition for the AFP-Register control bit, move all >> existing definitions for CR0 out of the C zone to the assmbler zone to >> keep the definitions concerning CR0 together. >> >> Signed-off-by: Pierre Morel >> Reviewed-by: David Hildenbrand >> Reviewed-by: Janosch Frank >> Reviewed-by: Cornelia Huck >> --- >> lib/s390x/asm/arch_def.h | 11 ++++++----- >> s390x/cstart64.S | 2 +- >> 2 files changed, 7 insertions(+), 6 deletions(-) >> >> diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h >> index 5388114..12045ff 100644 >> --- a/lib/s390x/asm/arch_def.h >> +++ b/lib/s390x/asm/arch_def.h >> @@ -19,17 +19,18 @@ >> >> #define PSW_EXCEPTION_MASK (PSW_MASK_EA | PSW_MASK_BA) >> >> +#define CR0_EXTM_SCLP 0x0000000000000200UL >> +#define CR0_EXTM_EXTC 0x0000000000002000UL >> +#define CR0_EXTM_EMGC 0x0000000000004000UL >> +#define CR0_EXTM_MASK 0x0000000000006200UL >> +#define CR0_AFP_REG_CRTL 0x0000000000040000UL >> + >> #ifndef __ASSEMBLER__ >> struct psw { >> uint64_t mask; >> uint64_t addr; >> }; >> >> -#define CR0_EXTM_SCLP 0x0000000000000200UL >> -#define CR0_EXTM_EXTC 0x0000000000002000UL >> -#define CR0_EXTM_EMGC 0x0000000000004000UL >> -#define CR0_EXTM_MASK 0x0000000000006200UL >> - >> struct lowcore { >> uint8_t pad_0x0000[0x0080 - 0x0000]; /* 0x0000 */ >> uint32_t ext_int_param; /* 0x0080 */ >> diff --git a/s390x/cstart64.S b/s390x/cstart64.S >> index 6e85635..b50c42c 100644 >> --- a/s390x/cstart64.S >> +++ b/s390x/cstart64.S >> @@ -214,4 +214,4 @@ svc_int_psw: >> .quad PSW_EXCEPTION_MASK, svc_int >> initial_cr0: >> /* enable AFP-register control, so FP regs (+BFP instr) can be used */ >> - .quad 0x0000000000040000 >> + .quad CR0_AFP_REG_CRTL >> > > Acked-by: Thomas Huth > Thanks, Pierre -- Pierre Morel IBM Lab Boeblingen