From: Geert Uytterhoeven <geert@linux-m68k.org> To: Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Sagar Kadam <sagar.kadam@sifive.com> Cc: Rob Herring <robh+dt@kernel.org>, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Geert Uytterhoeven <geert@linux-m68k.org>, Rob Herring <robh@kernel.org> Subject: [PATCH v3 2/2] dt-bindings: interrupt-controller: sifive,plic: Group interrupt tuples Date: Fri, 17 Dec 2021 13:34:04 +0100 [thread overview] Message-ID: <33c1526be595c933ddf7f2583fdb5e23e69968a7.1639744106.git.geert@linux-m68k.org> (raw) In-Reply-To: <cover.1639744106.git.geert@linux-m68k.org> To improve human readability and enable automatic validation, the tuples in "interrupts-extended" properties should be grouped using angle brackets. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Rob Herring <robh@kernel.org> --- v3: - Add Reviewed-by, v2: - Split in two patches. --- .../interrupt-controller/sifive,plic-1.0.0.yaml | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 0c6687511457413e..52a3bc31a2c19c5d 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -91,12 +91,11 @@ examples: #interrupt-cells = <1>; compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; interrupt-controller; - interrupts-extended = < - &cpu0_intc 11 - &cpu1_intc 11 &cpu1_intc 9 - &cpu2_intc 11 &cpu2_intc 9 - &cpu3_intc 11 &cpu3_intc 9 - &cpu4_intc 11 &cpu4_intc 9>; + interrupts-extended = <&cpu0_intc 11>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>; reg = <0xc000000 0x4000000>; riscv,ndev = <10>; }; -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Geert Uytterhoeven <geert@linux-m68k.org> To: Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Sagar Kadam <sagar.kadam@sifive.com> Cc: Rob Herring <robh+dt@kernel.org>, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Geert Uytterhoeven <geert@linux-m68k.org>, Rob Herring <robh@kernel.org> Subject: [PATCH v3 2/2] dt-bindings: interrupt-controller: sifive, plic: Group interrupt tuples Date: Fri, 17 Dec 2021 13:34:04 +0100 [thread overview] Message-ID: <33c1526be595c933ddf7f2583fdb5e23e69968a7.1639744106.git.geert@linux-m68k.org> (raw) In-Reply-To: <cover.1639744106.git.geert@linux-m68k.org> To improve human readability and enable automatic validation, the tuples in "interrupts-extended" properties should be grouped using angle brackets. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Rob Herring <robh@kernel.org> --- v3: - Add Reviewed-by, v2: - Split in two patches. --- .../interrupt-controller/sifive,plic-1.0.0.yaml | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 0c6687511457413e..52a3bc31a2c19c5d 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -91,12 +91,11 @@ examples: #interrupt-cells = <1>; compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; interrupt-controller; - interrupts-extended = < - &cpu0_intc 11 - &cpu1_intc 11 &cpu1_intc 9 - &cpu2_intc 11 &cpu2_intc 9 - &cpu3_intc 11 &cpu3_intc 9 - &cpu4_intc 11 &cpu4_intc 9>; + interrupts-extended = <&cpu0_intc 11>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>; reg = <0xc000000 0x4000000>; riscv,ndev = <10>; }; -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-12-17 12:34 UTC|newest] Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-12-17 12:34 [PATCH v3 0/2] dt-bindings: interrupt-controller: sifive,plic: Miscellaneous improvements Geert Uytterhoeven 2021-12-17 12:34 ` [PATCH v3 0/2] dt-bindings: interrupt-controller: sifive, plic: " Geert Uytterhoeven 2021-12-17 12:34 ` [PATCH v3 1/2] dt-bindings: interrupt-controller: sifive,plic: Fix number of interrupts Geert Uytterhoeven 2021-12-17 12:34 ` [PATCH v3 1/2] dt-bindings: interrupt-controller: sifive, plic: " Geert Uytterhoeven 2021-12-17 12:47 ` [PATCH v3 1/2] dt-bindings: interrupt-controller: sifive,plic: " Anup Patel 2021-12-17 12:47 ` Anup Patel 2021-12-17 12:34 ` Geert Uytterhoeven [this message] 2021-12-17 12:34 ` [PATCH v3 2/2] dt-bindings: interrupt-controller: sifive, plic: Group interrupt tuples Geert Uytterhoeven
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