From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rich Felker Date: Fri, 20 May 2016 02:53:04 +0000 Subject: [PATCH v2 04/12] of: add J-Core timer bindings Message-Id: <3460e061e18c6355407b585a8394b8da8cbd9fc8.1463708766.git.dalias@libc.org> List-Id: References: In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org Cc: Ian Campbell , Kumar Gala , Mark Rutland , Pawel Moll , Rob Herring Signed-off-by: Rich Felker --- .../devicetree/bindings/timer/jcore,pit.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/jcore,pit.txt diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt new file mode 100644 index 0000000..d53759a --- /dev/null +++ b/Documentation/devicetree/bindings/timer/jcore,pit.txt @@ -0,0 +1,28 @@ +J-Core Programmable Interval Timer and Realtime Clock + +Required properties: + +- compatible: Must be "jcore,pit". + +- reg: Memory region for timer/rtc registers. + +- interrupts: An interrupt to assign for the timer. The actual pit + core is integrated with the aic and allows the timer interrupt + assignment to be programmed by software, but this property is + required in order to reserve an interrupt number that doesn't + conflict with other devices. + +Optional properties: + +- cpu-offset: For SMP, the per-cpu offset to the local timer + programming memory range. + + +Example: + +timer { + compatible = "jcore,pit"; + reg = < 0x200 0x30 >; + cpu-offset = < 0x300 >; + interrupts = < 0x48 >; +}; -- 2.8.1