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Thu, 26 Nov 2020 20:41:34 -0800 (PST) X-Google-Smtp-Source: ABdhPJzhpNenukEglOX6vUcdBbv6y6M2t/As72V7OPnofNLR+jiE8plCnXMlM63eOtg3eMoWQXEjvA== X-Received: by 2002:aa7:c058:: with SMTP id k24mr5694961edo.263.1606452094517; Thu, 26 Nov 2020 20:41:34 -0800 (PST) Received: from [192.168.10.118] ([93.56.170.5]) by smtp.gmail.com with ESMTPSA id h22sm4213231ejt.21.2020.11.26.20.41.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 26 Nov 2020 20:41:33 -0800 (PST) Subject: Re: [PATCH 4/8] arm: Synchronize CPU on PSCI on To: Alexander Graf , Peter Maydell References: <20201126213600.40654-1-agraf@csgraf.de> <20201126213600.40654-5-agraf@csgraf.de> <785c216b-d4b5-b65f-1ddf-4c6374b72ece@csgraf.de> <284d0cd2-268b-b937-3a6e-d074ce28baee@csgraf.de> From: Paolo Bonzini Message-ID: <3594db71-c72f-2946-ffa5-47da737900c6@redhat.com> Date: Fri, 27 Nov 2020 05:41:32 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.4.0 MIME-Version: 1.0 In-Reply-To: <284d0cd2-268b-b937-3a6e-d074ce28baee@csgraf.de> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=pbonzini@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=63.128.21.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Richard Henderson , QEMU Developers , Cameron Esfahani , Roman Bolshakov , qemu-arm Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 27/11/20 00:32, Alexander Graf wrote: > > On 26.11.20 23:26, Peter Maydell wrote: >> On Thu, 26 Nov 2020 at 22:16, Alexander Graf wrote: >>> cpu_synchronize_state() sets the CPU registers into "dirty" state which >>> means that env now holds the current copy. On the next entry, we then >>> sync them back into HVF. >>> >>> Without the cpu_synchronize_state() call, HVF never knows that the CPU >>> state is actually dirty. I guess it could as well live in cpu_reset() >>> somewhere, but we have to get the state switched over to dirty one way >>> or another. >>> >>> One interesting thing to note here is that the CPU actually comes up in >>> "dirty" after init. But init is done on realization already. I'm not >>> sure why we lose the dirty state in between that and the reset. >> Yeah, it sounds like you need to figure out where the dirty >> to not-dirty transitions ought to be happening rather than >> just fudging things here... > > > When init is complete (system is ready to launch), the CPU state is > pushed to HVF and dirty is set to false. So by design, a normal > cpu_reset doesn't have vcpu_dirty set. > > How about this patch instead? > > Alex > > > > commit 8c61bc4d613b01e251b6b2f892d1a55a333c6e37 > Author: Alexander Graf > Date:   Thu Nov 26 02:47:09 2020 +0100 > >     hvf: arm: Mark CPU as dirty on reset > >     When clearing internal state of a CPU, we should also make sure > that HVF >     knows about it and can push the new values down to vcpu state. > >     Make sure that with HVF enabled, we tell it that it should synchronize >     CPU state on next entry after a reset. > >     This fixes PSCI handling, because now newly pushed state such as X0 > and >     PC on remote CPU enablement also get pushed into HVF. > >     Signed-off-by: Alexander Graf > > diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c > index b75f813b40..a49a5b32e6 100644 > --- a/target/arm/arm-powerctl.c > +++ b/target/arm/arm-powerctl.c > @@ -15,6 +15,7 @@ >  #include "arm-powerctl.h" >  #include "qemu/log.h" >  #include "qemu/main-loop.h" > +#include "sysemu/hw_accel.h" > >  #ifndef DEBUG_ARM_POWERCTL >  #define DEBUG_ARM_POWERCTL 0 > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index db6f7c34ed..9a501ea4bd 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -411,6 +411,8 @@ static void arm_cpu_reset(DeviceState *dev) >  #ifndef CONFIG_USER_ONLY >      if (kvm_enabled()) { >          kvm_arm_reset_vcpu(cpu); > +    } else if (hvf_enabled()) { > +        s->vcpu_dirty = true; >      } >  #endif > Why only for HVF and only for ARM? For example hax_init_vcpu and whpx_init_vcpu both set s->vcpu_dirty; should you just set it unconditionally in cpu_common_reset? Thanks, Paolo