From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mproxy.gmail.com (rproxy.gmail.com [64.233.170.194]) by ozlabs.org (Postfix) with ESMTP id 467F22BDB3 for ; Sun, 10 Oct 2004 05:40:32 +1000 (EST) Received: by mproxy.gmail.com with SMTP id 76so134724rnk for ; Sat, 09 Oct 2004 12:40:31 -0700 (PDT) Message-ID: <35fb2e5904100912409628a94@mail.gmail.com> Date: Sat, 9 Oct 2004 20:40:31 +0100 From: Jon Masters To: Andrei Konovalov In-Reply-To: <4166CCF5.7040705@ru.mvista.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII References: <4166CCF5.7040705@ru.mvista.com> Cc: akpm@osdl.org, linuxppc-embedded@ozlabs.org Subject: Re: [PATCH][PPC32] Xilinx ML300 board support (very basic) Reply-To: jonathan@jonmasters.org List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Fri, 08 Oct 2004 21:23:01 +0400, Andrei Konovalov wrote: > Adds minimal Xilinx ML300 board support (enough to boot with ramdisk). > The only peripheral devices supported are 16x50 compatible UARTs. > > Signed-off-by: Andrei Konovalov I'll test this if I get chance soon. > /* > - * At one point, we were getting machine checks. Linux was not > - * invalidating the data cache before it was enabled. The > - * following code was added to do that. Soon after we had done > - * that, we found the real reasons for the machine checks. I've > - * run the kernel a few times with the following code > - * temporarily removed without any apparent problems. However, > - * I objdump'ed the kernel and boot code and found out that > - * there were no other dccci's anywhere, so I put the code back > - * in and have been reluctant to remove it. It seems safer to > - * just leave it here. > + * Invalidate the data cache if the data cache is turned off. > + * - The 405 core does not invalidate the data cache on power-up > + * or reset but does turn off the data cache. We cannot assume > + * that the cache contents are valid. > + * - If the data cache is turned on this must have been done by > + * a bootloader and we assume that the cache contents are > + * valid. > */ Er...the caveat about the MSR is still worth noting - I had this problem and for a while couldn't figure out why the fsck the board wouldn't come up with cacheing enabled (I've written patches for debugging that turn off various cacheing by modifying the pte macros, etc.) and *still* believe we're not clean from unwanted machine checks here. Just FYI. > +/* We don't need anything mapped. Size of zero will accomplish that. */ > +#define PPC4xx_ONB_IO_PADDR 0u > +#define PPC4xx_ONB_IO_VADDR 0u > +#define PPC4xx_ONB_IO_SIZE 0u :-) > +* This program is free software; you can redistribute it and/or modify it > +* under the terms of the GNU General Public License as published by the > +* Free Software Foundation; either version 2 of the License, or (at your > +* option) any later version. ...and then: > +* Xilinx hardware products are not intended for use in life support > +* appliances, devices, or systems. Use in such applications is > +* expressly prohibited. I've always loved it how Xilinx GPL disclaimers cunningly aren't. They might want to wake up and smell the coffee at some point. Andrei, you'll want to modify the ML300 xparameters stuff to allow it's location to be specified by a parameter. People who want to use (ewww, spit) autogenerated Xilinx xparameters.h from their EDK will probably also want to choose where it lives. > + * arch/ppc/syslib/xilinx_pic.c > + * > + * Interrupt controller driver for Xilinx Virtex-II Pro. Nice. Better than the original and now handles different types of interrupts. Jon.