From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751817AbeCUIxQ (ORCPT ); Wed, 21 Mar 2018 04:53:16 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.154.211]:54119 "EHLO 9pmail.ess.barracuda.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751514AbeCUIw6 (ORCPT ); Wed, 21 Mar 2018 04:52:58 -0400 Subject: Re: [PATCH v3] MIPS: ralink: fix booting on mt7621 To: NeilBrown , John Crispin , Ralf Baechle , James Hogan CC: , References: <87efkf9z0o.fsf@notabene.neil.brown.name> <87605r9mwf.fsf@notabene.neil.brown.name> <871sge872l.fsf@notabene.neil.brown.name> From: Matt Redfearn Message-ID: <364419e1-947b-2a87-526d-ccf3e77beb16@mips.com> Date: Wed, 21 Mar 2018 08:52:54 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <871sge872l.fsf@notabene.neil.brown.name> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [192.168.155.41] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1521622370-321457-2567-40066-1 X-BESS-VER: 2018.3-r1803192001 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.191261 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 21/03/18 03:02, NeilBrown wrote: > > Since commit 3af5a67c86a3 ("MIPS: Fix early CM probing") the MT7621 > has not been able to boot. > > This patched caused mips_cm_probe() to be called before > mt7621.c::proc_soc_init(). > > prom_soc_init() has a comment explaining that mips_cm_probe() > "wipes out the bootloader config" and means that configuration > registers are no longer available. It has some code to re-enable > this config. > > Before this re-enable code is run, the sysc register cannot be > read, so when SYSC_REG_CHIP_NAME0 is read, a garbage value > is returned and panic() is called. > > If we move the config-repair code to the top of prom_soc_init(), > the registers can be read and boot can proceed. > > Very occasionally, the first register read after the reconfiguration > returns garbage. So I added a call to __sync(). > > Fixes: 3af5a67c86a3 ("MIPS: Fix early CM probing") > Signed-off-by: NeilBrown Looks good to me Reviewed-by: Matt Redfearn > --- > arch/mips/ralink/mt7621.c | 42 ++++++++++++++++++++++-------------------- > 1 file changed, 22 insertions(+), 20 deletions(-) > > diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c > index 1b274742077d..d2718de60b9b 100644 > --- a/arch/mips/ralink/mt7621.c > +++ b/arch/mips/ralink/mt7621.c > @@ -170,6 +170,28 @@ void prom_soc_init(struct ralink_soc_info *soc_info) > u32 n1; > u32 rev; > > + /* Early detection of CMP support */ > + mips_cm_probe(); > + mips_cpc_probe(); > + > + if (mips_cps_numiocu(0)) { > + /* > + * mips_cm_probe() wipes out bootloader > + * config for CM regions and we have to configure them > + * again. This SoC cannot talk to pamlbus devices > + * witout proper iocu region set up. > + * > + * FIXME: it would be better to do this with values > + * from DT, but we need this very early because > + * without this we cannot talk to pretty much anything > + * including serial. > + */ > + write_gcr_reg0_base(MT7621_PALMBUS_BASE); > + write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE | > + CM_GCR_REGn_MASK_CMTGT_IOCU0); > + __sync(); > + } > + > n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); > n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); > > @@ -194,26 +216,6 @@ void prom_soc_init(struct ralink_soc_info *soc_info) > > rt2880_pinmux_data = mt7621_pinmux_data; > > - /* Early detection of CMP support */ > - mips_cm_probe(); > - mips_cpc_probe(); > - > - if (mips_cps_numiocu(0)) { > - /* > - * mips_cm_probe() wipes out bootloader > - * config for CM regions and we have to configure them > - * again. This SoC cannot talk to pamlbus devices > - * witout proper iocu region set up. > - * > - * FIXME: it would be better to do this with values > - * from DT, but we need this very early because > - * without this we cannot talk to pretty much anything > - * including serial. > - */ > - write_gcr_reg0_base(MT7621_PALMBUS_BASE); > - write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE | > - CM_GCR_REGn_MASK_CMTGT_IOCU0); > - } > > if (!register_cps_smp_ops()) > return; > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from 9pmail.ess.barracuda.com ([64.235.154.211]:49677 "EHLO 9pmail.ess.barracuda.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S23990439AbeCUIw6ErPLX (ORCPT ); Wed, 21 Mar 2018 09:52:58 +0100 Subject: Re: [PATCH v3] MIPS: ralink: fix booting on mt7621 References: <87efkf9z0o.fsf@notabene.neil.brown.name> <87605r9mwf.fsf@notabene.neil.brown.name> <871sge872l.fsf@notabene.neil.brown.name> From: Matt Redfearn Message-ID: <364419e1-947b-2a87-526d-ccf3e77beb16@mips.com> Date: Wed, 21 Mar 2018 08:52:54 +0000 MIME-Version: 1.0 In-Reply-To: <871sge872l.fsf@notabene.neil.brown.name> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Return-Path: Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-subscribe: List-owner: List-post: List-archive: To: NeilBrown , John Crispin , Ralf Baechle , James Hogan Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Message-ID: <20180321085254.ZZ_Sn9XtBohUNdB5l_f4_e_Vo13CJkRXclVODp7oq4E@z> On 21/03/18 03:02, NeilBrown wrote: > > Since commit 3af5a67c86a3 ("MIPS: Fix early CM probing") the MT7621 > has not been able to boot. > > This patched caused mips_cm_probe() to be called before > mt7621.c::proc_soc_init(). > > prom_soc_init() has a comment explaining that mips_cm_probe() > "wipes out the bootloader config" and means that configuration > registers are no longer available. It has some code to re-enable > this config. > > Before this re-enable code is run, the sysc register cannot be > read, so when SYSC_REG_CHIP_NAME0 is read, a garbage value > is returned and panic() is called. > > If we move the config-repair code to the top of prom_soc_init(), > the registers can be read and boot can proceed. > > Very occasionally, the first register read after the reconfiguration > returns garbage. So I added a call to __sync(). > > Fixes: 3af5a67c86a3 ("MIPS: Fix early CM probing") > Signed-off-by: NeilBrown Looks good to me Reviewed-by: Matt Redfearn > --- > arch/mips/ralink/mt7621.c | 42 ++++++++++++++++++++++-------------------- > 1 file changed, 22 insertions(+), 20 deletions(-) > > diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c > index 1b274742077d..d2718de60b9b 100644 > --- a/arch/mips/ralink/mt7621.c > +++ b/arch/mips/ralink/mt7621.c > @@ -170,6 +170,28 @@ void prom_soc_init(struct ralink_soc_info *soc_info) > u32 n1; > u32 rev; > > + /* Early detection of CMP support */ > + mips_cm_probe(); > + mips_cpc_probe(); > + > + if (mips_cps_numiocu(0)) { > + /* > + * mips_cm_probe() wipes out bootloader > + * config for CM regions and we have to configure them > + * again. This SoC cannot talk to pamlbus devices > + * witout proper iocu region set up. > + * > + * FIXME: it would be better to do this with values > + * from DT, but we need this very early because > + * without this we cannot talk to pretty much anything > + * including serial. > + */ > + write_gcr_reg0_base(MT7621_PALMBUS_BASE); > + write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE | > + CM_GCR_REGn_MASK_CMTGT_IOCU0); > + __sync(); > + } > + > n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); > n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); > > @@ -194,26 +216,6 @@ void prom_soc_init(struct ralink_soc_info *soc_info) > > rt2880_pinmux_data = mt7621_pinmux_data; > > - /* Early detection of CMP support */ > - mips_cm_probe(); > - mips_cpc_probe(); > - > - if (mips_cps_numiocu(0)) { > - /* > - * mips_cm_probe() wipes out bootloader > - * config for CM regions and we have to configure them > - * again. This SoC cannot talk to pamlbus devices > - * witout proper iocu region set up. > - * > - * FIXME: it would be better to do this with values > - * from DT, but we need this very early because > - * without this we cannot talk to pretty much anything > - * including serial. > - */ > - write_gcr_reg0_base(MT7621_PALMBUS_BASE); > - write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE | > - CM_GCR_REGn_MASK_CMTGT_IOCU0); > - } > > if (!register_cps_smp_ops()) > return; >