From mboxrd@z Thu Jan 1 00:00:00 1970 From: Michal Simek Date: Wed, 29 Apr 2015 10:35:35 +0200 Subject: [U-Boot] [PATCH v2] armv8: caches: Added routine to set non cacheable region Message-ID: <36afeeb6504576ba92012c597d24b81517b085c7.1430296529.git.michal.simek@xilinx.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- Changes in v2: - Fix patch subject (remove addional zzz from v1) - Remove armv8: caches: Disable dcache after flush patch from this series based on the talk with Mark Rutland (patch is not needed anymore) arch/arm/cpu/armv8/cache_v8.c | 23 +++++++++++++++++++++++ arch/arm/include/asm/system.h | 28 ++++++++++++++++++---------- 2 files changed, 41 insertions(+), 10 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index c5ec5297cd39..25a2136a3cdf 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -139,6 +139,24 @@ int dcache_status(void) return (get_sctlr() & CR_C) != 0; } +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, + enum dcache_option option) +{ + /* get the level2_table0 start address */ + u64 *page_table = (u64 *)(gd->arch.tlb_addr + 0x3000); + u64 upto, end; + + end = ALIGN(start + size, (1 << MMU_SECTION_SHIFT)) >> + MMU_SECTION_SHIFT; + start = start >> MMU_SECTION_SHIFT; + for (upto = start; upto < end; upto++) { + page_table[upto] &= ~PMD_ATTRINDX_MASK; + page_table[upto] |= PMD_ATTRINDX(option); + } + + flush_dcache_range(page_table[start], page_table[end]); + __asm_invalidate_tlb_all(); +} #else /* CONFIG_SYS_DCACHE_OFF */ void invalidate_dcache_all(void) @@ -170,6 +188,11 @@ int dcache_status(void) return 0; } +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, + enum dcache_option option) +{ +} + #endif /* CONFIG_SYS_DCACHE_OFF */ #ifndef CONFIG_SYS_ICACHE_OFF diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 2a5bed2e46b6..c88687860ec1 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -15,9 +15,15 @@ #define CR_EE (1 << 25) /* Exception (Big) Endian */ #define PGTABLE_SIZE (0x10000) +/* 2M granularity */ +#define MMU_SECTION_SHIFT 21 #ifndef __ASSEMBLY__ +enum dcache_option { + DCACHE_OFF = 0x3, +}; + #define isb() \ ({asm volatile( \ "isb" : : : "memory"); \ @@ -211,16 +217,6 @@ enum { }; /** - * Change the cache settings for a region. - * - * \param start start address of memory region to change - * \param size size of memory region to change - * \param option dcache option to select - */ -void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, - enum dcache_option option); - -/** * Register an update to the page tables, and flush the TLB * * \param start start address of update in page table @@ -241,4 +237,16 @@ phys_addr_t noncached_alloc(size_t size, size_t align); #endif /* CONFIG_ARM64 */ +#ifndef __ASSEMBLY__ +/** + * Change the cache settings for a region. + * + * \param start start address of memory region to change + * \param size size of memory region to change + * \param option dcache option to select + */ +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, + enum dcache_option option); +#endif /* __ASSEMBLY__ */ + #endif -- 2.3.5