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From: Zong Li <zong.li@sifive.com>
To: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com,
	sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: Zong Li <zong.li@sifive.com>
Subject: [PATCH v6 3/4] target/riscv: Fix the translation of physical address
Date: Tue, 28 Jul 2020 16:26:16 +0800	[thread overview]
Message-ID: <370a983d0f9e8a9a927b9bb8af5e7bc84b1bf9b1.1595924470.git.zong.li@sifive.com> (raw)
In-Reply-To: <cover.1595924470.git.zong.li@sifive.com>

The real physical address should add the 12 bits page offset. It also
causes the PMP wrong checking due to the minimum granularity of PMP is
4 byte, but we always get the physical address which is 4KB alignment,
that means, we always use the start address of the page to check PMP for
all addresses which in the same page.

Signed-off-by: Zong Li <zong.li@sifive.com>
---
 target/riscv/cpu_helper.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 75d2ae3434..2f337e418c 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -543,7 +543,8 @@ restart:
             /* for superpage mappings, make a fake leaf PTE for the TLB's
                benefit. */
             target_ulong vpn = addr >> PGSHIFT;
-            *physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT;
+            *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
+                        (addr & ~TARGET_PAGE_MASK);
 
             /* set permissions on the TLB entry */
             if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
@@ -630,7 +631,7 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
         }
     }
 
-    return phys_addr;
+    return phys_addr & TARGET_PAGE_MASK;
 }
 
 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
-- 
2.27.0



  parent reply	other threads:[~2020-07-28  8:27 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-28  8:26 [PATCH v6 0/4] Fix some PMP implementations Zong Li
2020-07-28  8:26 ` [PATCH v6 1/4] target/riscv: Fix the range of pmpcfg of CSR funcion table Zong Li
2020-07-28  8:26   ` Zong Li
2020-07-28  8:26 ` [PATCH v6 2/4] target/riscv/pmp.c: Fix the index offset on RV64 Zong Li
2020-07-28  8:26   ` Zong Li
2020-07-28  8:26 ` Zong Li [this message]
2020-07-28 23:55   ` [PATCH v6 3/4] target/riscv: Fix the translation of physical address Alistair Francis
2020-07-28 23:55     ` Alistair Francis
2020-07-28  8:26 ` [PATCH v6 4/4] target/riscv: Change the TLB page size depends on PMP entries Zong Li
2020-08-05  2:43   ` Zong Li
2020-08-12 15:11   ` Alistair Francis
2020-08-12 15:11     ` Alistair Francis
2020-08-13  3:04     ` Zong Li
2020-08-13  3:04       ` Zong Li
2020-08-13 15:02       ` Alistair Francis
2020-08-13 15:02         ` Alistair Francis

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