From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935367AbbCPUBZ (ORCPT ); Mon, 16 Mar 2015 16:01:25 -0400 Received: from mout.kundenserver.de ([212.227.126.130]:62571 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933795AbbCPUBS convert rfc822-to-8bit (ORCPT ); Mon, 16 Mar 2015 16:01:18 -0400 From: Arnd Bergmann To: Kumar Gala Cc: Gabriel FERNANDEZ , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Srinivas Kandagatla , Maxime Coquelin , Patrice Chotard , Russell King , Bjorn Helgaas , Mohit Kumar , Jingoo Han , Lucas Stach , Fabrice Gasnier , Kishon Vijay Abraham I , Andrew Morton , "David S. Miller" , Greg KH , Mauro Carvalho Chehab , Joe Perches , Tejun Heo , Viresh Kumar , Thierry Reding , Phil Edworthy , Minghuan Lian , Tanmay Inamdar , m-karicheri2@ti.com, Sachin Kamat , Andrew Lunn , Liviu Dudau , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@stlinux.com, linux-pci@vger.kernel.org, Lee Jones , Gabriel Fernandez Subject: Re: [PATCH v2 4/5] PCI: designware: Add disable IO support Date: Mon, 16 Mar 2015 21:00:42 +0100 Message-ID: <3714853.Vuc23EfWdL@wuerfel> User-Agent: KMail/4.11.5 (Linux/3.16.0-10-generic; KDE/4.11.5; x86_64; ; ) In-Reply-To: <582D947C-1229-4DD9-BC82-812D1560C49E@codeaurora.org> References: <1426515635-9466-1-git-send-email-gabriel.fernandez@linaro.org> <1426515635-9466-5-git-send-email-gabriel.fernandez@linaro.org> <582D947C-1229-4DD9-BC82-812D1560C49E@codeaurora.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="utf-8" X-Provags-ID: V03:K0:eCkTuqIcQUcVJrzpkjWLMAem2YeSfzgIJRLiIFDzrZglo7Y0zXS H/7toREUlXwdy3KLewuS/dkslOe+fwegHj3E9WrSMTWYYlQ8OATuPtxcXqTqevI3lHDGbZR TBx4ZykfzLVDVXQeFhyBpA+Jlmo0DJPbYVDUuLpfsKoKGgj3/SpzaY+mL1PWnRjPNsjysM+ DYBZqRQoUCPxGiAoMj1AA== X-UI-Out-Filterresults: notjunk:1; Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Monday 16 March 2015 13:00:51 Kumar Gala wrote: > On Mar 16, 2015, at 9:20 AM, Gabriel FERNANDEZ wrote: > > > ST sti SoCs PCIe IPs are built around DesignWare IP Core. > > But in these SoCs PCIe IP doesn't support IO. > > > > This patch adds the possibility to disable it through > > a DT property, by creating an empty IO window and by > > removing PCI_COMMAND_IO from the setup register. > > > > Signed-off-by: Fabrice Gasnier > > Signed-off-by: Gabriel Fernandez > > --- > > .../devicetree/bindings/pci/designware-pcie.txt | 2 ++ > > drivers/pci/host/pcie-designware.c | 24 ++++++++++++++++++++-- > > drivers/pci/host/pcie-designware.h | 1 + > > 3 files changed, 25 insertions(+), 2 deletions(-) > > Why not just update the code such that if the ranges doesn’t have an IO > space rather than introducing a new DT property? I suspect we can simplify this now by changing over the designware PCI code from pci_common_init_dev to calling pci_scan_root_bus() in the same way that pci-versatile.c does. This would also clean up some other areas of the driver and let you do proper error handling in the probe. Arnd From mboxrd@z Thu Jan 1 00:00:00 1970 From: Arnd Bergmann Subject: Re: [PATCH v2 4/5] PCI: designware: Add disable IO support Date: Mon, 16 Mar 2015 21:00:42 +0100 Message-ID: <3714853.Vuc23EfWdL@wuerfel> References: <1426515635-9466-1-git-send-email-gabriel.fernandez@linaro.org> <1426515635-9466-5-git-send-email-gabriel.fernandez@linaro.org> <582D947C-1229-4DD9-BC82-812D1560C49E@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <582D947C-1229-4DD9-BC82-812D1560C49E-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Kumar Gala Cc: Gabriel FERNANDEZ , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Srinivas Kandagatla , Maxime Coquelin , Patrice Chotard , Russell King , Bjorn Helgaas , Mohit Kumar , Jingoo Han , Lucas Stach , Fabrice Gasnier , Kishon Vijay Abraham I , Andrew Morton , "David S. Miller" , Greg KH , Mauro Carvalho Chehab , Joe Perches , Tejun Heo , Viresh Kumar , Thierry List-Id: devicetree@vger.kernel.org On Monday 16 March 2015 13:00:51 Kumar Gala wrote: > On Mar 16, 2015, at 9:20 AM, Gabriel FERNANDEZ wrote: >=20 > > ST sti SoCs PCIe IPs are built around DesignWare IP Core. > > But in these SoCs PCIe IP doesn't support IO. > >=20 > > This patch adds the possibility to disable it through > > a DT property, by creating an empty IO window and by > > removing PCI_COMMAND_IO from the setup register. > >=20 > > Signed-off-by: Fabrice Gasnier > > Signed-off-by: Gabriel Fernandez > > --- > > .../devicetree/bindings/pci/designware-pcie.txt | 2 ++ > > drivers/pci/host/pcie-designware.c | 24 +++++++++++= +++++++++-- > > drivers/pci/host/pcie-designware.h | 1 + > > 3 files changed, 25 insertions(+), 2 deletions(-) >=20 > Why not just update the code such that if the ranges doesn=E2=80=99t = have an IO > space rather than introducing a new DT property? I suspect we can simplify this now by changing over the designware PCI code from pci_common_init_dev to calling pci_scan_root_bus() in the same way that pci-versatile.c does. This would also clean up some other areas of the driver and let you do proper error handling in the probe. Arnd -- To unsubscribe from this list: send the line "unsubscribe devicetree" i= n the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: arnd@arndb.de (Arnd Bergmann) Date: Mon, 16 Mar 2015 21:00:42 +0100 Subject: [PATCH v2 4/5] PCI: designware: Add disable IO support In-Reply-To: <582D947C-1229-4DD9-BC82-812D1560C49E@codeaurora.org> References: <1426515635-9466-1-git-send-email-gabriel.fernandez@linaro.org> <1426515635-9466-5-git-send-email-gabriel.fernandez@linaro.org> <582D947C-1229-4DD9-BC82-812D1560C49E@codeaurora.org> Message-ID: <3714853.Vuc23EfWdL@wuerfel> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Monday 16 March 2015 13:00:51 Kumar Gala wrote: > On Mar 16, 2015, at 9:20 AM, Gabriel FERNANDEZ wrote: > > > ST sti SoCs PCIe IPs are built around DesignWare IP Core. > > But in these SoCs PCIe IP doesn't support IO. > > > > This patch adds the possibility to disable it through > > a DT property, by creating an empty IO window and by > > removing PCI_COMMAND_IO from the setup register. > > > > Signed-off-by: Fabrice Gasnier > > Signed-off-by: Gabriel Fernandez > > --- > > .../devicetree/bindings/pci/designware-pcie.txt | 2 ++ > > drivers/pci/host/pcie-designware.c | 24 ++++++++++++++++++++-- > > drivers/pci/host/pcie-designware.h | 1 + > > 3 files changed, 25 insertions(+), 2 deletions(-) > > Why not just update the code such that if the ranges doesn?t have an IO > space rather than introducing a new DT property? I suspect we can simplify this now by changing over the designware PCI code from pci_common_init_dev to calling pci_scan_root_bus() in the same way that pci-versatile.c does. This would also clean up some other areas of the driver and let you do proper error handling in the probe. Arnd