From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932207AbcK1Ic7 (ORCPT ); Mon, 28 Nov 2016 03:32:59 -0500 Received: from galahad.ideasonboard.com ([185.26.127.97]:50384 "EHLO galahad.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754060AbcK1Icz (ORCPT ); Mon, 28 Nov 2016 03:32:55 -0500 From: Laurent Pinchart To: dri-devel@lists.freedesktop.org Cc: Neil Armstrong , airlied@linux.ie, khilman@baylibre.com, carlo@caione.org, devicetree@vger.kernel.org, Xing.Xu@amlogic.com, victor.wan@amlogic.com, linux-kernel@vger.kernel.org, jerry.cao@amlogic.com, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: Re: [RFC PATCH 3/3] dt-bindings: display: add Amlogic Meson DRM Bindings Date: Mon, 28 Nov 2016 10:33:07 +0200 Message-ID: <3721857.XEGXu9B51N@avalon> User-Agent: KMail/4.14.10 (Linux/4.8.6-gentoo; KDE/4.14.24; x86_64; ; ) In-Reply-To: <1480089791-12517-4-git-send-email-narmstrong@baylibre.com> References: <1480089791-12517-1-git-send-email-narmstrong@baylibre.com> <1480089791-12517-4-git-send-email-narmstrong@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Neil, Thank you for the patch. On Friday 25 Nov 2016 17:03:11 Neil Armstrong wrote: > Signed-off-by: Neil Armstrong > --- > .../bindings/display/meson/meson-drm.txt | 134 +++++++++++++++++ > 1 file changed, 134 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/meson/meson-drm.txt > > diff --git a/Documentation/devicetree/bindings/display/meson/meson-drm.txt > b/Documentation/devicetree/bindings/display/meson/meson-drm.txt new file > mode 100644 > index 0000000..89c1b5f > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/meson/meson-drm.txt > @@ -0,0 +1,134 @@ > +Amlogic Meson Display Controller > +================================ > + > +The Amlogic Meson Display controller is composed of several components > +that are going to be documented below: > + > +DMC|---------------VPU (Video Processing Unit)------------|------HHI------| > + | vd1 _______ _____________ _____________ | | > +D |-------| |----| | | | | HDMI PLL | > +D | vd2 | VIU | | Video Post | | Video Encs |<---|-----VCLK | > +R |-------| |----| Processing | | | | | > + | osd2 | | | |---| Enci ------|----|-----VDAC------| > +R |-------| CSC |----| Scalers | | Encp ------|----|----HDMI-TX----| > +A | osd1 | | | Blenders | | Encl-------|----|---------------| > +M |-------|______|----|____________| |____________| | | > +___|______________________________________________________|_______________| > + > + > +VIU: Video Input Unit > +--------------------- > + > +The Video Input Unit is in charge of the pixel scanout from the DDR memory. > +It fetches the frames addresses, stride and parameters from the "Canvas" > memory. > +This part is also in charge of the CSC (Colorspace Conversion). > +It can handle 2 OSD Planes and 2 Video Planes. > + > +VPP: Video Processing Unit Do you mean "Video Post Processing" ? In your diagram above Video Processing Unit is abbreviated VPU and covers the VIU, VPP and encoders. > +-------------------------- > + > +The Video Processing Unit is in charge if the scaling and blending of the > +various planes into a single pixel stream. > +There is a special "pre-blending" used by the video planes with a dedicated > +scaler and a "post-blending" to merge with the OSD Planes. > +The OSD planes also have a dedicated scaler for one of the OSD. > + > +VENC: Video Encoders > +-------------------- > + > +The VENC is composed of the multiple pixel encoders : > + - ENCI : Interlace Video encoder for CVBS and Interlace HDMI > + - ENCP : Progressive Video Encoder for HDMI > + - ENCL : LCD LVDS Encoder > +The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and > clock > +tree and provides the scanout clock to the VPP and VIU. > +The ENCI is connected to a single VDAC for Composite Output. > +The ENCI and ENCP are connected to an on-chip HDMI Transceiver. > + > +Device Tree Bindings: > +--------------------- > + > +VPU: Video Processing Unit > +-------------------------- > + > +Required properties: > + - compatible: value should be different for each SoC family as : > + - GXBB (S905) : "amlogic,meson-gxbb-vpu" > + - GXL (S905X, S905D) : "amlogic,meson-gxl-vpu" > + - GXM (S912) : "amlogic,meson-gxm-vpu" > + followed by the common "amlogic,meson-gx-vpu" > + - reg: base address and size of he following memory-mapped regions : > + - vpu > + - hhi > + - dmc > + - reg-names: should contain the names of the previous memory regions > + - interrupts: should contain the VENC Vsync interrupt number > + > +- ports: A ports node with endpoint definitions as defined in > + Documentation/devicetree/bindings/media/video-interfaces.txt. The > + second port should be the output endpoints for VENC connectors. > + > +VENC CBVS Output > +---------------------- > + > +The VENC can output Composite/CVBS output via a decicated VDAC. > + > +Required properties: > + - compatible: value must be one of: > + - compatible: value should be different for each SoC family as : One of those two lines is redundant. > + - GXBB (S905) : "amlogic,meson-gxbb-venc-cvbs" > + - GXL (S905X, S905D) : "amlogic,meson-gxl-venc-cvbs" > + - GXM (S912) : "amlogic,meson-gxm-venc-cvbs" > + followed by the common "amlogic,meson-gx-venc-cvbs" > + No registers ? Are the encoders registers part of the VPU register space, intertwined in a way that they can't be specified separately here ? > +- ports: A ports node with endpoint definitions as defined in > + Documentation/devicetree/bindings/media/video-interfaces.txt. The > + first port should be the input endpoints, connected ot the VPU node. > + > +Example: > + > +venc_cvbs: venc-cvbs { > + compatible = "amlogic,meson-gxbb-venc-cvbs"; > + status = "okay"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + enc_cvbs_in: port@0 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0>; > + > + venc_cvbs_in_vpu: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&vpu_out_venc_cvbs>; > + }; > + }; > + }; > +}; > + > +vpu: vpu@d0100000 { > + compatible = "amlogic,meson-gxbb-vpu"; > + reg = <0x0 0xd0100000 0x0 0x100000>, > + <0x0 0xc883c000 0x0 0x1000>, > + <0x0 0xc8838000 0x0 0x1000>; > + reg-names = "base", "hhi", "dmc"; > + interrupts = ; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + vpu_out: port@1 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <1>; > + > + vpu_out_venc_cvbs: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&venc_cvbs_in_vpu>; > + }; > + }; > + }; > +}; -- Regards, Laurent Pinchart From mboxrd@z Thu Jan 1 00:00:00 1970 From: Laurent Pinchart Subject: Re: [RFC PATCH 3/3] dt-bindings: display: add Amlogic Meson DRM Bindings Date: Mon, 28 Nov 2016 10:33:07 +0200 Message-ID: <3721857.XEGXu9B51N@avalon> References: <1480089791-12517-1-git-send-email-narmstrong@baylibre.com> <1480089791-12517-4-git-send-email-narmstrong@baylibre.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1480089791-12517-4-git-send-email-narmstrong@baylibre.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org Cc: devicetree@vger.kernel.org, Xing.Xu@amlogic.com, victor.wan@amlogic.com, Neil Armstrong , khilman@baylibre.com, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, carlo@caione.org, jerry.cao@amlogic.com, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org SGkgTmVpbCwKClRoYW5rIHlvdSBmb3IgdGhlIHBhdGNoLgoKT24gRnJpZGF5IDI1IE5vdiAyMDE2 IDE3OjAzOjExIE5laWwgQXJtc3Ryb25nIHdyb3RlOgo+IFNpZ25lZC1vZmYtYnk6IE5laWwgQXJt c3Ryb25nIDxuYXJtc3Ryb25nQGJheWxpYnJlLmNvbT4KPiAtLS0KPiAgLi4uL2JpbmRpbmdzL2Rp c3BsYXkvbWVzb24vbWVzb24tZHJtLnR4dCAgICAgICAgICAgfCAxMzQgKysrKysrKysrKysrKysr KysKPiAgMSBmaWxlIGNoYW5nZWQsIDEzNCBpbnNlcnRpb25zKCspCj4gIGNyZWF0ZSBtb2RlIDEw MDY0NAo+IERvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9kaXNwbGF5L21lc29uL21l c29uLWRybS50eHQKPiAKPiBkaWZmIC0tZ2l0IGEvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2Jp bmRpbmdzL2Rpc3BsYXkvbWVzb24vbWVzb24tZHJtLnR4dAo+IGIvRG9jdW1lbnRhdGlvbi9kZXZp Y2V0cmVlL2JpbmRpbmdzL2Rpc3BsYXkvbWVzb24vbWVzb24tZHJtLnR4dCBuZXcgZmlsZQo+IG1v ZGUgMTAwNjQ0Cj4gaW5kZXggMDAwMDAwMC4uODljMWI1Zgo+IC0tLSAvZGV2L251bGwKPiArKysg Yi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvZGlzcGxheS9tZXNvbi9tZXNvbi1k cm0udHh0Cj4gQEAgLTAsMCArMSwxMzQgQEAKPiArQW1sb2dpYyBNZXNvbiBEaXNwbGF5IENvbnRy b2xsZXIKPiArPT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT0KPiArCj4gK1RoZSBBbWxv Z2ljIE1lc29uIERpc3BsYXkgY29udHJvbGxlciBpcyBjb21wb3NlZCBvZiBzZXZlcmFsIGNvbXBv bmVudHMKPiArdGhhdCBhcmUgZ29pbmcgdG8gYmUgZG9jdW1lbnRlZCBiZWxvdzoKPiArCj4gK0RN Q3wtLS0tLS0tLS0tLS0tLS1WUFUgKFZpZGVvIFByb2Nlc3NpbmcgVW5pdCktLS0tLS0tLS0tLS18 LS0tLS0tSEhJLS0tLS0tfAo+ICsgICB8IHZkMSAgIF9fX19fX18gICAgIF9fX19fX19fX19fX18g ICAgX19fX19fX19fX19fXyAgICAgfCAgICAgICAgICAgICAgIHwKPiArRCAgfC0tLS0tLS18ICAg ICAgfC0tLS18ICAgICAgICAgICAgfCAgIHwgICAgICAgICAgICB8ICAgIHwgICBIRE1JIFBMTCAg ICB8Cj4gK0QgIHwgdmQyICAgfCBWSVUgIHwgICAgfCBWaWRlbyBQb3N0IHwgICB8IFZpZGVvIEVu Y3MgfDwtLS18LS0tLS1WQ0xLICAgICAgfAo+ICtSICB8LS0tLS0tLXwgICAgICB8LS0tLXwgUHJv Y2Vzc2luZyB8ICAgfCAgICAgICAgICAgIHwgICAgfCAgICAgICAgICAgICAgIHwKPiArICAgfCBv c2QyICB8ICAgICAgfCAgICB8ICAgICAgICAgICAgfC0tLXwgRW5jaSAtLS0tLS18LS0tLXwtLS0t LVZEQUMtLS0tLS18Cj4gK1IgIHwtLS0tLS0tfCBDU0MgIHwtLS0tfCBTY2FsZXJzICAgIHwgICB8 IEVuY3AgLS0tLS0tfC0tLS18LS0tLUhETUktVFgtLS0tfAo+ICtBICB8IG9zZDEgIHwgICAgICB8 ICAgIHwgQmxlbmRlcnMgICB8ICAgfCBFbmNsLS0tLS0tLXwtLS0tfC0tLS0tLS0tLS0tLS0tLXwK PiArTSAgfC0tLS0tLS18X19fX19ffC0tLS18X19fX19fX19fX19ffCAgIHxfX19fX19fX19fX198 ICAgIHwgICAgICAgICAgICAgICB8Cj4gK19fX3xfX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX198X19fX19fX19fX19fX19ffAo+ICsKPiArCj4gK1ZJ VTogVmlkZW8gSW5wdXQgVW5pdAo+ICstLS0tLS0tLS0tLS0tLS0tLS0tLS0KPiArCj4gK1RoZSBW aWRlbyBJbnB1dCBVbml0IGlzIGluIGNoYXJnZSBvZiB0aGUgcGl4ZWwgc2Nhbm91dCBmcm9tIHRo ZSBERFIgbWVtb3J5Lgo+ICtJdCBmZXRjaGVzIHRoZSBmcmFtZXMgYWRkcmVzc2VzLCBzdHJpZGUg YW5kIHBhcmFtZXRlcnMgZnJvbSB0aGUgIkNhbnZhcyIKPiBtZW1vcnkuCj4gK1RoaXMgcGFydCBp cyBhbHNvIGluIGNoYXJnZSBvZiB0aGUgQ1NDIChDb2xvcnNwYWNlIENvbnZlcnNpb24pLgo+ICtJ dCBjYW4gaGFuZGxlIDIgT1NEIFBsYW5lcyBhbmQgMiBWaWRlbyBQbGFuZXMuCj4gKwo+ICtWUFA6 IFZpZGVvIFByb2Nlc3NpbmcgVW5pdAoKRG8geW91IG1lYW4gIlZpZGVvIFBvc3QgUHJvY2Vzc2lu ZyIgPyBJbiB5b3VyIGRpYWdyYW0gYWJvdmUgVmlkZW8gUHJvY2Vzc2luZyAKVW5pdCBpcyBhYmJy ZXZpYXRlZCBWUFUgYW5kIGNvdmVycyB0aGUgVklVLCBWUFAgYW5kIGVuY29kZXJzLgoKPiArLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0KPiArCj4gK1RoZSBWaWRlbyBQcm9jZXNzaW5nIFVuaXQg aXMgaW4gY2hhcmdlIGlmIHRoZSBzY2FsaW5nIGFuZCBibGVuZGluZyBvZiB0aGUKPiArdmFyaW91 cyBwbGFuZXMgaW50byBhIHNpbmdsZSBwaXhlbCBzdHJlYW0uCj4gK1RoZXJlIGlzIGEgc3BlY2lh bCAicHJlLWJsZW5kaW5nIiB1c2VkIGJ5IHRoZSB2aWRlbyBwbGFuZXMgd2l0aCBhIGRlZGljYXRl ZAo+ICtzY2FsZXIgYW5kIGEgInBvc3QtYmxlbmRpbmciIHRvIG1lcmdlIHdpdGggdGhlIE9TRCBQ bGFuZXMuCj4gK1RoZSBPU0QgcGxhbmVzIGFsc28gaGF2ZSBhIGRlZGljYXRlZCBzY2FsZXIgZm9y IG9uZSBvZiB0aGUgT1NELgo+ICsKPiArVkVOQzogVmlkZW8gRW5jb2RlcnMKPiArLS0tLS0tLS0t LS0tLS0tLS0tLS0KPiArCj4gK1RoZSBWRU5DIGlzIGNvbXBvc2VkIG9mIHRoZSBtdWx0aXBsZSBw aXhlbCBlbmNvZGVycyA6Cj4gKyAtIEVOQ0kgOiBJbnRlcmxhY2UgVmlkZW8gZW5jb2RlciBmb3Ig Q1ZCUyBhbmQgSW50ZXJsYWNlIEhETUkKPiArIC0gRU5DUCA6IFByb2dyZXNzaXZlIFZpZGVvIEVu Y29kZXIgZm9yIEhETUkKPiArIC0gRU5DTCA6IExDRCBMVkRTIEVuY29kZXIKPiArVGhlIFZFTkMg VW5pdCBnZXRzIGEgUGl4ZWwgQ2xvY2tzIChWQ0xLKSBmcm9tIGEgZGVkaWNhdGVkIEhETUkgUExM IGFuZAo+IGNsb2NrCj4gK3RyZWUgYW5kIHByb3ZpZGVzIHRoZSBzY2Fub3V0IGNsb2NrIHRvIHRo ZSBWUFAgYW5kIFZJVS4KPiArVGhlIEVOQ0kgaXMgY29ubmVjdGVkIHRvIGEgc2luZ2xlIFZEQUMg Zm9yIENvbXBvc2l0ZSBPdXRwdXQuCj4gK1RoZSBFTkNJIGFuZCBFTkNQIGFyZSBjb25uZWN0ZWQg dG8gYW4gb24tY2hpcCBIRE1JIFRyYW5zY2VpdmVyLgo+ICsKPiArRGV2aWNlIFRyZWUgQmluZGlu Z3M6Cj4gKy0tLS0tLS0tLS0tLS0tLS0tLS0tLQo+ICsKPiArVlBVOiBWaWRlbyBQcm9jZXNzaW5n IFVuaXQKPiArLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0KPiArCj4gK1JlcXVpcmVkIHByb3Bl cnRpZXM6Cj4gKyAtIGNvbXBhdGlibGU6IHZhbHVlIHNob3VsZCBiZSBkaWZmZXJlbnQgZm9yIGVh Y2ggU29DIGZhbWlseSBhcyA6Cj4gKyAJLSBHWEJCIChTOTA1KSA6ICJhbWxvZ2ljLG1lc29uLWd4 YmItdnB1Igo+ICsgCS0gR1hMIChTOTA1WCwgUzkwNUQpIDogImFtbG9naWMsbWVzb24tZ3hsLXZw dSIKPiArIAktIEdYTSAoUzkxMikgOiAiYW1sb2dpYyxtZXNvbi1neG0tdnB1Igo+ICsJZm9sbG93 ZWQgYnkgdGhlIGNvbW1vbiAiYW1sb2dpYyxtZXNvbi1neC12cHUiCj4gKyAtIHJlZzogYmFzZSBh ZGRyZXNzIGFuZCBzaXplIG9mIGhlIGZvbGxvd2luZyBtZW1vcnktbWFwcGVkIHJlZ2lvbnMgOgo+ ICsJLSB2cHUKPiArCS0gaGhpCj4gKwktIGRtYwo+ICsgLSByZWctbmFtZXM6IHNob3VsZCBjb250 YWluIHRoZSBuYW1lcyBvZiB0aGUgcHJldmlvdXMgbWVtb3J5IHJlZ2lvbnMKPiArIC0gaW50ZXJy dXB0czogc2hvdWxkIGNvbnRhaW4gdGhlIFZFTkMgVnN5bmMgaW50ZXJydXB0IG51bWJlcgo+ICsK PiArLSBwb3J0czogQSBwb3J0cyBub2RlIHdpdGggZW5kcG9pbnQgZGVmaW5pdGlvbnMgYXMgZGVm aW5lZCBpbgo+ICsgIERvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9tZWRpYS92aWRl by1pbnRlcmZhY2VzLnR4dC4gVGhlCj4gKyAgc2Vjb25kIHBvcnQgc2hvdWxkIGJlIHRoZSBvdXRw dXQgZW5kcG9pbnRzIGZvciBWRU5DIGNvbm5lY3RvcnMuCj4gKwo+ICtWRU5DIENCVlMgT3V0cHV0 Cj4gKy0tLS0tLS0tLS0tLS0tLS0tLS0tLS0KPiArCj4gK1RoZSBWRU5DIGNhbiBvdXRwdXQgQ29t cG9zaXRlL0NWQlMgb3V0cHV0IHZpYSBhIGRlY2ljYXRlZCBWREFDLgo+ICsKPiArUmVxdWlyZWQg cHJvcGVydGllczoKPiArICAtIGNvbXBhdGlibGU6IHZhbHVlIG11c3QgYmUgb25lIG9mOgo+ICsg LSBjb21wYXRpYmxlOiB2YWx1ZSBzaG91bGQgYmUgZGlmZmVyZW50IGZvciBlYWNoIFNvQyBmYW1p bHkgYXMgOgoKT25lIG9mIHRob3NlIHR3byBsaW5lcyBpcyByZWR1bmRhbnQuCgo+ICsgCS0gR1hC QiAoUzkwNSkgOiAiYW1sb2dpYyxtZXNvbi1neGJiLXZlbmMtY3ZicyIKPiArIAktIEdYTCAoUzkw NVgsIFM5MDVEKSA6ICJhbWxvZ2ljLG1lc29uLWd4bC12ZW5jLWN2YnMiCj4gKyAJLSBHWE0gKFM5 MTIpIDogImFtbG9naWMsbWVzb24tZ3htLXZlbmMtY3ZicyIKPiArCWZvbGxvd2VkIGJ5IHRoZSBj b21tb24gImFtbG9naWMsbWVzb24tZ3gtdmVuYy1jdmJzIgo+ICsKCk5vIHJlZ2lzdGVycyA/IEFy ZSB0aGUgZW5jb2RlcnMgcmVnaXN0ZXJzIHBhcnQgb2YgdGhlIFZQVSByZWdpc3RlciBzcGFjZSwg CmludGVydHdpbmVkIGluIGEgd2F5IHRoYXQgdGhleSBjYW4ndCBiZSBzcGVjaWZpZWQgc2VwYXJh dGVseSBoZXJlID8KCj4gKy0gcG9ydHM6IEEgcG9ydHMgbm9kZSB3aXRoIGVuZHBvaW50IGRlZmlu aXRpb25zIGFzIGRlZmluZWQgaW4KPiArICBEb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGlu Z3MvbWVkaWEvdmlkZW8taW50ZXJmYWNlcy50eHQuIFRoZQo+ICsgIGZpcnN0IHBvcnQgc2hvdWxk IGJlIHRoZSBpbnB1dCBlbmRwb2ludHMsIGNvbm5lY3RlZCBvdCB0aGUgVlBVIG5vZGUuCj4gKwo+ ICtFeGFtcGxlOgo+ICsKPiArdmVuY19jdmJzOiB2ZW5jLWN2YnMgewo+ICsJY29tcGF0aWJsZSA9 ICJhbWxvZ2ljLG1lc29uLWd4YmItdmVuYy1jdmJzIjsKPiArCXN0YXR1cyA9ICJva2F5IjsKPiAr Cj4gKwlwb3J0cyB7Cj4gKwkJI2FkZHJlc3MtY2VsbHMgPSA8MT47Cj4gKwkJI3NpemUtY2VsbHMg PSA8MD47Cj4gKwo+ICsJCWVuY19jdmJzX2luOiBwb3J0QDAgewo+ICsJCQkgI2FkZHJlc3MtY2Vs bHMgPSA8MT47Cj4gKwkJCSAjc2l6ZS1jZWxscyA9IDwwPjsKPiArCQkJIHJlZyA9IDwwPjsKPiAr Cj4gKwkJCSB2ZW5jX2N2YnNfaW5fdnB1OiBlbmRwb2ludEAwIHsKPiArCQkJCSByZWcgPSA8MD47 Cj4gKwkJCQkgcmVtb3RlLWVuZHBvaW50ID0gPCZ2cHVfb3V0X3ZlbmNfY3Zicz47Cj4gKwkJCX07 Cj4gKwkJfTsKPiArCX07Cj4gK307Cj4gKwo+ICt2cHU6IHZwdUBkMDEwMDAwMCB7Cj4gKwljb21w YXRpYmxlID0gImFtbG9naWMsbWVzb24tZ3hiYi12cHUiOwo+ICsJcmVnID0gPDB4MCAweGQwMTAw MDAwIDB4MCAweDEwMDAwMD4sCj4gKwkgICAgICA8MHgwIDB4Yzg4M2MwMDAgMHgwIDB4MTAwMD4s Cj4gKwkgICAgICA8MHgwIDB4Yzg4MzgwMDAgMHgwIDB4MTAwMD47Cj4gKwlyZWctbmFtZXMgPSAi YmFzZSIsICJoaGkiLCAiZG1jIjsKPiArCWludGVycnVwdHMgPSA8R0lDX1NQSSAzIElSUV9UWVBF X0VER0VfUklTSU5HPjsKPiArCj4gKwlwb3J0cyB7Cj4gKwkJI2FkZHJlc3MtY2VsbHMgPSA8MT47 Cj4gKwkJI3NpemUtY2VsbHMgPSA8MD47Cj4gKwo+ICsJCXZwdV9vdXQ6IHBvcnRAMSB7Cj4gKwkJ CSAjYWRkcmVzcy1jZWxscyA9IDwxPjsKPiArCQkJICNzaXplLWNlbGxzID0gPDA+Owo+ICsJCQkg cmVnID0gPDE+Owo+ICsKPiArCQkJIHZwdV9vdXRfdmVuY19jdmJzOiBlbmRwb2ludEAwIHsKPiAr CQkJCSByZWcgPSA8MD47Cj4gKwkJCQkgcmVtb3RlLWVuZHBvaW50ID0gPCZ2ZW5jX2N2YnNfaW5f dnB1PjsKPiArCQkJIH07Cj4gKwkJIH07Cj4gKwl9Owo+ICt9OwoKLS0gClJlZ2FyZHMsCgpMYXVy ZW50IFBpbmNoYXJ0CgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5v cmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2 ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 From: laurent.pinchart@ideasonboard.com (Laurent Pinchart) Date: Mon, 28 Nov 2016 10:33:07 +0200 Subject: [RFC PATCH 3/3] dt-bindings: display: add Amlogic Meson DRM Bindings In-Reply-To: <1480089791-12517-4-git-send-email-narmstrong@baylibre.com> References: <1480089791-12517-1-git-send-email-narmstrong@baylibre.com> <1480089791-12517-4-git-send-email-narmstrong@baylibre.com> Message-ID: <3721857.XEGXu9B51N@avalon> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Neil, Thank you for the patch. On Friday 25 Nov 2016 17:03:11 Neil Armstrong wrote: > Signed-off-by: Neil Armstrong > --- > .../bindings/display/meson/meson-drm.txt | 134 +++++++++++++++++ > 1 file changed, 134 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/meson/meson-drm.txt > > diff --git a/Documentation/devicetree/bindings/display/meson/meson-drm.txt > b/Documentation/devicetree/bindings/display/meson/meson-drm.txt new file > mode 100644 > index 0000000..89c1b5f > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/meson/meson-drm.txt > @@ -0,0 +1,134 @@ > +Amlogic Meson Display Controller > +================================ > + > +The Amlogic Meson Display controller is composed of several components > +that are going to be documented below: > + > +DMC|---------------VPU (Video Processing Unit)------------|------HHI------| > + | vd1 _______ _____________ _____________ | | > +D |-------| |----| | | | | HDMI PLL | > +D | vd2 | VIU | | Video Post | | Video Encs |<---|-----VCLK | > +R |-------| |----| Processing | | | | | > + | osd2 | | | |---| Enci ------|----|-----VDAC------| > +R |-------| CSC |----| Scalers | | Encp ------|----|----HDMI-TX----| > +A | osd1 | | | Blenders | | Encl-------|----|---------------| > +M |-------|______|----|____________| |____________| | | > +___|______________________________________________________|_______________| > + > + > +VIU: Video Input Unit > +--------------------- > + > +The Video Input Unit is in charge of the pixel scanout from the DDR memory. > +It fetches the frames addresses, stride and parameters from the "Canvas" > memory. > +This part is also in charge of the CSC (Colorspace Conversion). > +It can handle 2 OSD Planes and 2 Video Planes. > + > +VPP: Video Processing Unit Do you mean "Video Post Processing" ? In your diagram above Video Processing Unit is abbreviated VPU and covers the VIU, VPP and encoders. > +-------------------------- > + > +The Video Processing Unit is in charge if the scaling and blending of the > +various planes into a single pixel stream. > +There is a special "pre-blending" used by the video planes with a dedicated > +scaler and a "post-blending" to merge with the OSD Planes. > +The OSD planes also have a dedicated scaler for one of the OSD. > + > +VENC: Video Encoders > +-------------------- > + > +The VENC is composed of the multiple pixel encoders : > + - ENCI : Interlace Video encoder for CVBS and Interlace HDMI > + - ENCP : Progressive Video Encoder for HDMI > + - ENCL : LCD LVDS Encoder > +The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and > clock > +tree and provides the scanout clock to the VPP and VIU. > +The ENCI is connected to a single VDAC for Composite Output. > +The ENCI and ENCP are connected to an on-chip HDMI Transceiver. > + > +Device Tree Bindings: > +--------------------- > + > +VPU: Video Processing Unit > +-------------------------- > + > +Required properties: > + - compatible: value should be different for each SoC family as : > + - GXBB (S905) : "amlogic,meson-gxbb-vpu" > + - GXL (S905X, S905D) : "amlogic,meson-gxl-vpu" > + - GXM (S912) : "amlogic,meson-gxm-vpu" > + followed by the common "amlogic,meson-gx-vpu" > + - reg: base address and size of he following memory-mapped regions : > + - vpu > + - hhi > + - dmc > + - reg-names: should contain the names of the previous memory regions > + - interrupts: should contain the VENC Vsync interrupt number > + > +- ports: A ports node with endpoint definitions as defined in > + Documentation/devicetree/bindings/media/video-interfaces.txt. The > + second port should be the output endpoints for VENC connectors. > + > +VENC CBVS Output > +---------------------- > + > +The VENC can output Composite/CVBS output via a decicated VDAC. > + > +Required properties: > + - compatible: value must be one of: > + - compatible: value should be different for each SoC family as : One of those two lines is redundant. > + - GXBB (S905) : "amlogic,meson-gxbb-venc-cvbs" > + - GXL (S905X, S905D) : "amlogic,meson-gxl-venc-cvbs" > + - GXM (S912) : "amlogic,meson-gxm-venc-cvbs" > + followed by the common "amlogic,meson-gx-venc-cvbs" > + No registers ? Are the encoders registers part of the VPU register space, intertwined in a way that they can't be specified separately here ? > +- ports: A ports node with endpoint definitions as defined in > + Documentation/devicetree/bindings/media/video-interfaces.txt. The > + first port should be the input endpoints, connected ot the VPU node. > + > +Example: > + > +venc_cvbs: venc-cvbs { > + compatible = "amlogic,meson-gxbb-venc-cvbs"; > + status = "okay"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + enc_cvbs_in: port at 0 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0>; > + > + venc_cvbs_in_vpu: endpoint at 0 { > + reg = <0>; > + remote-endpoint = <&vpu_out_venc_cvbs>; > + }; > + }; > + }; > +}; > + > +vpu: vpu at d0100000 { > + compatible = "amlogic,meson-gxbb-vpu"; > + reg = <0x0 0xd0100000 0x0 0x100000>, > + <0x0 0xc883c000 0x0 0x1000>, > + <0x0 0xc8838000 0x0 0x1000>; > + reg-names = "base", "hhi", "dmc"; > + interrupts = ; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + vpu_out: port at 1 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <1>; > + > + vpu_out_venc_cvbs: endpoint at 0 { > + reg = <0>; > + remote-endpoint = <&venc_cvbs_in_vpu>; > + }; > + }; > + }; > +}; -- Regards, Laurent Pinchart From mboxrd@z Thu Jan 1 00:00:00 1970 From: laurent.pinchart@ideasonboard.com (Laurent Pinchart) Date: Mon, 28 Nov 2016 10:33:07 +0200 Subject: [RFC PATCH 3/3] dt-bindings: display: add Amlogic Meson DRM Bindings In-Reply-To: <1480089791-12517-4-git-send-email-narmstrong@baylibre.com> References: <1480089791-12517-1-git-send-email-narmstrong@baylibre.com> <1480089791-12517-4-git-send-email-narmstrong@baylibre.com> Message-ID: <3721857.XEGXu9B51N@avalon> To: linus-amlogic@lists.infradead.org List-Id: linus-amlogic.lists.infradead.org Hi Neil, Thank you for the patch. On Friday 25 Nov 2016 17:03:11 Neil Armstrong wrote: > Signed-off-by: Neil Armstrong > --- > .../bindings/display/meson/meson-drm.txt | 134 +++++++++++++++++ > 1 file changed, 134 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/meson/meson-drm.txt > > diff --git a/Documentation/devicetree/bindings/display/meson/meson-drm.txt > b/Documentation/devicetree/bindings/display/meson/meson-drm.txt new file > mode 100644 > index 0000000..89c1b5f > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/meson/meson-drm.txt > @@ -0,0 +1,134 @@ > +Amlogic Meson Display Controller > +================================ > + > +The Amlogic Meson Display controller is composed of several components > +that are going to be documented below: > + > +DMC|---------------VPU (Video Processing Unit)------------|------HHI------| > + | vd1 _______ _____________ _____________ | | > +D |-------| |----| | | | | HDMI PLL | > +D | vd2 | VIU | | Video Post | | Video Encs |<---|-----VCLK | > +R |-------| |----| Processing | | | | | > + | osd2 | | | |---| Enci ------|----|-----VDAC------| > +R |-------| CSC |----| Scalers | | Encp ------|----|----HDMI-TX----| > +A | osd1 | | | Blenders | | Encl-------|----|---------------| > +M |-------|______|----|____________| |____________| | | > +___|______________________________________________________|_______________| > + > + > +VIU: Video Input Unit > +--------------------- > + > +The Video Input Unit is in charge of the pixel scanout from the DDR memory. > +It fetches the frames addresses, stride and parameters from the "Canvas" > memory. > +This part is also in charge of the CSC (Colorspace Conversion). > +It can handle 2 OSD Planes and 2 Video Planes. > + > +VPP: Video Processing Unit Do you mean "Video Post Processing" ? In your diagram above Video Processing Unit is abbreviated VPU and covers the VIU, VPP and encoders. > +-------------------------- > + > +The Video Processing Unit is in charge if the scaling and blending of the > +various planes into a single pixel stream. > +There is a special "pre-blending" used by the video planes with a dedicated > +scaler and a "post-blending" to merge with the OSD Planes. > +The OSD planes also have a dedicated scaler for one of the OSD. > + > +VENC: Video Encoders > +-------------------- > + > +The VENC is composed of the multiple pixel encoders : > + - ENCI : Interlace Video encoder for CVBS and Interlace HDMI > + - ENCP : Progressive Video Encoder for HDMI > + - ENCL : LCD LVDS Encoder > +The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and > clock > +tree and provides the scanout clock to the VPP and VIU. > +The ENCI is connected to a single VDAC for Composite Output. > +The ENCI and ENCP are connected to an on-chip HDMI Transceiver. > + > +Device Tree Bindings: > +--------------------- > + > +VPU: Video Processing Unit > +-------------------------- > + > +Required properties: > + - compatible: value should be different for each SoC family as : > + - GXBB (S905) : "amlogic,meson-gxbb-vpu" > + - GXL (S905X, S905D) : "amlogic,meson-gxl-vpu" > + - GXM (S912) : "amlogic,meson-gxm-vpu" > + followed by the common "amlogic,meson-gx-vpu" > + - reg: base address and size of he following memory-mapped regions : > + - vpu > + - hhi > + - dmc > + - reg-names: should contain the names of the previous memory regions > + - interrupts: should contain the VENC Vsync interrupt number > + > +- ports: A ports node with endpoint definitions as defined in > + Documentation/devicetree/bindings/media/video-interfaces.txt. The > + second port should be the output endpoints for VENC connectors. > + > +VENC CBVS Output > +---------------------- > + > +The VENC can output Composite/CVBS output via a decicated VDAC. > + > +Required properties: > + - compatible: value must be one of: > + - compatible: value should be different for each SoC family as : One of those two lines is redundant. > + - GXBB (S905) : "amlogic,meson-gxbb-venc-cvbs" > + - GXL (S905X, S905D) : "amlogic,meson-gxl-venc-cvbs" > + - GXM (S912) : "amlogic,meson-gxm-venc-cvbs" > + followed by the common "amlogic,meson-gx-venc-cvbs" > + No registers ? Are the encoders registers part of the VPU register space, intertwined in a way that they can't be specified separately here ? > +- ports: A ports node with endpoint definitions as defined in > + Documentation/devicetree/bindings/media/video-interfaces.txt. The > + first port should be the input endpoints, connected ot the VPU node. > + > +Example: > + > +venc_cvbs: venc-cvbs { > + compatible = "amlogic,meson-gxbb-venc-cvbs"; > + status = "okay"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + enc_cvbs_in: port at 0 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0>; > + > + venc_cvbs_in_vpu: endpoint at 0 { > + reg = <0>; > + remote-endpoint = <&vpu_out_venc_cvbs>; > + }; > + }; > + }; > +}; > + > +vpu: vpu at d0100000 { > + compatible = "amlogic,meson-gxbb-vpu"; > + reg = <0x0 0xd0100000 0x0 0x100000>, > + <0x0 0xc883c000 0x0 0x1000>, > + <0x0 0xc8838000 0x0 0x1000>; > + reg-names = "base", "hhi", "dmc"; > + interrupts = ; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + vpu_out: port at 1 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <1>; > + > + vpu_out_venc_cvbs: endpoint at 0 { > + reg = <0>; > + remote-endpoint = <&venc_cvbs_in_vpu>; > + }; > + }; > + }; > +}; -- Regards, Laurent Pinchart