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[83.42.66.122]) by smtp.gmail.com with ESMTPSA id c2sm27342338wrs.60.2021.07.21.10.49.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Jul 2021 10:49:06 -0700 (PDT) Subject: Re: [PATCH v2 07/22] target/loongarch: Add fixed point arithmetic instruction translation From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= To: Song Gao , qemu-devel@nongnu.org References: <1626861198-6133-1-git-send-email-gaosong@loongson.cn> <1626861198-6133-8-git-send-email-gaosong@loongson.cn> Message-ID: <380b9896-8f6b-e695-a8ca-447c86f06a89@amsat.org> Date: Wed, 21 Jul 2021 19:49:05 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, NICE_REPLY_A=-0.117, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, thuth@redhat.com, chenhuacai@gmail.com, richard.henderson@linaro.org, laurent@vivier.eu, maobibo@loongson.cn, yangxiaojuan@loongson.cn, alistair.francis@wdc.com, pbonzini@redhat.com, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/21/21 7:38 PM, Philippe Mathieu-Daudé wrote: > On 7/21/21 11:53 AM, Song Gao wrote: >> This patch implement fixed point arithemtic instruction translation. Typo arithmetic. >> >> This includes: >> - ADD.{W/D}, SUB.{W/D} >> - ADDI.{W/D}, ADDU16ID >> - ALSL.{W[U]/D} >> - LU12I.W, LU32I.D LU52I.D >> - SLT[U], SLT[U]I >> - PCADDI, PCADDU12I, PCADDU18I, PCALAU12I >> - AND, OR, NOR, XOR, ANDN, ORN >> - MUL.{W/D}, MULH.{W[U]/D[U]} >> - MULW.D.W[U] >> - DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]} >> - ANDI, ORI, XORI >> >> Signed-off-by: Song Gao >> --- >> target/loongarch/insns.decode | 89 ++++ >> target/loongarch/trans.inc.c | 1090 +++++++++++++++++++++++++++++++++++++++++ >> target/loongarch/translate.c | 12 + >> target/loongarch/translate.h | 1 + >> 4 files changed, 1192 insertions(+) >> create mode 100644 target/loongarch/insns.decode >> create mode 100644 target/loongarch/trans.inc.c > > Please don't include all .inc.c in one big translate.c... > >> diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c >> index 531f7e1..b60bdc2 100644 >> --- a/target/loongarch/translate.c >> +++ b/target/loongarch/translate.c >> @@ -57,6 +57,15 @@ void gen_load_gpr(TCGv t, int reg) >> } >> } >> >> +TCGv get_gpr(int regno) >> +{ >> + if (regno == 0) { >> + return tcg_constant_tl(0); >> + } else { >> + return cpu_gpr[regno]; >> + } >> +} >> + >> static inline void gen_save_pc(target_ulong pc) > > ... expose this one ... > >> { >> tcg_gen_movi_tl(cpu_PC, pc); >> @@ -287,6 +296,9 @@ static bool loongarch_tr_breakpoint_check(DisasContextBase *dcbase, >> return true; >> } >> >> +#include "decode-insns.c.inc" > > ... and move this include to "trans.c". Since you have the luck to add a new architecture, you could start cleanly from scratch and add group of instructions, so this patch would add "trans_arithmetic.c", etc.. in the series. >> +#include "trans.inc.c" > > removing this include. > >> static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) >> { >> CPULoongArchState *env = cs->env_ptr; >> diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h >> index 333c3bf..ef4d4e7 100644 >> --- a/target/loongarch/translate.h >> +++ b/target/loongarch/translate.h >> @@ -35,6 +35,7 @@ void check_fpu_enabled(DisasContext *ctx); >> >> void gen_base_offset_addr(TCGv addr, int base, int offset); >> void gen_load_gpr(TCGv t, int reg); >> +TCGv get_gpr(int regno); >> void gen_load_fpr32(TCGv_i32 t, int reg); >> void gen_load_fpr64(TCGv_i64 t, int reg); >> void gen_store_fpr32(TCGv_i32 t, int reg); >> > >