From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE43CC169C4 for ; Thu, 31 Jan 2019 09:53:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C07FE218AC for ; Thu, 31 Jan 2019 09:53:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731809AbfAaJxq (ORCPT ); Thu, 31 Jan 2019 04:53:46 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:40754 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726221AbfAaJxp (ORCPT ); Thu, 31 Jan 2019 04:53:45 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 644B5A78; Thu, 31 Jan 2019 01:53:45 -0800 (PST) Received: from [10.1.196.62] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 381223F71E; Thu, 31 Jan 2019 01:53:42 -0800 (PST) Subject: Re: [PATCH v9 01/26] arm64: Fix HCR.TGE status for NMI contexts To: Julien Thierry , Christoffer Dall Cc: James Morse , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, daniel.thompson@linaro.org, joel@joelfernandes.org, catalin.marinas@arm.com, will.deacon@arm.com, mark.rutland@arm.com, Arnd Bergmann , linux-arch@vger.kernel.org, stable@vger.kernel.org References: <1548084825-8803-1-git-send-email-julien.thierry@arm.com> <1548084825-8803-2-git-send-email-julien.thierry@arm.com> <8e8c4f5b-5b83-7bbc-1b84-36d68e210968@arm.com> <847c54ef-ea41-eea5-8aff-72e0cea465f8@arm.com> <20190131081900.GM13482@e113682-lin.lund.arm.com> <32af4a5c-7aeb-0171-1b4a-2cbee5f78bca@arm.com> <20190131092706.GN13482@e113682-lin.lund.arm.com> <7a2c92ca-f0eb-1391-4dc4-005e1dbadc30@arm.com> From: Marc Zyngier Openpgp: preference=signencrypt Autocrypt: addr=marc.zyngier@arm.com; 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Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <7a2c92ca-f0eb-1391-4dc4-005e1dbadc30@arm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 31/01/2019 09:40, Julien Thierry wrote: > > > On 31/01/2019 09:27, Christoffer Dall wrote: >> On Thu, Jan 31, 2019 at 08:56:04AM +0000, Julien Thierry wrote: >>> >>> >>> On 31/01/2019 08:19, Christoffer Dall wrote: >>>> On Mon, Jan 28, 2019 at 03:42:42PM +0000, Julien Thierry wrote: >>>>> Hi James, >>>>> >>>>> On 28/01/2019 11:48, James Morse wrote: >>>>>> Hi Julien, >>>>>> >>>>>> On 21/01/2019 15:33, Julien Thierry wrote: >>>>>>> When using VHE, the host needs to clear HCR_EL2.TGE bit in order >>>>>>> to interract with guest TLBs, switching from EL2&0 translation regime >>>>>> >>>>>> (interact) >>>>>> >>>>>> >>>>>>> to EL1&0. >>>>>>> >>>>>>> However, some non-maskable asynchronous event could happen while TGE is >>>>>>> cleared like SDEI. Because of this address translation operations >>>>>>> relying on EL2&0 translation regime could fail (tlb invalidation, >>>>>>> userspace access, ...). >>>>>>> >>>>>>> Fix this by properly setting HCR_EL2.TGE when entering NMI context and >>>>>>> clear it if necessary when returning to the interrupted context. >>>>>> >>>>>> Yes please. This would not have been fun to debug! >>>>>> >>>>>> Reviewed-by: James Morse >>>>>> >>>>>> >>>>> >>>>> Thanks. >>>>> >>>>>> >>>>>> I was looking for why we need core code to do this, instead of updating the >>>>>> arch's call sites. Your 'irqdesc: Add domain handlers for NMIs' patch (pointed >>>>>> to from the cover letter) is the reason: core-code calls nmi_enter()/nmi_exit() >>>>>> itself. >>>>>> >>>>> >>>>> Yes, that's the main reason. >>>>> >>>> I wondered the same thing, but I don't understand the explanation :( >>>> >>>> Why can't we do a local_daif_mask() around the (very small) calls that >>>> clear TGE instead? >>>> >>> >>> That would protect against the pseudo-NMIs, but you can still get an >>> SDEI at that point even with all daif bits set. Or did I misunderstand >>> how SDEI works? >>> >> >> I don't know the details of SDEI. From looking at this patch, the >> logical conclusion would be that SDEIs can then only be delivered once >> we've called nmi_enter, but since we don't call this directly from the >> code that clears TGE for doing guest TLB invalidation (or do we?) then >> masking interrupts at the PSTATE level should be sufficient. >> >> Surely I'm missing some part of the bigger picture here. >> > > I'm not sure I understand. SDEI uses the NMI context and AFAIU, it is an > interrupt that the firmware sends to the OS, and it is sent regardless > of the PSTATE at the OS EL. I don't think we can describe SDEI as an interrupt. It is not even an exception. It is just EL3 ERET-ing to a pre-defined location. And yes, it will completely ignore any form of mask bit. > > So, the worrying part is: > - Hyp clears TGE > - Exception/interrupt taken to EL3 > - Firmware decides it's a good time to send an SDEI to the OS > - SDEI handler (at EL2 for VHE) does nmi_enter() > - SDEI handler needs to do cache invalidation or something with the > EL2&0 translation regime but TGE is cleared > > We don't expect the code that clears TGE to call nmi_enter(). Indeed. Without this patch, SDEI is already broken. Pseudo-NMIs only make the bug easier to trigger. Thanks, M. -- Jazz is not dead. It just smells funny... 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Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <7a2c92ca-f0eb-1391-4dc4-005e1dbadc30@arm.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190131_015346_023323_16E638F4 X-CRM114-Status: GOOD ( 19.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, linux-arch@vger.kernel.org, daniel.thompson@linaro.org, Arnd Bergmann , catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, stable@vger.kernel.org, James Morse , joel@joelfernandes.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 31/01/2019 09:40, Julien Thierry wrote: > > > On 31/01/2019 09:27, Christoffer Dall wrote: >> On Thu, Jan 31, 2019 at 08:56:04AM +0000, Julien Thierry wrote: >>> >>> >>> On 31/01/2019 08:19, Christoffer Dall wrote: >>>> On Mon, Jan 28, 2019 at 03:42:42PM +0000, Julien Thierry wrote: >>>>> Hi James, >>>>> >>>>> On 28/01/2019 11:48, James Morse wrote: >>>>>> Hi Julien, >>>>>> >>>>>> On 21/01/2019 15:33, Julien Thierry wrote: >>>>>>> When using VHE, the host needs to clear HCR_EL2.TGE bit in order >>>>>>> to interract with guest TLBs, switching from EL2&0 translation regime >>>>>> >>>>>> (interact) >>>>>> >>>>>> >>>>>>> to EL1&0. >>>>>>> >>>>>>> However, some non-maskable asynchronous event could happen while TGE is >>>>>>> cleared like SDEI. Because of this address translation operations >>>>>>> relying on EL2&0 translation regime could fail (tlb invalidation, >>>>>>> userspace access, ...). >>>>>>> >>>>>>> Fix this by properly setting HCR_EL2.TGE when entering NMI context and >>>>>>> clear it if necessary when returning to the interrupted context. >>>>>> >>>>>> Yes please. This would not have been fun to debug! >>>>>> >>>>>> Reviewed-by: James Morse >>>>>> >>>>>> >>>>> >>>>> Thanks. >>>>> >>>>>> >>>>>> I was looking for why we need core code to do this, instead of updating the >>>>>> arch's call sites. Your 'irqdesc: Add domain handlers for NMIs' patch (pointed >>>>>> to from the cover letter) is the reason: core-code calls nmi_enter()/nmi_exit() >>>>>> itself. >>>>>> >>>>> >>>>> Yes, that's the main reason. >>>>> >>>> I wondered the same thing, but I don't understand the explanation :( >>>> >>>> Why can't we do a local_daif_mask() around the (very small) calls that >>>> clear TGE instead? >>>> >>> >>> That would protect against the pseudo-NMIs, but you can still get an >>> SDEI at that point even with all daif bits set. Or did I misunderstand >>> how SDEI works? >>> >> >> I don't know the details of SDEI. From looking at this patch, the >> logical conclusion would be that SDEIs can then only be delivered once >> we've called nmi_enter, but since we don't call this directly from the >> code that clears TGE for doing guest TLB invalidation (or do we?) then >> masking interrupts at the PSTATE level should be sufficient. >> >> Surely I'm missing some part of the bigger picture here. >> > > I'm not sure I understand. SDEI uses the NMI context and AFAIU, it is an > interrupt that the firmware sends to the OS, and it is sent regardless > of the PSTATE at the OS EL. I don't think we can describe SDEI as an interrupt. It is not even an exception. It is just EL3 ERET-ing to a pre-defined location. And yes, it will completely ignore any form of mask bit. > > So, the worrying part is: > - Hyp clears TGE > - Exception/interrupt taken to EL3 > - Firmware decides it's a good time to send an SDEI to the OS > - SDEI handler (at EL2 for VHE) does nmi_enter() > - SDEI handler needs to do cache invalidation or something with the > EL2&0 translation regime but TGE is cleared > > We don't expect the code that clears TGE to call nmi_enter(). Indeed. Without this patch, SDEI is already broken. Pseudo-NMIs only make the bug easier to trigger. Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel