From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.4 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E676C4338F for ; Thu, 29 Jul 2021 15:48:17 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2CFBD60F42 for ; Thu, 29 Jul 2021 15:48:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 2CFBD60F42 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AB0AB6EDD3; Thu, 29 Jul 2021 15:48:16 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id CDDA16EDD3; Thu, 29 Jul 2021 15:48:15 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10060"; a="212904242" X-IronPort-AV: E=Sophos;i="5.84,278,1620716400"; d="scan'208";a="212904242" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jul 2021 08:48:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,278,1620716400"; d="scan'208";a="476443785" Received: from irvmail001.ir.intel.com ([10.43.11.63]) by fmsmga008.fm.intel.com with ESMTP; 29 Jul 2021 08:48:12 -0700 Received: from [10.249.142.82] (mwajdecz-MOBL.ger.corp.intel.com [10.249.142.82]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id 16TFmBTa024751; Thu, 29 Jul 2021 16:48:11 +0100 Subject: Re: [PATCH 05/14] drm/i915/guc/slpc: Enable SLPC and add related H2G events To: Vinay Belgaumkar , intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org References: <20210728211144.15322-1-vinay.belgaumkar@intel.com> <20210728211144.15322-6-vinay.belgaumkar@intel.com> From: Michal Wajdeczko Message-ID: <3848937b-9364-e3c6-b25f-72bafd5383cf@intel.com> Date: Thu, 29 Jul 2021 17:48:11 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Firefox/78.0 Thunderbird/78.12.0 MIME-Version: 1.0 In-Reply-To: <20210728211144.15322-6-vinay.belgaumkar@intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sundaresan Sujaritha Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 28.07.2021 23:11, Vinay Belgaumkar wrote: > Add methods for interacting with GuC for enabling SLPC. Enable > SLPC after GuC submission has been established. GuC load will > fail if SLPC cannot be successfully initialized. Add various > helper methods to set/unset the parameters for SLPC. They can > be set using H2G calls or directly setting bits in the shared > data structure. > > v2: Address several review comments, add new helpers for > decoding the SLPC min/max frequencies. Use masks instead of hardcoded > constants. (Michal W) > > v3: Split global_state_to_string function, and check for positive > non-zero return value from intel_guc_send() (Michal W) > > v4: Optimize the stringify function and other comments (Michal W) > > v5: Enable slpc as well before declaring GuC submission status (Michal W) > > Signed-off-by: Vinay Belgaumkar > Signed-off-by: Sundaresan Sujaritha > --- > drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 226 ++++++++++++++++++ > .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 2 + > drivers/gpu/drm/i915/gt/uc/intel_uc.c | 11 + > 3 files changed, 239 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c > index 6d76ea4c0ace..da3e1f8844a9 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c > @@ -45,6 +45,40 @@ void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc) > slpc->selected = __guc_slpc_selected(guc); > } > > +static void slpc_mem_set_param(struct slpc_shared_data *data, > + u32 id, u32 value) > +{ > + GEM_BUG_ON(id >= SLPC_MAX_OVERRIDE_PARAMETERS); > + /* > + * When the flag bit is set, corresponding value will be read > + * and applied by SLPC. > + */ > + data->override_params.bits[id >> 5] |= (1 << (id % 32)); > + data->override_params.values[id] = value; > +} > + > +static void slpc_mem_set_enabled(struct slpc_shared_data *data, > + u8 enable_id, u8 disable_id) > +{ > + /* > + * Enabling a param involves setting the enable_id > + * to 1 and disable_id to 0. > + */ > + slpc_mem_set_param(data, enable_id, 1); > + slpc_mem_set_param(data, disable_id, 0); > +} > + > +static void slpc_mem_set_disabled(struct slpc_shared_data *data, > + u8 enable_id, u8 disable_id) > +{ > + /* > + * Disabling a param involves setting the enable_id > + * to 0 and disable_id to 1. > + */ > + slpc_mem_set_param(data, disable_id, 1); > + slpc_mem_set_param(data, enable_id, 0); > +} > + > static int slpc_shared_data_init(struct intel_guc_slpc *slpc) > { > struct intel_guc *guc = slpc_to_guc(slpc); > @@ -63,6 +97,121 @@ static int slpc_shared_data_init(struct intel_guc_slpc *slpc) > return err; > } > > +static u32 slpc_get_state(struct intel_guc_slpc *slpc) > +{ > + struct slpc_shared_data *data; > + > + GEM_BUG_ON(!slpc->vma); > + > + drm_clflush_virt_range(slpc->vaddr, sizeof(u32)); > + data = slpc->vaddr; > + > + return data->header.global_state; > +} > + > +static bool slpc_is_running(struct intel_guc_slpc *slpc) > +{ > + return slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING; > +} > + > +static int guc_action_slpc_query(struct intel_guc *guc, u32 offset) > +{ > + u32 request[] = { > + GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST, > + SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2), > + offset, > + 0, > + }; > + int ret; > + > + ret = intel_guc_send(guc, request, ARRAY_SIZE(request)); > + > + return ret > 0 ? -EPROTO : ret; > +} > + > +static int slpc_query_task_state(struct intel_guc_slpc *slpc) > +{ > + struct intel_guc *guc = slpc_to_guc(slpc); > + struct drm_i915_private *i915 = slpc_to_i915(slpc); > + u32 offset = intel_guc_ggtt_offset(guc, slpc->vma); > + int ret; > + > + ret = guc_action_slpc_query(guc, offset); > + if (ret) unlikely(ret) ? > + drm_err(&i915->drm, "Failed to query task state (%pe)\n", > + ERR_PTR(ret)); is this indent correct ? > + > + drm_clflush_virt_range(slpc->vaddr, SLPC_PAGE_SIZE_BYTES); > + > + return ret; > +} > + > +static const char *slpc_global_state_to_string(enum slpc_global_state state) > +{ > + switch (state) { > + case SLPC_GLOBAL_STATE_NOT_RUNNING: > + return "not running"; > + case SLPC_GLOBAL_STATE_INITIALIZING: > + return "initializing"; > + case SLPC_GLOBAL_STATE_RESETTING: > + return "resetting"; > + case SLPC_GLOBAL_STATE_RUNNING: > + return "running"; > + case SLPC_GLOBAL_STATE_SHUTTING_DOWN: > + return "shutting down"; > + case SLPC_GLOBAL_STATE_ERROR: > + return "error"; > + default: > + return "unknown"; > + } > +} > + > +static const char *slpc_get_state_string(struct intel_guc_slpc *slpc) > +{ > + return slpc_global_state_to_string(slpc_get_state(slpc)); > +} > + > +static int guc_action_slpc_reset(struct intel_guc *guc, u32 offset) > +{ > + u32 request[] = { > + GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST, > + SLPC_EVENT(SLPC_EVENT_RESET, 2), > + offset, > + 0, > + }; > + int ret; > + > + ret = intel_guc_send(guc, request, ARRAY_SIZE(request)); > + > + return ret > 0 ? -EPROTO : ret; > +} > + > +static int slpc_reset(struct intel_guc_slpc *slpc) > +{ > + struct drm_i915_private *i915 = slpc_to_i915(slpc); > + struct intel_guc *guc = slpc_to_guc(slpc); > + u32 offset = intel_guc_ggtt_offset(guc, slpc->vma); > + int ret; > + > + ret = guc_action_slpc_reset(guc, offset); > + > + if (unlikely(ret < 0)) { > + drm_err(&i915->drm, "SLPC reset action failed (%pe)\n", > + ERR_PTR(ret)); same here > + return ret; > + } > + > + if (!ret) { > + if (wait_for(slpc_is_running(slpc), SLPC_RESET_TIMEOUT_MS)) { > + drm_err(&i915->drm, "SLPC not enabled! State = %s\n", > + slpc_get_state_string(slpc)); > + return -EIO; > + } > + } > + > + return 0; > +} > + > int intel_guc_slpc_init(struct intel_guc_slpc *slpc) > { > GEM_BUG_ON(slpc->vma); > @@ -70,6 +219,83 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc) > return slpc_shared_data_init(slpc); > } > > +static u32 slpc_decode_min_freq(struct intel_guc_slpc *slpc) > +{ > + struct slpc_shared_data *data = slpc->vaddr; > + > + GEM_BUG_ON(!slpc->vma); > + > + return DIV_ROUND_CLOSEST( double space ^^ > + REG_FIELD_GET(SLPC_MIN_UNSLICE_FREQ_MASK, > + data->task_state_data.freq) * > + GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER); and here > +} > + > +static u32 slpc_decode_max_freq(struct intel_guc_slpc *slpc) > +{ > + struct slpc_shared_data *data = slpc->vaddr; > + > + GEM_BUG_ON(!slpc->vma); > + > + return DIV_ROUND_CLOSEST( double space ^^ > + REG_FIELD_GET(SLPC_MAX_UNSLICE_FREQ_MASK, > + data->task_state_data.freq) * > + GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER); > +} > + > +static void slpc_shared_data_reset(struct slpc_shared_data *data) > +{ > + memset(data, 0, sizeof(struct slpc_shared_data)); > + > + data->header.size = sizeof(struct slpc_shared_data); > + > + /* Enable only GTPERF task, disable others */ > + slpc_mem_set_enabled(data, SLPC_PARAM_TASK_ENABLE_GTPERF, > + SLPC_PARAM_TASK_DISABLE_GTPERF); > + > + slpc_mem_set_disabled(data, SLPC_PARAM_TASK_ENABLE_BALANCER, > + SLPC_PARAM_TASK_DISABLE_BALANCER); > + > + slpc_mem_set_disabled(data, SLPC_PARAM_TASK_ENABLE_DCC, > + SLPC_PARAM_TASK_DISABLE_DCC); > +} > + > +/* > + * intel_guc_slpc_enable() - Start SLPC > + * @slpc: pointer to intel_guc_slpc. > + * > + * SLPC is enabled by setting up the shared data structure and > + * sending reset event to GuC SLPC. Initial data is setup in > + * intel_guc_slpc_init. Here we send the reset event. We do > + * not currently need a slpc_disable since this is taken care > + * of automatically when a reset/suspend occurs and the GuC > + * CTB is destroyed. > + * > + * Return: 0 on success, non-zero error code on failure. > + */ > +int intel_guc_slpc_enable(struct intel_guc_slpc *slpc) > +{ > + struct drm_i915_private *i915 = slpc_to_i915(slpc); > + int ret; > + > + GEM_BUG_ON(!slpc->vma); > + > + slpc_shared_data_reset(slpc->vaddr); > + > + ret = slpc_reset(slpc); > + if (unlikely(ret < 0)) { > + drm_err(&i915->drm, "SLPC Reset event returned (%pe)\n", > + ERR_PTR(ret)); > + return ret; > + } > + > + ret = slpc_query_task_state(slpc); > + if (unlikely(ret < 0)) > + return ret; > + > + return 0; > +} > + > void intel_guc_slpc_fini(struct intel_guc_slpc *slpc) > { > if (!slpc->vma) > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h > index 8bd753167234..3cefe19b17b2 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h > @@ -8,6 +8,8 @@ > > #include > > +#define SLPC_RESET_TIMEOUT_MS 5 > + > struct intel_guc_slpc { > struct i915_vma *vma; > struct slpc_shared_data *vaddr; > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c > index e6bd9406c7b2..3e0cd1f05e3b 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c > @@ -500,12 +500,21 @@ static int __uc_init_hw(struct intel_uc *uc) > if (intel_uc_uses_guc_submission(uc)) > intel_guc_submission_enable(guc); > > + if (intel_uc_uses_guc_slpc(uc)) { > + ret = intel_guc_slpc_enable(&guc->slpc); > + if (ret) > + goto err_submission; > + } > + > drm_info(&i915->drm, "%s firmware %s version %u.%u %s:%s\n", > intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_GUC), guc->fw.path, > guc->fw.major_ver_found, guc->fw.minor_ver_found, > "submission", > enableddisabled(intel_uc_uses_guc_submission(uc))); > > + drm_info(&i915->drm, "GuC SLPC: %s\n", > + enableddisabled(intel_uc_uses_guc_slpc(uc))); > + > if (intel_uc_uses_huc(uc)) { > drm_info(&i915->drm, "%s firmware %s version %u.%u %s:%s\n", > intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_HUC), > @@ -520,6 +529,8 @@ static int __uc_init_hw(struct intel_uc *uc) > /* > * We've failed to load the firmware :( > */ > +err_submission: > + intel_guc_submission_disable(guc); > err_log_capture: > __uc_capture_load_err_log(uc); > err_out: > make sure checkpatch.pl is happy with indents, with that Reviewed-by: Michal Wajdeczko From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.4 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D235C432BE for ; Thu, 29 Jul 2021 15:48:20 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 06DEC60F43 for ; Thu, 29 Jul 2021 15:48:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 06DEC60F43 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 429AE6EDD6; Thu, 29 Jul 2021 15:48:17 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id CDDA16EDD3; Thu, 29 Jul 2021 15:48:15 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10060"; a="212904242" X-IronPort-AV: E=Sophos;i="5.84,278,1620716400"; d="scan'208";a="212904242" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jul 2021 08:48:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,278,1620716400"; d="scan'208";a="476443785" Received: from irvmail001.ir.intel.com ([10.43.11.63]) by fmsmga008.fm.intel.com with ESMTP; 29 Jul 2021 08:48:12 -0700 Received: from [10.249.142.82] (mwajdecz-MOBL.ger.corp.intel.com [10.249.142.82]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id 16TFmBTa024751; Thu, 29 Jul 2021 16:48:11 +0100 To: Vinay Belgaumkar , intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org References: <20210728211144.15322-1-vinay.belgaumkar@intel.com> <20210728211144.15322-6-vinay.belgaumkar@intel.com> From: Michal Wajdeczko Message-ID: <3848937b-9364-e3c6-b25f-72bafd5383cf@intel.com> Date: Thu, 29 Jul 2021 17:48:11 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Firefox/78.0 Thunderbird/78.12.0 MIME-Version: 1.0 In-Reply-To: <20210728211144.15322-6-vinay.belgaumkar@intel.com> Content-Language: en-US Subject: Re: [Intel-gfx] [PATCH 05/14] drm/i915/guc/slpc: Enable SLPC and add related H2G events X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 28.07.2021 23:11, Vinay Belgaumkar wrote: > Add methods for interacting with GuC for enabling SLPC. Enable > SLPC after GuC submission has been established. GuC load will > fail if SLPC cannot be successfully initialized. Add various > helper methods to set/unset the parameters for SLPC. They can > be set using H2G calls or directly setting bits in the shared > data structure. > > v2: Address several review comments, add new helpers for > decoding the SLPC min/max frequencies. Use masks instead of hardcoded > constants. (Michal W) > > v3: Split global_state_to_string function, and check for positive > non-zero return value from intel_guc_send() (Michal W) > > v4: Optimize the stringify function and other comments (Michal W) > > v5: Enable slpc as well before declaring GuC submission status (Michal W) > > Signed-off-by: Vinay Belgaumkar > Signed-off-by: Sundaresan Sujaritha > --- > drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 226 ++++++++++++++++++ > .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 2 + > drivers/gpu/drm/i915/gt/uc/intel_uc.c | 11 + > 3 files changed, 239 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c > index 6d76ea4c0ace..da3e1f8844a9 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c > @@ -45,6 +45,40 @@ void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc) > slpc->selected = __guc_slpc_selected(guc); > } > > +static void slpc_mem_set_param(struct slpc_shared_data *data, > + u32 id, u32 value) > +{ > + GEM_BUG_ON(id >= SLPC_MAX_OVERRIDE_PARAMETERS); > + /* > + * When the flag bit is set, corresponding value will be read > + * and applied by SLPC. > + */ > + data->override_params.bits[id >> 5] |= (1 << (id % 32)); > + data->override_params.values[id] = value; > +} > + > +static void slpc_mem_set_enabled(struct slpc_shared_data *data, > + u8 enable_id, u8 disable_id) > +{ > + /* > + * Enabling a param involves setting the enable_id > + * to 1 and disable_id to 0. > + */ > + slpc_mem_set_param(data, enable_id, 1); > + slpc_mem_set_param(data, disable_id, 0); > +} > + > +static void slpc_mem_set_disabled(struct slpc_shared_data *data, > + u8 enable_id, u8 disable_id) > +{ > + /* > + * Disabling a param involves setting the enable_id > + * to 0 and disable_id to 1. > + */ > + slpc_mem_set_param(data, disable_id, 1); > + slpc_mem_set_param(data, enable_id, 0); > +} > + > static int slpc_shared_data_init(struct intel_guc_slpc *slpc) > { > struct intel_guc *guc = slpc_to_guc(slpc); > @@ -63,6 +97,121 @@ static int slpc_shared_data_init(struct intel_guc_slpc *slpc) > return err; > } > > +static u32 slpc_get_state(struct intel_guc_slpc *slpc) > +{ > + struct slpc_shared_data *data; > + > + GEM_BUG_ON(!slpc->vma); > + > + drm_clflush_virt_range(slpc->vaddr, sizeof(u32)); > + data = slpc->vaddr; > + > + return data->header.global_state; > +} > + > +static bool slpc_is_running(struct intel_guc_slpc *slpc) > +{ > + return slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING; > +} > + > +static int guc_action_slpc_query(struct intel_guc *guc, u32 offset) > +{ > + u32 request[] = { > + GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST, > + SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2), > + offset, > + 0, > + }; > + int ret; > + > + ret = intel_guc_send(guc, request, ARRAY_SIZE(request)); > + > + return ret > 0 ? -EPROTO : ret; > +} > + > +static int slpc_query_task_state(struct intel_guc_slpc *slpc) > +{ > + struct intel_guc *guc = slpc_to_guc(slpc); > + struct drm_i915_private *i915 = slpc_to_i915(slpc); > + u32 offset = intel_guc_ggtt_offset(guc, slpc->vma); > + int ret; > + > + ret = guc_action_slpc_query(guc, offset); > + if (ret) unlikely(ret) ? > + drm_err(&i915->drm, "Failed to query task state (%pe)\n", > + ERR_PTR(ret)); is this indent correct ? > + > + drm_clflush_virt_range(slpc->vaddr, SLPC_PAGE_SIZE_BYTES); > + > + return ret; > +} > + > +static const char *slpc_global_state_to_string(enum slpc_global_state state) > +{ > + switch (state) { > + case SLPC_GLOBAL_STATE_NOT_RUNNING: > + return "not running"; > + case SLPC_GLOBAL_STATE_INITIALIZING: > + return "initializing"; > + case SLPC_GLOBAL_STATE_RESETTING: > + return "resetting"; > + case SLPC_GLOBAL_STATE_RUNNING: > + return "running"; > + case SLPC_GLOBAL_STATE_SHUTTING_DOWN: > + return "shutting down"; > + case SLPC_GLOBAL_STATE_ERROR: > + return "error"; > + default: > + return "unknown"; > + } > +} > + > +static const char *slpc_get_state_string(struct intel_guc_slpc *slpc) > +{ > + return slpc_global_state_to_string(slpc_get_state(slpc)); > +} > + > +static int guc_action_slpc_reset(struct intel_guc *guc, u32 offset) > +{ > + u32 request[] = { > + GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST, > + SLPC_EVENT(SLPC_EVENT_RESET, 2), > + offset, > + 0, > + }; > + int ret; > + > + ret = intel_guc_send(guc, request, ARRAY_SIZE(request)); > + > + return ret > 0 ? -EPROTO : ret; > +} > + > +static int slpc_reset(struct intel_guc_slpc *slpc) > +{ > + struct drm_i915_private *i915 = slpc_to_i915(slpc); > + struct intel_guc *guc = slpc_to_guc(slpc); > + u32 offset = intel_guc_ggtt_offset(guc, slpc->vma); > + int ret; > + > + ret = guc_action_slpc_reset(guc, offset); > + > + if (unlikely(ret < 0)) { > + drm_err(&i915->drm, "SLPC reset action failed (%pe)\n", > + ERR_PTR(ret)); same here > + return ret; > + } > + > + if (!ret) { > + if (wait_for(slpc_is_running(slpc), SLPC_RESET_TIMEOUT_MS)) { > + drm_err(&i915->drm, "SLPC not enabled! State = %s\n", > + slpc_get_state_string(slpc)); > + return -EIO; > + } > + } > + > + return 0; > +} > + > int intel_guc_slpc_init(struct intel_guc_slpc *slpc) > { > GEM_BUG_ON(slpc->vma); > @@ -70,6 +219,83 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc) > return slpc_shared_data_init(slpc); > } > > +static u32 slpc_decode_min_freq(struct intel_guc_slpc *slpc) > +{ > + struct slpc_shared_data *data = slpc->vaddr; > + > + GEM_BUG_ON(!slpc->vma); > + > + return DIV_ROUND_CLOSEST( double space ^^ > + REG_FIELD_GET(SLPC_MIN_UNSLICE_FREQ_MASK, > + data->task_state_data.freq) * > + GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER); and here > +} > + > +static u32 slpc_decode_max_freq(struct intel_guc_slpc *slpc) > +{ > + struct slpc_shared_data *data = slpc->vaddr; > + > + GEM_BUG_ON(!slpc->vma); > + > + return DIV_ROUND_CLOSEST( double space ^^ > + REG_FIELD_GET(SLPC_MAX_UNSLICE_FREQ_MASK, > + data->task_state_data.freq) * > + GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER); > +} > + > +static void slpc_shared_data_reset(struct slpc_shared_data *data) > +{ > + memset(data, 0, sizeof(struct slpc_shared_data)); > + > + data->header.size = sizeof(struct slpc_shared_data); > + > + /* Enable only GTPERF task, disable others */ > + slpc_mem_set_enabled(data, SLPC_PARAM_TASK_ENABLE_GTPERF, > + SLPC_PARAM_TASK_DISABLE_GTPERF); > + > + slpc_mem_set_disabled(data, SLPC_PARAM_TASK_ENABLE_BALANCER, > + SLPC_PARAM_TASK_DISABLE_BALANCER); > + > + slpc_mem_set_disabled(data, SLPC_PARAM_TASK_ENABLE_DCC, > + SLPC_PARAM_TASK_DISABLE_DCC); > +} > + > +/* > + * intel_guc_slpc_enable() - Start SLPC > + * @slpc: pointer to intel_guc_slpc. > + * > + * SLPC is enabled by setting up the shared data structure and > + * sending reset event to GuC SLPC. Initial data is setup in > + * intel_guc_slpc_init. Here we send the reset event. We do > + * not currently need a slpc_disable since this is taken care > + * of automatically when a reset/suspend occurs and the GuC > + * CTB is destroyed. > + * > + * Return: 0 on success, non-zero error code on failure. > + */ > +int intel_guc_slpc_enable(struct intel_guc_slpc *slpc) > +{ > + struct drm_i915_private *i915 = slpc_to_i915(slpc); > + int ret; > + > + GEM_BUG_ON(!slpc->vma); > + > + slpc_shared_data_reset(slpc->vaddr); > + > + ret = slpc_reset(slpc); > + if (unlikely(ret < 0)) { > + drm_err(&i915->drm, "SLPC Reset event returned (%pe)\n", > + ERR_PTR(ret)); > + return ret; > + } > + > + ret = slpc_query_task_state(slpc); > + if (unlikely(ret < 0)) > + return ret; > + > + return 0; > +} > + > void intel_guc_slpc_fini(struct intel_guc_slpc *slpc) > { > if (!slpc->vma) > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h > index 8bd753167234..3cefe19b17b2 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h > @@ -8,6 +8,8 @@ > > #include > > +#define SLPC_RESET_TIMEOUT_MS 5 > + > struct intel_guc_slpc { > struct i915_vma *vma; > struct slpc_shared_data *vaddr; > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c > index e6bd9406c7b2..3e0cd1f05e3b 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c > @@ -500,12 +500,21 @@ static int __uc_init_hw(struct intel_uc *uc) > if (intel_uc_uses_guc_submission(uc)) > intel_guc_submission_enable(guc); > > + if (intel_uc_uses_guc_slpc(uc)) { > + ret = intel_guc_slpc_enable(&guc->slpc); > + if (ret) > + goto err_submission; > + } > + > drm_info(&i915->drm, "%s firmware %s version %u.%u %s:%s\n", > intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_GUC), guc->fw.path, > guc->fw.major_ver_found, guc->fw.minor_ver_found, > "submission", > enableddisabled(intel_uc_uses_guc_submission(uc))); > > + drm_info(&i915->drm, "GuC SLPC: %s\n", > + enableddisabled(intel_uc_uses_guc_slpc(uc))); > + > if (intel_uc_uses_huc(uc)) { > drm_info(&i915->drm, "%s firmware %s version %u.%u %s:%s\n", > intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_HUC), > @@ -520,6 +529,8 @@ static int __uc_init_hw(struct intel_uc *uc) > /* > * We've failed to load the firmware :( > */ > +err_submission: > + intel_guc_submission_disable(guc); > err_log_capture: > __uc_capture_load_err_log(uc); > err_out: > make sure checkpatch.pl is happy with indents, with that Reviewed-by: Michal Wajdeczko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx